JP2855882B2 - Circuit board and method of manufacturing the same - Google Patents

Circuit board and method of manufacturing the same

Info

Publication number
JP2855882B2
JP2855882B2 JP3120977A JP12097791A JP2855882B2 JP 2855882 B2 JP2855882 B2 JP 2855882B2 JP 3120977 A JP3120977 A JP 3120977A JP 12097791 A JP12097791 A JP 12097791A JP 2855882 B2 JP2855882 B2 JP 2855882B2
Authority
JP
Japan
Prior art keywords
electrode
layer
silver
glass substrate
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3120977A
Other languages
Japanese (ja)
Other versions
JPH04348587A (en
Inventor
禎志 中村
昇 毛利
康晴 福井
進 稲継
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3120977A priority Critical patent/JP2855882B2/en
Publication of JPH04348587A publication Critical patent/JPH04348587A/en
Application granted granted Critical
Publication of JP2855882B2 publication Critical patent/JP2855882B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は電子機器、特にハイブリ
ッドＩＣに使用する回路基板およびその製造方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board for use in electronic equipment, particularly a hybrid IC, and a method for manufacturing the same.

【０００２】[0002]

【従来の技術】図４は従来の回路基板の断面図である。
図４において１１は上面に導体配線１２を施したガラス
基板である。１３はガラス基板１１上の導体配線１２に
接続され、周縁部がオーバーコート１４に重合されるよ
うに設けた電極である。１５は電極１３の上面に設けら
れた半田層である。2. Description of the Related Art FIG. 4 is a sectional view of a conventional circuit board.
In FIG. 4, reference numeral 11 denotes a glass substrate provided with a conductor wiring 12 on the upper surface. Reference numeral 13 denotes an electrode which is connected to the conductor wiring 12 on the glass substrate 11 and is provided so that the peripheral portion is overlapped with the overcoat 14. Reference numeral 15 denotes a solder layer provided on the upper surface of the electrode 13.

【０００３】以下、上記従来の回路基板の製造方法につ
いて説明する。まず、ガラス基板１１をアルカリ洗浄剤
で超音波洗浄した後、十分に乾燥させたガラス基板１１
上に銅、銀、または、インジウムテインオキサイドのい
ずれかよりなる導体配線１２を印刷し焼成して形成す
る。Hereinafter, a method for manufacturing the above-mentioned conventional circuit board will be described. First, the glass substrate 11 was ultrasonically cleaned with an alkali cleaning agent, and then dried sufficiently.
A conductive wiring 12 made of any of copper, silver, and indium tin oxide is printed and baked thereon.

【０００４】次に、導体配線１２の一部と接続されるよ
うに銀、銅のいずれかを印刷し焼成して電極１３を形成
する。Next, silver or copper is printed and baked so as to be connected to a part of the conductor wiring 12 to form an electrode 13.

【０００５】次に、電極１３の周縁部と重合するように
オーバーコート１４を印刷し焼成する。[0005] Next, the overcoat 14 is printed and baked so as to be superposed on the periphery of the electrode 13.

【０００６】最後に、電極１３の上面に半田層１５を設
けて回路基板を製造していた。Finally, a circuit board is manufactured by providing a solder layer 15 on the upper surface of the electrode 13.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら上記従来
の構成では、半田層１５、電極１３、ガラス基板１１の
それぞれにおける熱膨張係数が大きく異なるため、特に
一番密着力の弱い電極１３とガラス基板１１の界面に応
力が集中して、剥離しやすくガラス基板１１との密着強
度が劣化しやすいという課題を有していた。However, in the above-mentioned conventional structure, since the thermal expansion coefficients of the solder layer 15, the electrode 13, and the glass substrate 11 are largely different from each other, particularly, the electrode 13 having the weakest adhesion and the glass substrate 11 Has a problem that stress is concentrated on the interface of the glass substrate 11 and the adhesive strength with the glass substrate 11 is easily deteriorated.

【０００８】また、電極１３の周縁部と重合するように
オーバーコート１４を印刷し、焼成して形成することに
より、オーバーコート１４が電極１３に浸透して、電極
１３の表面での半田ぬれ性が損なわれ、半田球ができや
すくなり、半田層１５を介して他の電子部品を実装した
際に剥離しやすいという課題を有していた。Further, by printing and baking the overcoat 14 so as to be superposed on the peripheral portion of the electrode 13, the overcoat 14 penetrates the electrode 13 and the solder wettability on the surface of the electrode 13. However, there is a problem that solder balls are easily formed, and are easily separated when another electronic component is mounted via the solder layer 15.

【０００９】本発明は上記従来の課題を解決するもの
で、電極とガラス基板の界面において応力を分散させる
ことにより界面剥離を防ぎ、かつ、電極表面での半田ぬ
れ性の向上した回路基板およびその製造方法を提供する
ことを目的とする。The present invention solves the above-mentioned conventional problems, and disperses stress at an interface between an electrode and a glass substrate to prevent separation of the interface and to improve the solder wettability on the electrode surface, and a circuit board having the same. It is intended to provide a manufacturing method.

【００１０】[0010]

【課題を解決するための手段】この目的を達成するため
に本発明の回路基板は、上面に導体配線を施したガラス
基板と、このガラス基板上の前記導体配線に接続される
ように少なくとも銅、銀、銀ーパラジウムのいずれかの
金属粉体と熱硬化系樹脂を混合してなる第１層の電極
と、前記第１層の電極の周縁部に重合するように基板上
に形成したオーバーコートと、前記第１層の電極の上面
に電気的に接続されるように少なくとも銅、銀、銀−パ
ラジウムのいづれかの金属粉体と熱硬化系樹脂を混合し
てなる第２層の電極を備え、前記第２層の電極の上面に
他の電子部品を半田実装する半田層を有した構成であ
り、その製造方法は、ガラス基板の上面に導体配線を印
刷し焼成して形成する工程と、前記導体配線に接続され
るように少なくとも銅、銀、銀−パラジウムのいずれか
の金属粉体と熱硬化系樹脂を混合してなるペーストで第
１層の電極を形成する工程と、前記第１層の電極の周縁
部に重合するようにガラス基板上にオーバーコートを印
刷し硬化して形成する工程と、前記第１層の電極の上面
に電気的に接続されるように少なくとも銅、銀、銀−パ
ラジウムのいずれかの金属粉体と熱硬化系樹脂を混合し
て第２層の電極を形成する工程と、前記第２層の電極の
上面に他の電子部品を半田実装する半田層を形成する工
程とを有している。In order to achieve this object, a circuit board according to the present invention comprises a glass substrate provided with a conductor wiring on an upper surface, and at least copper which is connected to the conductor wiring on the glass substrate. A first layer electrode formed by mixing a metal powder of any of silver, silver and silver-palladium with a thermosetting resin, and an overcoat formed on a substrate so as to be polymerized on the periphery of the first layer electrode And a second layer electrode formed by mixing at least a metal powder of copper, silver, or silver-palladium and a thermosetting resin so as to be electrically connected to the upper surface of the first layer electrode. Having a solder layer for solder mounting another electronic component on the upper surface of the electrode of the second layer, the manufacturing method includes the steps of printing and firing conductive wiring on the upper surface of the glass substrate, At least copper to be connected to the conductor wiring Forming a first layer electrode with a paste obtained by mixing a metal powder of either silver or silver-palladium and a thermosetting resin; and forming a glass so as to polymerize on the periphery of the first layer electrode. Printing and curing an overcoat on the substrate, and heating at least one of copper, silver and silver-palladium metal powder so as to be electrically connected to the upper surface of the first layer electrode. The method includes a step of forming a second layer electrode by mixing a curable resin, and a step of forming a solder layer for solder mounting another electronic component on the upper surface of the second layer electrode.

【００１１】[0011]

【作用】従って本発明によれば、少なくとも銅、銀、銀
−パラジウムのいずれかの金属粉体と熱硬化系樹脂を混
合してなる第１層の電極および第２層の電極との電極２
層構造にすることにより、この相互で応力を受けとめ、
緩衝し、分散させる。そして、ガラス基板上の第１層の
電極に熱硬化系樹脂を混入して形成することにより、耐
熱および耐湿特性に優れ、ガラス基板との密着性が増
す。Therefore, according to the present invention, the electrode 2 of the first layer and the second layer formed by mixing at least a metal powder of copper, silver or silver-palladium with a thermosetting resin.
By having a layer structure, this mutual stress is received,
Buffer and disperse. By forming the first layer electrode on the glass substrate by mixing the thermosetting resin, the heat resistance and the moisture resistance are excellent, and the adhesion to the glass substrate is increased.

【００１２】また、上面に半田層を設ける第２層の電極
は、オーバーコートと重合する部分がないので、オーバ
ーコートを吸収し浸透させることはない。Further, since the second layer electrode provided with the solder layer on the upper surface has no portion that overlaps with the overcoat, it does not absorb and penetrate the overcoat.

【００１３】[0013]

【実施例】【Example】

（実施例１）以下本発明の一実施例について、図面を参
照しながら説明する。(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

【００１４】図１は本発明の回路基板の断面図である。
図１において、１は上面に導体配線２を施したガラス基
板で、この導体配線２に接続されるように少なくとも
銅、銀、銀−パラジウムのいずれかの金属粉体と熱硬化
系樹脂を混合してなる第１層の電極３が設けてある。さ
らに、この第１層の電極３の周縁部に重合するようにガ
ラス基板１上にオーバーコート４が設けてある。５は第
１層の電極３の上面に電気的に接続された少なくとも
銅、銀、銀−パラジウムのいずれかの金属粉体と熱硬化
系樹脂を混合してなる第二層の電極で、その第二層の電
極５の上面に他の電子部品を半田実装する半田層６が設
けてある。FIG. 1 is a sectional view of a circuit board according to the present invention.
In FIG. 1, reference numeral 1 denotes a glass substrate having an upper surface provided with a conductor wiring 2, and at least a metal powder of copper, silver, or silver-palladium mixed with a thermosetting resin so as to be connected to the conductor wiring 2. A first layer electrode 3 is provided. Further, an overcoat 4 is provided on the glass substrate 1 so as to overlap with the periphery of the electrode 3 of the first layer. Reference numeral 5 denotes a second-layer electrode formed by mixing at least one of copper, silver, and silver-palladium metal powder electrically connected to the upper surface of the first-layer electrode 3 and a thermosetting resin. On the upper surface of the second layer electrode 5, a solder layer 6 for soldering another electronic component is provided.

【００１５】以上のように構成された回路基板の製造方
法について説明する。まず、図２（ａ）に示すように、
ガラス基板１をアルカリ洗浄剤で超音波洗浄した後、十
分に乾燥させたガラス基板１上に銀で導体配線２を印刷
し焼成して形成する。A description will be given of a method of manufacturing the circuit board configured as described above. First, as shown in FIG.
After the glass substrate 1 is ultrasonically cleaned with an alkali cleaning agent, the conductor wiring 2 is printed with silver on the sufficiently dried glass substrate 1 and baked to form the same.

【００１６】次に、図２（ｂ）に示すように、導体配線
２の一部と接続されるようにフェノール系熱硬化型銀ペ
ースト（ＥＬＥＣＴＲＯ−ＳＣＩＥＮＣＥ ＬＡＢＯＲ
ＡＴＯＲＩＥＳ，ＩＮＣ．社製１１０９−Ｓ）をスクリ
ーン印刷し、温度２２０℃で２時間、熱硬化して第１層
の電極３を形成する。このとき、第１層の電極３の面積
抵抗を低くすることや、未硬化部分を完全になくして硬
化後の樹脂の経時変化や、熱的に不安定な要素を取り除
く必要があるので、比較的高温（製造元推奨温度：１５
０℃）で硬化しなければならない。Next, as shown in FIG. 2B, a phenol-based thermosetting silver paste (ELECTRO-SCIENCE LABOR) is connected so as to be connected to a part of the conductor wiring 2.
ATORIES, INC. 1109-S) is screen-printed and thermally cured at a temperature of 220 ° C. for 2 hours to form the first layer electrode 3. At this time, it is necessary to lower the sheet resistance of the electrode 3 of the first layer, completely remove the uncured portion, change the cured resin with time, and remove thermally unstable elements. High temperature (manufacturer recommended temperature: 15
(0 ° C.).

【００１７】次に、図２（ｃ）に示すように、オーバー
コート４を印刷し硬化する。これは、導体配線２で用い
た銀配線の銀移行を防止するために施すものである。Next, as shown in FIG. 2C, the overcoat 4 is printed and cured. This is to prevent the silver wiring used in the conductor wiring 2 from migrating to silver.

【００１８】次に、図２（ｄ）に示すように、半田付け
電極部としてフェノール系熱硬化型銅ペーストを第１層
の電極３と電気的に接続されるように印刷して、温度１
５０℃で３０分間、熱硬化して第２層の電極５を形成す
る。この第２層の電極５と第１層の電極３とは、物理的
かつ化学的なアンカー効果で結合されているため、接続
界面で電極剥離を生じることはない。Next, as shown in FIG. 2D, a phenolic thermosetting copper paste is printed as a soldering electrode portion so as to be electrically connected to the electrode 3 of the first layer.
Heat curing at 50 ° C. for 30 minutes to form the second layer electrode 5. Since the electrode 5 of the second layer and the electrode 3 of the first layer are connected by a physical and chemical anchor effect, the electrode does not peel off at the connection interface.

【００１９】最後に、図１に示すように第２層の電極３
の上面に他の電子部品を半田実装する半田層６を設けて
回路基板が完成する。Finally, as shown in FIG.
The circuit board is completed by providing a solder layer 6 for soldering other electronic components on the upper surface of the circuit board.

【００２０】また、下記にこの製造方法で作られた回路
基板の耐候性に関するプレッシャークッカー試験（１３
３℃、３気圧、５時間）の結果を図３に示す。A pressure cooker test (13) concerning the weather resistance of a circuit board manufactured by this manufacturing method is described below.
(3 ° C., 3 atm, 5 hours) are shown in FIG.

【００２１】図３より明らかなように、本発明の回路基
板は、従来に比べて明らかに耐候性が優れていることが
わかる。As is clear from FIG. 3, the circuit board of the present invention is clearly superior in weather resistance to the conventional one.

【００２２】（実施例２）以下本発明の他の実施例の回
路基板について説明する。(Embodiment 2) A circuit board according to another embodiment of the present invention will be described below.

【００２３】実施例２の構成は実施例１と同様のため説
明は省略する。本実施例２の製造方法は、実施例１の図
２（ｄ）で示したように、半田付け電極部としてフェノ
ール系熱硬化型銅ペーストを第１層の電極３と電気的に
接続されるように印刷して、温度１５０℃で３０分間、
熱硬化して第２層の電極５を形成したが、ここで用いた
銅電極は半田付けが良好である反面、酸化しやすく、基
板のままでの長期保存ができず、両面実装基板の場合リ
フロー半田付けの際に半田のない面の銅電極が酸化して
しまう等の問題があり、それを解決するためになされた
ものである。本第２の実施例では、第２層の電極５をフ
ェノール系熱硬化型銀ペースト（ＥＬＥＣＴＲＯ−ＳＣ
ＩＥＮＣＥ ＬＡＢＯＲＡＴＯＲＩＥＳ，ＩＮＣ．社製
１１１０−Ｓ）を第１層の電極３と電気的に接続される
ように印刷して、温度１５０℃で３０分間熱硬化して形
成し、前述した問題点である電極表面の酸化を防止し
た。この第２層の電極５と第１層の電極３とは、物理的
かつ化学的なアンカー効果で結合されたいるため、接続
界面で電極剥離を生じることはない。しかし、この第２
層の電極５に用いた銀ペーストは、第１層の電極３に用
いた銀ペーストよりも銀含有量が多いため銀拡散（銀と
スズの共晶現象）が生じるため半田付けが良好であると
はいえないが、銀拡散防止用半田（千住金属工業株式会
社製ＳＰＴ７３−Ｅ１２０−Ｍ１０）を用いることによ
り改善することができる。Since the configuration of the second embodiment is the same as that of the first embodiment, the description is omitted. In the manufacturing method of the second embodiment, as shown in FIG. 2D of the first embodiment, a phenolic thermosetting copper paste is electrically connected to the first layer electrode 3 as a soldering electrode portion. Print at 150 ° C for 30 minutes,
Although the electrode 5 of the second layer was formed by thermosetting, the copper electrode used here was good in soldering, but was easily oxidized and could not be stored for a long time as a substrate. There is a problem that the copper electrode on the surface without solder is oxidized at the time of reflow soldering, and this is made to solve the problem. In the second embodiment, the electrode 5 of the second layer is formed of a phenol-based thermosetting silver paste (ELECTRO-SC).
IENCE LABORATORIES, INC. 1110-S) is printed so as to be electrically connected to the electrode 3 of the first layer, and formed by thermosetting at a temperature of 150 ° C. for 30 minutes. Prevented. Since the electrode 5 of the second layer and the electrode 3 of the first layer are to be bonded by a physical and chemical anchor effect, electrode separation does not occur at the connection interface. However, this second
The silver paste used for the electrode 5 of the layer has a higher silver content than the silver paste used for the electrode 3 of the first layer, so that silver diffusion (a eutectic phenomenon of silver and tin) occurs, so that the soldering is good. However, it can be improved by using a solder for preventing silver diffusion (SPT73-E120-M10 manufactured by Senju Metal Industry Co., Ltd.).

【００２４】[0024]

【発明の効果】以上のように本発明は、ガラス基板上の
導体配線に接続されるように形成した少なくとも銅、
銀、銀−パラジウムのいずれかの金属粉体と熱硬化系樹
脂を混合してなる第１層の電極と、第１層の電極の上面
に電気的に接続されように少なくとも銅、銀、銀−パラ
ジウムのいずれかの金属粉体と熱硬化系樹脂を混合して
なる第２層の電極とによる電極の２層構造とすることに
より、電極とガラス基板の界面で剥離しにくく、ガラス
基板との密着強度を向上させ、耐候性および半田ぬれ性
の優れた回路基板およびその製造方法を提供することが
できる。As described above, according to the present invention, at least copper formed so as to be connected to conductor wiring on a glass substrate,
A first layer electrode formed by mixing a metal powder of any of silver and silver-palladium with a thermosetting resin; and at least copper, silver, and silver so as to be electrically connected to the upper surface of the first layer electrode. -The electrode has a two-layer structure including a metal powder of any of palladium and a second-layer electrode formed by mixing a thermosetting resin, so that it is difficult to peel off at the interface between the electrode and the glass substrate, To improve the adhesion strength of the circuit board, and provide a circuit board having excellent weather resistance and solder wettability, and a method for manufacturing the same.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の回路基板の一実施例を示す断面図FIG. 1 is a sectional view showing one embodiment of a circuit board of the present invention.

【図２】（ａ）〜（ｄ）は同回路基板の製造方法の一実
施例を示す各工程の断面図2 (a) to 2 (d) are cross-sectional views of respective steps showing one embodiment of a method of manufacturing the circuit board.

【図３】本発明と従来の回路基板の耐候性特性比較図FIG. 3 is a comparison diagram of the weather resistance characteristics of the present invention and a conventional circuit board.

【図４】従来の回路基板の断面図FIG. 4 is a cross-sectional view of a conventional circuit board.

【符号の説明】[Explanation of symbols]

１ ガラス基板 ２ 導体配線 ３ 第１層の電極 ４ オーバーコート ５ 第２層の電極 ６ 半田層 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Conductor wiring 3 1st layer electrode 4 Overcoat 5 2nd layer electrode 6 Solder layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 稲継 進 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 昭63−38287（ＪＰ，Ａ) 特開 平２−191394（ＪＰ，Ａ) 特開 平２−39588（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H05K 3/24 H05K 3/34 501────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Susumu Inazushi 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-63-38287 (JP, A) JP-A-2- 191394 (JP, A) JP-A-2-39588 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H05K 3/24 H05K 3/34 501

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】上面に導体配線を施したガラス基板と、こ
のガラス基板上の前記導体配線に接続されるように形成
した少なくとも銅、銀、銀ーパラジウムのいずれかの金
属粉体と熱硬化系樹脂を混合してなる第１層の電極と、
前記第１層の電極の周縁部に重合するように基板上に形
成したオーバーコートと、前記第１層の電極の上面に電
気的に接続されるように少なくとも銅、銀、銀ーパラジ
ウムのいずれかの金属粉体と熱硬化系樹脂を混合してな
る第２層の電極を備え、前記第２層の電極の上面に他の
電子部品を半田実装する半田層を有することを特徴とす
る回路基板。1. A glass substrate having an upper surface provided with a conductor wiring, and at least one metal powder of copper, silver, silver-palladium formed so as to be connected to the conductor wiring on the glass substrate, and a thermosetting system. A first layer electrode formed by mixing a resin;
An overcoat formed on the substrate so as to overlap the peripheral portion of the first layer electrode; and at least one of copper, silver, and silver-palladium so as to be electrically connected to the upper surface of the first layer electrode. A second layer electrode formed by mixing a metal powder and a thermosetting resin, and a solder layer for mounting another electronic component by soldering on the upper surface of the second layer electrode. . 【請求項２】ガラス基板の上面に導体配線を印刷し焼成
して形成する工程と、前記導体配線に接続されるように
少なくとも銅、銀、銀−パラジウムのいずれかの金属粉
体と熱硬化系樹脂を混合してなるペーストを印刷し硬化
して第１層の電極を形成する工程と、前記第１層の電極
の周縁部に重合するようにガラス基板上にオーバーコー
トを印刷し硬化して形成する工程と、前記第１層の電極
の上面に電気的に接続されるように少なくとも銅、銀、
銀−パラジウムのいずれかの金属粉体と熱硬化系樹脂を
混合してなるペーストを印刷し硬化して第２層の電極を
形成する工程と、前記第２層の電極の上面に他の電子部
品を半田実装する半田層を形成する工程とからなる回路
基板の製造方法。2. A step of printing and firing conductive wiring on the upper surface of a glass substrate, and thermosetting with at least one of copper, silver, and silver-palladium metal powder so as to be connected to the conductive wiring. Printing and curing a paste obtained by mixing the base resin to form an electrode of the first layer, and printing and curing an overcoat on a glass substrate so as to polymerize on the periphery of the electrode of the first layer. Forming at least copper, silver, and the like so as to be electrically connected to the upper surface of the electrode of the first layer.
A step of printing and curing a paste obtained by mixing any one of silver-palladium metal powder and a thermosetting resin to form a second layer electrode; and forming another electron on the upper surface of the second layer electrode. Forming a solder layer for mounting components by soldering.
JP3120977A 1991-05-27 1991-05-27 Circuit board and method of manufacturing the same Expired - Fee Related JP2855882B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3120977A JP2855882B2 (en) 1991-05-27 1991-05-27 Circuit board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3120977A JP2855882B2 (en) 1991-05-27 1991-05-27 Circuit board and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH04348587A JPH04348587A (en) 1992-12-03
JP2855882B2 true JP2855882B2 (en) 1999-02-10

Family

ID=14799728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3120977A Expired - Fee Related JP2855882B2 (en) 1991-05-27 1991-05-27 Circuit board and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2855882B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4066522B2 (en) 1998-07-22 2008-03-26 イビデン株式会社 Printed wiring board
JP5018250B2 (en) * 2007-06-04 2012-09-05 富士電機株式会社 Semiconductor device and manufacturing method thereof
JP5220766B2 (en) * 2007-12-26 2013-06-26 株式会社フジクラ Mounting board

Also Published As

Publication number Publication date
JPH04348587A (en) 1992-12-03

Similar Documents

Publication Publication Date Title
KR0142178B1 (en) Electric circuit board module and method for producing electric circuit board module
EP0249755A2 (en) Hybrid integrated circuit apparatus
US5886457A (en) Sealing structure and method of sealing electronic component
JPH0621627A (en) Mounting of electric parts on circuit board
JP2855882B2 (en) Circuit board and method of manufacturing the same
JPS63310581A (en) Film body for electric connection
JPS60108822A (en) Terminal connecting method of liquid crystal display element
JPH0210571B2 (en)
WO1997030461A1 (en) Resistor network in ball grid array package
US5219607A (en) Method of manufacturing printed circuit board
JP2000022070A (en) Electronic part having bump and its manufacture
JP2961859B2 (en) Multilayer ceramic substrate
JPH11177016A (en) Composite integrated circuit device
JPH06124850A (en) Laminated composite electronic component
JPH09260822A (en) Structure for connecting/fixing electronic part to board with solder
JPH0982835A (en) Circuit substrate and multilayer circuit substrate
JP2003133473A (en) Wiring board
JPH0751807Y2 (en) Flexible circuit board
JPH0543311B2 (en)
JPH0547485Y2 (en)
JP3418874B2 (en) Multilayer composite electronic components
JP2000200953A (en) Mounting structure and mounting method of electronic components
JP3065013B2 (en) Circuit board and circuit pattern forming method
EP0375954B1 (en) Method of manufacturing printed circuit board
JP2842707B2 (en) Circuit board

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees