JP2713517B2 - Differential amplifier circuit - Google Patents
Differential amplifier circuitInfo
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- JP2713517B2 JP2713517B2 JP3259465A JP25946591A JP2713517B2 JP 2713517 B2 JP2713517 B2 JP 2713517B2 JP 3259465 A JP3259465 A JP 3259465A JP 25946591 A JP25946591 A JP 25946591A JP 2713517 B2 JP2713517 B2 JP 2713517B2
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- JP
- Japan
- Prior art keywords
- source
- constant current
- power supply
- fet
- voltage
- Prior art date
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- Logic Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＧａＡｓＦＥＴ等のＦ
ＥＴ（電界効果トランジスタ）を用いたソース・カップ
ルドＦＥＴロジック回路（以下、ＳＣＦＬ回路という）
等で構成される差動増幅回路、特に電流の導通／遮断機
能を持つ定電流源を備えた差動増幅回路に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention
Source-coupled FET logic circuit using ET (field effect transistor) (hereinafter referred to as SCFL circuit)
More particularly, the present invention relates to a differential amplifier circuit having a constant current source having a current conduction / cutoff function.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば次のような文献に記載されるものがあった。 文献；昭和６１年度電子通信学会総合全国大会予稿集４
１９、首藤 他「ＧａＡｓ ＬＳＣＦＬ 縦積みゲート
の基本特性」Ｐ．２−１７７ 図２は、前記文献に記載された従来のＳＣＦＬ回路で構
成される差動増幅回路の一構成例を示す回路図である。
この差動増幅回路は、入力信号Ｉ１を入力する入力端子
１、その逆相入力信号Ｉ２を入力する入力端子２、出力
信号Ｏ１を出力する出力端子３、及びその逆相出力信号
Ｏ２を出力する出力端子４、高電位側の電源電圧Ｖｄ１
が印加される電源端子５、及び低電位側の電源電圧Ｖｓ
ｓ１が印加される電源端子６を有している。そして、入
力信号Ｉ１，Ｉ２によりゲート制御される一対の駆動用
ＦＥＴ１１，１２が設けられ、その各ドレインが出力端
子３，４にそれぞれ接続されると共に、一対の負荷抵抗
１３，１４を介して電源端子５に接続されている。各駆
動用ＦＥＴ１１，１２のソースが共通接続され、その共
通ソースが定電流源２０に接続されている。定電流源２
０は、電流の導通／遮断機能を有し、ドレインが前記共
通ソースに、ソースが電源端子６にそれぞれ接続され、
制御電圧Ｖｃ１によりゲート制御される定電流源用ＦＥ
Ｔ２１で構成されている。2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. References: Proceedings of IEEJ General Conference, 1986 4
19, Shuto et al., "Basic Characteristics of GaAs LSCFL Vertically Stacked Gates" 2-177 FIG. 2 is a circuit diagram showing a configuration example of a differential amplifier circuit constituted by a conventional SCFL circuit described in the above document.
This differential amplifier circuit outputs an input terminal 1 for inputting an input signal I1, an input terminal 2 for receiving an inverted-phase input signal I2, an output terminal 3 for outputting an output signal O1, and an inverted-phase output signal O2. Output terminal 4, power supply voltage Vd1 on high potential side
Is applied to the power supply terminal 5 and the power supply voltage Vs on the low potential side.
It has a power supply terminal 6 to which s1 is applied. A pair of driving FETs 11 and 12 whose gates are controlled by the input signals I1 and I2 are provided, the drains of which are connected to the output terminals 3 and 4, respectively, and a power supply is connected via a pair of load resistors 13 and 14. Connected to terminal 5. The sources of the driving FETs 11 and 12 are commonly connected, and the common source is connected to the constant current source 20. Constant current source 2
0 has a current conduction / interruption function, a drain is connected to the common source, and a source is connected to the power supply terminal 6, respectively.
FE for constant current source gate-controlled by control voltage Vc1
It is composed of T21.
【０００３】次に、動作を説明する。まず、制御電圧Ｖ
ｃ１がＦＥＴ２１の閾値電圧Ｖｔｈより十分高いとき、
該ＦＥＴ２１が導通状態となり、定電流源として動作す
る。２つの入力信号Ｉ１とＩ２の論理レベルがそれぞれ
“Ｈ”，“Ｌ”のときは、駆動用ＦＥＴ１１，１２がそ
れぞれオン，オフとなり、電源電圧Ｖｄ１からの電源電
流Ｉｄ１が負荷抵抗１３を流れる。すると、出力信号Ｏ
１及び逆相出力信号Ｏ２の論理レベルがそれぞれ
“Ｌ”，“Ｈ”となる。また、２つの入力信号Ｉ１，Ｉ
２がそれぞれ“Ｌ”，“Ｈ”のときは、前記と同様にし
て出力信号Ｏ１及び逆相出力信号Ｏ２の論理レベルがそ
れぞれ“Ｈ”，“Ｌ”となる。制御電圧Ｖｃ１が定電流
源用ＦＥＴ２１の閾値電圧Ｖｔｈより十分低いとき、Ｆ
ＥＴ２１が遮断状態となり、電源電流Ｉｄ１がほとんど
流れなくなって該差動増幅回路の消費電力が抑制され
る。Next, the operation will be described. First, the control voltage V
When c1 is sufficiently higher than the threshold voltage Vth of the FET 21,
The FET 21 becomes conductive and operates as a constant current source. When the logic levels of the two input signals I1 and I2 are "H" and "L", respectively, the driving FETs 11 and 12 are turned on and off, respectively, and the power supply current Id1 from the power supply voltage Vd1 flows through the load resistor 13. Then, the output signal O
The logic levels of 1 and the inverted output signal O2 become "L" and "H", respectively. Also, two input signals I1, I
When 2 is "L" and "H", respectively, the logic levels of the output signal O1 and the inverted-phase output signal O2 become "H" and "L", respectively, as described above. When the control voltage Vc1 is sufficiently lower than the threshold voltage Vth of the constant current source FET 21, F
ET21 is cut off, power supply current Id1 hardly flows, and power consumption of the differential amplifier circuit is suppressed.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記構
成の回路では、電源電流Ｉｄ１の導通／遮断は制御電圧
Ｖｃ１によって定電流源用ＦＥＴ２１のゲート・ソース
間電圧を制御することにより行われる。そのため、制御
電圧Ｖｃ１がノイズによって不安定となったり、あるい
は該制御電圧Ｖｃ１を出力する制御回路における出力イ
ンピーダンスの変化等で該制御電圧Ｖｃ１が不安定とな
った場合、電源電流Ｉｄ１の電流値が大きく変化し、そ
れによって出力信号Ｏ１及び逆相出力信号Ｏ２の論理レ
ベルも大きく変化するという問題があり、それを比較的
簡単な回路構成で解決することが困難であった。本発明
は、前記従来技術が持っていた課題として、定電流源用
ＦＥＴのゲート・ソース間電圧で電流の導通／遮断を制
御する構成では、ノイズ等による制御電圧の変動に対し
て電流が変動し、出力信号の論理レベルが大きく変動す
るという点について解決した差動増幅回路を提供するも
のである。However, in the circuit having the above configuration, the conduction / cut-off of the power supply current Id1 is performed by controlling the gate-source voltage of the constant current source FET 21 by the control voltage Vc1. Therefore, when the control voltage Vc1 becomes unstable due to noise, or when the control voltage Vc1 becomes unstable due to a change in output impedance in a control circuit that outputs the control voltage Vc1, the current value of the power supply current Id1 becomes There is a problem that the logic level greatly changes, and accordingly, the logic levels of the output signal O1 and the negative-phase output signal O2 also greatly change, and it has been difficult to solve this with a relatively simple circuit configuration. The present invention has a problem that the conventional technology has a problem in that in the configuration in which the conduction / interruption of the current is controlled by the gate-source voltage of the constant current source FET, the current fluctuates with respect to the fluctuation of the control voltage due to noise or the like. It is another object of the present invention to provide a differential amplifier circuit that solves the problem that the logic level of an output signal fluctuates greatly.
【０００５】[0005]
【課題を解決するための手段】第１の発明は、前記課題
を解決するために、ソースが共通接続され、２つの入力
信号によりそれぞれオン，オフ動作する一対の駆動用Ｆ
ＥＴと、前記一対の駆動用ＦＥＴの各ドレインと高電位
側の電源電圧との間にそれぞれ接続された一対の負荷抵
抗と、前記一対の駆動用ＦＥＴの共通ソースと低電位側
の電源電圧との間に接続され、定電流の導通／遮断機能
を持つ定電流源とを、備えた差動増幅回路において、前
記定電流源を次のように構成している。即ち、前記定電
流源は、ドレインが前記共通ソースに接続され、制御電
圧によってゲート制御される制御用ＦＥＴと、ドレイン
が前記制御用ＦＥＴのソースに、ソースが前記低電位側
の電源電圧に、ゲートが固定電圧または該低電位側の電
源電圧にそれぞれ接続された定電流源用ＦＥＴとで、構
成している。第２の発明は、第１の発明において、ドレ
インが前記高電位側の電源電圧にそれぞれ接続され、前
記一対の駆動用ＦＥＴの各ドレイン電圧によってそれぞ
れゲート制御される一対の出力バッファ用ソースホロワ
ＦＥＴと、一方の電極が前記各ソースホロワＦＥＴのソ
ースに直接またはレベルシフタを介してそれぞれ接続さ
れ、他方の電極が前記低電位側の電源電圧にそれぞれ接
続され、前記定電流源と同一構成の２つの出力バッファ
用定電流源とを、設けている。According to a first aspect of the present invention, in order to solve the above-mentioned problems, a pair of driving Fs whose sources are commonly connected and which are turned on and off by two input signals respectively are provided.
ET, a pair of load resistors respectively connected between the drains of the pair of driving FETs and the power supply voltage on the high potential side, and a common source of the pair of driving FETs and the power supply voltage on the low potential side. And a constant current source having a function of conducting / cutting off a constant current in the differential amplifier circuit, wherein the constant current source is configured as follows. That is, the constant current source has a drain connected to the common source, a control FET whose gate is controlled by a control voltage, a drain connected to the source of the control FET, and a source connected to the power supply voltage on the low potential side. A constant current source FET whose gate is connected to the fixed voltage or the power supply voltage on the low potential side, respectively. According to a second aspect, in the first aspect, a pair of output buffer source follower FETs, each having a drain connected to the power supply voltage on the high potential side and having a gate controlled by each drain voltage of the pair of driving FETs, , One of the electrodes is connected to the source of each of the source follower FETs directly or via a level shifter, and the other electrode is connected to the low-potential-side power supply voltage, respectively. And a constant current source.
【０００６】[0006]
【作用】第１の発明によれば、以上のように差動増幅回
路を構成したので、定電流源用ＦＥＴに直列接続した制
御用ＦＥＴのゲート・ソース間を制御電圧で制御すれ
ば、定電流源の電流の導通／遮断が行え、その電流の導
通時に定電流特性の安定性が向上する。第２の発明によ
れば、出力バッファ用定電流源は、駆動用ＦＥＴ側の定
電流源と同一回路で構成されているので、該出力バッフ
ァ用定電流源を構成する制御用ＦＥＴにより、該出力バ
ッファ用定電流源の電流の導通／遮断を行い、導通時に
おける定電流特性の安定性の向上が図れる。従って、前
記課題を解決できるのである。According to the first aspect of the present invention, since the differential amplifier circuit is constructed as described above, if the gate-source of the control FET connected in series with the constant current source FET is controlled by the control voltage, the constant Conduction / interruption of the current of the current source can be performed, and stability of the constant current characteristic is improved when the current is conducted. According to the second invention, the constant current source for the output buffer is constituted by the same circuit as the constant current source on the driving FET side. Therefore, the constant current source for the output buffer is controlled by the control FET constituting the constant current source for the output buffer. Conduction / interruption of the current of the output buffer constant current source is performed, and the stability of the constant current characteristic during conduction is improved. Therefore, the above problem can be solved.
【０００７】[0007]
【実施例】第１の実施例 図１は、本発明の第１の実施例を示すＳＣＦＬ回路で構
成される差動増幅回路の回路図である。この差動増幅回
路は、入力信号Ｉ１１を入力する入力端子３１、その逆
相入力信号Ｉ１２を入力する入力端子３２、出力信号Ｏ
１１を出力する出力端子３３、その逆相出力信号Ｏ１２
を出力する出力端子３４、高電位側の電源電圧Ｖｄ１１
を印加する電源端子３５、及び低電位側の電源電圧Ｖｓ
ｓ１１を印加す電源端子３６を有している。そして、入
力信号Ｉ１１及び逆相入力信号Ｉ１２によりオン，オフ
動作する一対の駆動用ＦＥＴ４１，４２が設けられてい
る。EXAMPLES First Embodiment FIG. 1 is a circuit diagram of a differential amplifier circuit constituted by SCFL circuit showing a first embodiment of the present invention. This differential amplifier circuit has an input terminal 31 for inputting an input signal I11, an input terminal 32 for inputting its inverted-phase input signal I12, and an output signal O.
11, an output terminal 33 for outputting an output signal O12
Output terminal 34 for outputting the power supply voltage Vd11 on the high potential side
And a power supply voltage Vs on the low potential side.
It has a power supply terminal 36 for applying s11. Further, a pair of driving FETs 41 and 42 that are turned on and off by the input signal I11 and the negative-phase input signal I12 are provided.
【０００８】各ＦＥＴ４１，４２のドレインは、出力端
子３３，３４に接続されると共に、一対の負荷抵抗４
３，４４を介して電源端子３５に接続されている。各駆
動用ＦＥＴ４１，４２のソースは共通接続され、その共
通ソースが定電流源５０を介して電源端子３６に接続さ
れている。定電流源５０は、電源端子３５から流れる電
源電流Ｉｄ１１を導通／遮断する機能を有し、ノーマリ
オフ型の制御用ＦＥＴ５１、及びノーマリオン型の定電
流源用ＦＥＴ５２より構成されている。制御用ＦＥＴ５
１は、制御電圧Ｖｃ１１によってゲート制御されるトラ
ンジスタであり、そのドレインがＦＥＴ４１，４２の共
通ソースに接続され、そのソースが定電流源用ＦＥＴ５
２のドレインに接続されている。ＦＥＴ５２のゲートは
ソースに接続され、そのソースが電源端子３６に接続さ
れている。The drains of the FETs 41 and 42 are connected to output terminals 33 and 34, and a pair of load resistors 4
It is connected to the power supply terminal 35 via 3 and 44. The sources of the driving FETs 41 and 42 are commonly connected, and the common source is connected to the power supply terminal 36 via the constant current source 50. The constant current source 50 has a function of conducting / cutting off a power supply current Id11 flowing from the power supply terminal 35, and includes a normally-off type control FET 51 and a normally-on type constant current source FET 52. Control FET5
Reference numeral 1 denotes a transistor whose gate is controlled by a control voltage Vc11, the drain of which is connected to a common source of the FETs 41 and 42, and the source of which is a constant current source FET5.
2 drain. The gate of the FET 52 is connected to the source, and the source is connected to the power supply terminal 36.
【０００９】次に、動作を説明する。まず、制御電圧Ｖ
ｃ１１が十分高いときには、制御用ＦＥＴ５１がオン
し、電源端子３５から電源電流Ｉｄ１１が流れる。この
とき、２つの入力信号Ｉ１１，Ｉ１２がそれぞれ
“Ｈ”，“Ｌ”ならば、一対の駆動用ＦＥＴ４１，４２
がそれぞれオン，オフとなり、電源端子３５から電源電
流Ｉｄ１１が負荷抵抗４３に流れる。そのため、出力信
号Ｏ１１及び逆相出力信号Ｏ１２の論理レベルは、それ
ぞれ“Ｌ”，“Ｈ”となる。また、２つの入力信号Ｉ１
１，Ｉ１２の論理レベルが“Ｌ”，“Ｈ”であれば、出
力信号Ｏ１１及び逆相出力信号Ｏ１２が“Ｈ”，“Ｌ”
となる。制御電圧Ｖｃ１１を電位Ｖｓｓ（＝０Ｖ）まで
低くすると、ＦＥＴ５２のドレインとＦＥＴ５１のゲー
トとの間の電圧が０Ｖに近くなり、電源電流Ｉｄ１１が
流れなくなる。Next, the operation will be described. First, the control voltage V
When c11 is sufficiently high, the control FET 51 is turned on, and the power supply current Id11 flows from the power supply terminal 35. At this time, if the two input signals I11 and I12 are "H" and "L", respectively, a pair of driving FETs 41 and 42 are provided.
Are turned on and off, respectively, and the power supply current Id11 flows from the power supply terminal 35 to the load resistor 43. Therefore, the logic levels of the output signal O11 and the inverted-phase output signal O12 are “L” and “H”, respectively. Also, two input signals I1
1 and I12 are “L” and “H”, the output signal O11 and the negative-phase output signal O12 are “H” and “L”.
Becomes When the control voltage Vc11 is lowered to the potential Vss (= 0V), the voltage between the drain of the FET 52 and the gate of the FET 51 approaches 0V, and the power supply current Id11 stops flowing.
【００１０】この第１の実施例の利点を、図３を参照し
つつ説明する。図３は、本実施例の図１の回路と従来の
図２の回路との電源電流Ｉｄ１，Ｉｄ１１の制御電圧Ｖ
ｃ１，Ｖｃ１１依存特性を、コンピュータを用いてシミ
ュレーションした結果を示す図である。本実施例の回路
と従来の回路とは共に制御電圧Ｖｃ１，Ｖｃ１１をＶｓ
ｓ（＝０Ｖ）レベルまで低くすると、電源電流Ｉｄ１，
Ｉｄ１１が２５〜４０μＡまで小さくなる。そのため、
本実施例の回路が、電源電流Ｉｄ１１の導通／遮断機能
を持つことがわかる。The advantages of the first embodiment will be described with reference to FIG. FIG. 3 shows the control voltage V of the power supply currents Id1 and Id11 of the circuit of FIG. 1 of this embodiment and the conventional circuit of FIG.
FIG. 14 is a diagram illustrating a result of simulating the c1 and Vc11 dependence characteristics using a computer. In both the circuit of the present embodiment and the conventional circuit, the control voltages Vc1 and Vc11 are set to Vs
s (= 0V) level, the power supply current Id1,
Id11 decreases to 25-40 μA. for that reason,
It can be seen that the circuit of this embodiment has a function of conducting / cutting off the power supply current Id11.
【００１１】例えば、電流導通時の消費電流設計値が２
００μＡとする。すると、図３より、従来の図２の回路
では制御電圧Ｖｃ１を０．２７Ｖに、本実施例の図１の
回路では制御電圧Ｖｃ１１を０．８Ｖにすれば良いこと
がわかる。ここで、前記の動作点電圧における電流の電
圧に対する変化率ΔＩｄ／ΔＶｃを求めると、次のよう
になる。 従来の回路： ΔＩｄ１／ΔＶｃ１〜０．９（ｍＡ／Ｖ） 本実施例の回路： ΔＩｄ１１／ΔＶｃ１１〜０．０５（ｍＡ／Ｖ） 本実施例の回路では、従来の回路と比較して、制御電圧
Ｖｃ１１のレベル変動に対する電流変動が１／１８であ
る。また、電流変動と負荷抵抗４３，４４の積で表わさ
れる出力信号Ｏ１１及び逆相出力信号Ｏ１２の論理レベ
ルの変動も、１／１８に抑えられることがわかる。従っ
て、制御電圧Ｖｃ１１がノイズや、該制御電圧生成用の
制御回路の出力インピーダンスの変化等で、不安定とな
っても、電流導通時の電流変動を小さくできる。さら
に、定電流源用ＦＥＴ５２のドレイン側に制御用ＦＥＴ
５１を直列に接続しているので、該ＦＥＴ５２のドレイ
ン電圧をＦＥＴ５１の制御電圧Ｖｃ１１で制御できる。
そのため、定電流源用ＦＥＴ５２のドレイン電圧上昇に
よるドレイン電流の増加や降伏を防ぐことができる。 For example, the design value of the current consumption when the current is conducted is 2
00 μA. Then, it is understood from FIG. 3 that the control voltage Vc1 should be set to 0.27 V in the conventional circuit of FIG. 2, and the control voltage Vc11 should be set to 0.8 V in the circuit of FIG. Here, the rate of change ΔId / ΔVc of the current at the operating point voltage with respect to the voltage is obtained as follows. Conventional circuit: ΔId1 / ΔVc1 to 0.9 (mA / V) Circuit of the present embodiment: ΔId11 / ΔVc11 to 0.05 (mA / V) In the circuit of the present embodiment, compared with the conventional circuit, The current fluctuation with respect to the level fluctuation of the voltage Vc11 is 1/18. It can also be seen that the fluctuations in the logic levels of the output signal O11 and the negative-phase output signal O12, which are expressed by the product of the current fluctuation and the load resistances 43 and 44, can be suppressed to 1/18. Therefore, even if the control voltage Vc11 becomes unstable due to noise, a change in the output impedance of the control circuit for generating the control voltage, or the like, the current fluctuation at the time of current conduction can be reduced. Further, a control FET is connected to the drain of the constant current source FET 52.
Since the FETs 51 are connected in series, the drain voltage of the FET 52 can be controlled by the control voltage Vc11 of the FET 51.
Therefore, it is possible to prevent an increase and a breakdown of the drain current due to an increase in the drain voltage of the constant current source FET 52 .
【００１２】第２の実施例 図４は、本発明の第２の実施例を示すＳＣＦＬ回路で構
成される差動増幅回路の回路図であり、図１中の要素と
共通の要素には共通の符号が付されている。この差動増
幅回路では、図１の差動増幅回路に、ソースホロワバッ
ファを接続している。ソースホロワバッファは、一対の
ソースホロワ用ＦＥＴ６１，６２、ダイオード等で構成
される一対のレベルシフタ６３，６４、及び一対の定電
流源５０−１，５０−２を備えている。各ソースホロワ
用ＦＥＴ６１，６２は、各駆動用ＦＥＴ４１，４２のド
レイン電圧によってオン，オフ動作するトランジスタで
あり、その各ドレインが電源端子３５にそれぞれ接続さ
れ、そのソースが出力端子３３，３４にそれぞれ接続さ
れている。各出力端子３３，３４には、レベルシフタ６
３，６４がそれぞれ接続され、その各レベルシフタ６
３，６４が定電流源５０−１，５０−２をそれぞれ介し
て電源端子３６に接続されている、定電流源５０−１，
５０−２は、図１の定電流源５０と同様に、制御電圧Ｖ
ｃ１１によってゲート制御されるノーマリオフ型の制御
用ＦＥＴ５１−１，５１−２と、ノーマリオン型の定電
流源用ＦＥＴ５２−１，５２−２とで、それぞれ構成さ
れている。 Second Embodiment FIG. 4 is a circuit diagram of a differential amplifier circuit composed of an SCFL circuit according to a second embodiment of the present invention. The elements common to those in FIG. Are given. In this differential amplifier circuit, a source follower buffer is connected to the differential amplifier circuit of FIG. The source-follower buffer includes a pair of source-follower FETs 61 and 62, a pair of level shifters 63 and 64 including diodes and the like, and a pair of constant current sources 50-1 and 50-2. Each of the source follower FETs 61 and 62 is a transistor that is turned on and off by the drain voltage of each of the driving FETs 41 and 42, and has its drain connected to the power supply terminal 35 and its source connected to the output terminals 33 and 34, respectively. Have been. Each output terminal 33, 34 has a level shifter 6
3 and 64 are connected to each other and each level shifter 6
3 and 64 are connected to the power terminal 36 via the constant current sources 50-1 and 50-2, respectively.
50-2 is a control voltage V, similar to the constant current source 50 of FIG.
It comprises normally-off type control FETs 51-1 and 51-2 gate-controlled by c11 and normally-on type constant current source FETs 52-1 and 52-2.
【００１３】この差動増幅回路では、駆動用ＦＥＴ４
１，４２のドレイン電圧によってソースホロワ用ＦＥＴ
６１，６２がオン，オフ動作し、それに応じた出力信号
Ｏ１１及び逆相出力信号Ｏ１２が出力端子３３，３４か
らそれぞれ出力される。この出力信号Ｏ１１及び逆相出
力信号Ｏ１２は、レベルシフタ６３，６４によって所定
の電圧レベルにレベルシフトされる。この差動増幅回路
においても、ソースホロワ用ＦＥＴ６１，６２に定電流
源５０−１，５０−２をそれぞれ設けたので、制御電圧
Ｖｃ１１によって制御用ＦＥＴ５１−１，５１−２がオ
ン，オフ動作し、電源電流の導通／遮断が行え、電流導
通時にはソースホロワバッファ側で安定な定電流特性が
得られる。In this differential amplifier circuit, the driving FET 4
FET for source follower by drain voltage of 1,42
61 and 62 are turned on and off, and an output signal O11 and a negative-phase output signal O12 are output from the output terminals 33 and 34, respectively. The output signal O11 and the negative-phase output signal O12 are level-shifted to predetermined voltage levels by the level shifters 63 and 64. Also in this differential amplifier circuit, since the constant current sources 50-1 and 50-2 are provided in the source follower FETs 61 and 62, the control FETs 51-1 and 51-2 are turned on and off by the control voltage Vc11. Power supply current can be turned on / off, and a stable constant current characteristic can be obtained on the source follower buffer side when the current is turned on.
【００１４】なお、本発明は上記実施例に限定されず、
種々の変形が可能である。その変形例としては、例えば
次のようなものがある。 （ａ） 図１及び図４において、制御用ＦＥＴ５１，５
１−１，５１−２をノーマリオン型ＦＥＴで構成した
り、あるいは定電流源用ＦＥＴ５２，５２−１，５２−
２をノーマリオフ型ＦＥＴで構成しても良い。この際、
制御電圧Ｖｃ１１の極性をそれに応じて変えれば良い。 （ｂ ） 図４の差動増幅回路において、駆動用ＦＥＴ４
１，４２及び入力端子３１，３２を複数個設けることに
より、複数入力のノア回路等といった他の論理回路を構
成することも可能である。 （ｃ） 図１及び図４の定電流源用ＦＥＴ５２，５２−
１，５２−２のゲートを固定電圧端子に接続しても、上
記実施例と同様の作用、効果が得られる。The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (A) In FIGS. 1 and 4 , the control FETs 51, 5
1-1 and 51-2 may be composed of normally-on type FETs, or constant current source FETs 52, 52-1, and 52-.
2 may be constituted by a normally-off type FET. On this occasion,
What is necessary is just to change the polarity of the control voltage Vc11 accordingly . (B) in the differential amplifier circuit of FIG. 4, the driving FET4
By providing a plurality of input terminals 1 and 42 and a plurality of input terminals 31 and 32, it is possible to configure another logic circuit such as a multiple-input NOR circuit. ( C ) The constant current source FETs 52, 52- shown in FIGS.
Even when the gates of the terminals 1 and 52-2 are connected to the fixed voltage terminals, the same operation and effect as those of the above embodiment can be obtained.
【００１５】[0015]
【発明の効果】以上詳細に説明したように、第１の発明
によれば、電流の導通／遮断機能を持つ定電流源を、制
御用ＦＥＴと定電流源用ＦＥＴとの直列回路で構成し、
該制御用ＦＥＴを制御電圧で制御するようにしたので、
制御電圧が、ノイズや、該制御電圧生成用の制御回路に
おける出力インピーダンスの変化等で不安定となって
も、電流導通時の電流変動を小さくできる。そのため、
比較的簡単な回路構成で、出力の論理レベルの変動を抑
制することができる。しかも、定電流源用ＦＥＴのドレ
イン側に制御用ＦＥＴを接続しているので、該定電流源
用ＦＥＴのドレイン電圧を、制御用ＦＥＴのゲートに印
加する制御電圧で制御できる。そのため、定電流源用Ｆ
ＥＴのドレイン電圧上昇によるドレイン電流の増加や降
伏を防止できる。As described above in detail, according to the first aspect, the constant current source having the current conducting / cutting function is constituted by a series circuit of the control FET and the constant current source FET. ,
Since the control FET is controlled by the control voltage,
Even if the control voltage becomes unstable due to noise, a change in the output impedance of the control voltage generation control circuit, or the like, the current fluctuation during current conduction can be reduced. for that reason,
With a relatively simple circuit configuration, it is possible to suppress a change in the logic level of the output. In addition, since the control FET is connected to the drain of the constant current source FET, the drain voltage of the constant current source FET can be controlled by the control voltage applied to the gate of the control FET. Therefore, the constant current source F
It is possible to prevent an increase in the drain current and a breakdown due to an increase in the drain voltage of the ET.
【００１６】第２の発明によれば、第１の発明の回路に
出力バッファ用ソースホロワＦＥＴと出力バッファ用定
電流源とを接続し、該出力バッファ用定電流源を駆動用
ＦＥＴ側の定電流源と同一の回路で構成している。その
ため、出力バッファ側についても、電流の導通／遮断機
能と安定な定電流特性が得られる。また、出力バッファ
用ソースホロワＦＥＴと出力バッファ用定電流源との間
にレベルシフタを設けた場合、該レベルシフタによって
出力レベルを任意の値にシフトすることが可能となる。According to the second invention, a source follower FET for an output buffer and a constant current source for an output buffer are connected to the circuit of the first invention, and the constant current source for the output buffer is connected to the constant current on the driving FET side. It consists of the same circuit as the source. Therefore, also on the output buffer side, a current conduction / cutoff function and stable constant current characteristics can be obtained. When a level shifter is provided between the output buffer source follower FET and the output buffer constant current source, the output level can be shifted to an arbitrary value by the level shifter.
【図１】本発明の第１の実施例を示す差動増幅回路の回
路図である。FIG. 1 is a circuit diagram of a differential amplifier circuit according to a first embodiment of the present invention.
【図２】従来の差動増幅回路の回路図である。FIG. 2 is a circuit diagram of a conventional differential amplifier circuit.
【図３】本実施例と従来とを比較するための電源電流の
制御電圧依存特性図である。FIG. 3 is a control voltage dependence characteristic diagram of a power supply current for comparing the present embodiment with a conventional example.
【図４】本発明の第２の実施例を示す差動増幅回路の回
路図である。 FIG. 4 is a circuit diagram of a differential amplifier circuit according to a second embodiment of the present invention .
４１，４２ 駆動用ＦＥＴ ４３，４４ 負荷抵抗 ５０，５１−１，５０−２ 定電流源 ５１，５１−１，５１−２ 制御用ＦＥＴ ５２，５２−１，５２−２ 定電流源用ＦＥＴ ６３，６４ レベルシフタ41, 42 Driving FET 43, 44 Load resistance 50 , 5 1-1 , 50-2 Constant current source 51, 51-1, 51-2 Control FET 52, 52-1, 52-2 FET for constant current source 63, 64 level shifter
Claims (2)
によりそれぞれオン，オフ動作する一対の駆動用ＦＥＴ
と、 前記一対の駆動用ＦＥＴの各ドレインと高電位側の電源
電圧との間にそれぞれ接続された一対の負荷抵抗と、 前記一対の駆動用ＦＥＴの共通ソースと低電位側の電源
電圧との間に接続され、定電流の導通／遮断機能を持つ
定電流源とを、備えた差動増幅回路において、 前記定電流源は、 ドレインが前記共通ソースに接続され、制御電圧によっ
てゲート制御される制御用ＦＥＴと、 ドレインが前記制御用ＦＥＴのソースに、ソースが前記
低電位側の電源電圧に、ゲートが固定電圧または該低電
位側の電源電圧にそれぞれ接続された定電流源用ＦＥＴ
とで、構成したことを特徴とする差動増幅回路。A pair of driving FETs whose sources are commonly connected and which are turned on and off by two input signals, respectively.
A pair of load resistors respectively connected between each drain of the pair of driving FETs and a power supply voltage on a high potential side; and a common source of the pair of driving FETs and a power supply voltage on a low potential side. A constant current source having a conduction / shutoff function of a constant current, the constant current source having a drain connected to the common source and being gate-controlled by a control voltage. A control FET, a constant current source FET having a drain connected to the source of the control FET, a source connected to the low potential side power supply voltage, and a gate connected to the fixed voltage or the low potential side power supply voltage, respectively.
A differential amplifier circuit comprising:
れ、前記一対の駆動用ＦＥＴの各ドレイン電圧によって
それぞれゲート制御される一対の出力バッファ用ソース
ホロワＦＥＴと、 一方の電極が前記各ソースホロワＦＥＴのソースに直接
またはレベルシフタを介してそれぞれ接続され、他方の
電極が前記低電位側の電源電圧にそれぞれ接続され、前
記定電流源と同一構成の２つの出力バッファ用定電流源
とを、設けたことを特徴とする差動増幅回路。2. A pair of output buffers according to claim 1, wherein drains are respectively connected to the power supply voltage on the high potential side, and a gate is controlled by each drain voltage of the pair of driving FETs. Source follower FET, one electrode is connected to the source of each of the source follower FETs directly or via a level shifter, and the other electrode is connected to the low potential side power supply voltage, respectively, and has the same configuration as the constant current source. A differential amplifier circuit comprising: two output buffer constant current sources.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3259465A JP2713517B2 (en) | 1991-10-07 | 1991-10-07 | Differential amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3259465A JP2713517B2 (en) | 1991-10-07 | 1991-10-07 | Differential amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102838A JPH05102838A (en) | 1993-04-23 |
| JP2713517B2 true JP2713517B2 (en) | 1998-02-16 |
Family
ID=17334454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3259465A Expired - Fee Related JP2713517B2 (en) | 1991-10-07 | 1991-10-07 | Differential amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2713517B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276921A (en) * | 1988-04-28 | 1989-11-07 | Fujitsu Ltd | Logic circuit |
| JPH03213016A (en) * | 1990-01-18 | 1991-09-18 | Sumitomo Electric Ind Ltd | Inverter circuit |
-
1991
- 1991-10-07 JP JP3259465A patent/JP2713517B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05102838A (en) | 1993-04-23 |
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