JP2712967B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2712967B2
JP2712967B2 JP3336791A JP33679191A JP2712967B2 JP 2712967 B2 JP2712967 B2 JP 2712967B2 JP 3336791 A JP3336791 A JP 3336791A JP 33679191 A JP33679191 A JP 33679191A JP 2712967 B2 JP2712967 B2 JP 2712967B2
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor device
wiring
plating layer
mounting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3336791A
Other languages
English (en)
Other versions
JPH05166967A (ja
Inventor
和文 寺地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3336791A priority Critical patent/JP2712967B2/ja
Publication of JPH05166967A publication Critical patent/JPH05166967A/ja
Application granted granted Critical
Publication of JP2712967B2 publication Critical patent/JP2712967B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置に関し、特に
プラスチック・ピン・グリッド・アレイ型の半導体装置
に関する。
【０００２】
【従来の技術】従来、この種の半導体装置は、半導体素
子搭載部とワイヤーボンディング部を有する印刷配線基
板上に半導体素子を搭載後、封止枠が樹脂で接着され、
エポキシ樹脂、シリコーン樹脂等の樹脂で封止後、封止
部を覆う様にアルミニウム製の金属キャップが樹脂で接
着されていた。
【０００３】
【発明が解決しようとする課題】しかしながら、上述し
た従来の半導体装置では、印刷配線基板上の銅配線部上
に封止枠が接着されているので、温度サイクルやＰＣＴ
（プレッシャー・クッカー・テスト）等の環境試験で印
刷配線が断線する不良があった。
【０００４】そこで、本発明の技術的課題は、上記欠点
に鑑み、環境試験等で印刷配線が断線することのない半
導体装置を提供することである。
【０００５】
【課題を解決するための手段】本発明によれば、印刷配
線基板が半導体素子搭載部と表面に印刷された配線部と
を有し、前記半導体素子搭載部に半導体素子を搭載し、
前記半導体素子と前記配線部とがワイヤボンディングに
て接続される半導体装置において、前記配線部は、銅配
線層とこの銅配線層のすべてを覆うニッケルめっき層及
び金めっき層とよりなり、かつ前記印刷配線基板の表面
は、前記半導体素子搭載部と前記配線部のうちの前記ワ
イヤボンディングにて接続される部分とを除いてソルダ
ーレジストにて覆われていることを特徴とする半導体装
置が得られる。
【０００６】また、本発明によれば、上記の半導体装置
において、前記印刷配線基板上を封止するための封止枠
を、少なくとも前記ニッケルめっき層及び金めっき層上
に配することを特徴とする半導体装置が得られる。
【０００７】即ち、本発明の半導体装置は、半導体素子
搭載部、ワイヤーボンディング部を有する印刷配線基板
上に半導体素子を搭載後、封止枠が樹脂で接着されてエ
ポキシ樹脂、シリコーン樹脂等の樹脂で封止後、封止部
を覆う様にアルミニウム製の金属キャップが樹脂で接着
されたプラスチック・ピン・グリッド・アレイ型の半導
体装置において、前記印刷配線基板上の銅配線上にニッ
ケル、金めっきを行なった後、半導体素子搭載部、ワイ
ヤーボンディング部以外の基板表面をエポキシ樹脂、ポ
リイミド樹脂等のソルダーレジストで被覆した構造とな
っている。
【０００８】
【実施例】次に本発明の実施例について図面を参照して
説明する。
【０００９】図１は本発明の一実施例の断面図である。
【００１０】半導体素子搭載部１、ワイヤーボンディン
グ部２を有し、エポキシ系ガラス布やポリイミド系ガラ
ス布やトリアジン系ガラス布等から成り、０．８〜３mm
厚の印刷配線基板３の印刷配線である銅配線４上にニッ
ケルめっき部６（５μm ）、金めっき部７（０．５μm
）を施した後、半導体搭載部１、ワイヤーボンディン
グ部２以外の基板表面をエポキシ樹脂、ポリイミド樹脂
等のソルダーレジスト５で被覆されている。このように
銅配線上にニッケル、金めっきを行なったことにより、
環境試験時の応力集中があってもめっきで補強されてい
るので信頼性を向上することができる。
【００１１】
【発明の効果】以上説明したように本発明は、樹脂で封
入される箇所の基板配線を銅配線のでなくニッケル、金
めっきを行ない補強することにより、封入樹脂と基板と
の熱膨張係数の差による配線の断線を防止し、環境試験
の信頼性が向上できるという効果がある。
【図面の簡単な説明】
【図１】本発明の一実施例の断面図。
【符号の説明】
１ 半導体素子搭載部 ２ ワイヤーボンディング部 ３ 印刷配線基板 ４ 銅配線 ５ ソルダーレジスト ６ ニッケルめっき部 ７ 金めっき部 ８ 半導体素子 ９ 封止樹脂 １０ 封止枠 １１ 金属キャップ １２ 外部リード端子

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】 印刷配線基板が半導体素子搭載部と表面
    に印刷された配線部とを有し、前記半導体素子搭載部に
    半導体素子を搭載し、前記半導体素子と前記配線部とが
    ワイヤボンディングにて接続される半導体装置におい
    て、 前記配線部は、銅配線層とこの銅配線層のすべてを覆う
    ニッケルめっき層及び金めっき層とよりなり、かつ前記
    印刷配線基板の表面は、前記半導体素子搭載部と前記配
    線部のうちの前記ワイヤボンディングにて接続される部
    分とを除いてソルダーレジストにて覆われている ことを
    特徴とする半導体装置。
  2. 【請求項２】 請求項１の半導体装置において、前記印
    刷配線基板上を封止するための封止枠を、少なくとも前
    記ニッケルめっき層及び金めっき層上に配することを特
    徴とする半導体装置。
JP3336791A 1991-12-19 1991-12-19 半導体装置 Expired - Lifetime JP2712967B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3336791A JP2712967B2 (ja) 1991-12-19 1991-12-19 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3336791A JP2712967B2 (ja) 1991-12-19 1991-12-19 半導体装置

Publications (2)

Publication Number Publication Date
JPH05166967A JPH05166967A (ja) 1993-07-02
JP2712967B2 true JP2712967B2 (ja) 1998-02-16

Family

ID=18302724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3336791A Expired - Lifetime JP2712967B2 (ja) 1991-12-19 1991-12-19 半導体装置

Country Status (1)

Country Link
JP (1) JP2712967B2 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6347037B2 (en) 1994-04-28 2002-02-12 Fujitsu Limited Semiconductor device and method of forming the same
JP3034180B2 (ja) * 1994-04-28 2000-04-17 富士通株式会社 半導体装置及びその製造方法及び基板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3122542U (ja) * 2006-04-05 2006-06-15 得欽 何 モップの構造

Also Published As

Publication number Publication date
JPH05166967A (ja) 1993-07-02

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