JP2691305B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP2691305B2 JP2691305B2 JP30860089A JP30860089A JP2691305B2 JP 2691305 B2 JP2691305 B2 JP 2691305B2 JP 30860089 A JP30860089 A JP 30860089A JP 30860089 A JP30860089 A JP 30860089A JP 2691305 B2 JP2691305 B2 JP 2691305B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- external lead
- lid
- lead terminal
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子を収容する半導体素子収納用パッ
ケージの改良に関するものである。Description: TECHNICAL FIELD The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor device.
（従来の技術） 従来、半導体素子を収容するためのパッケージ、特に
ガラスの溶着によって封止するガラス封止型半導体素子
収納用パッケージは、絶縁基体と蓋体とから成り、内部
に半導体素子を収容する空所を有する絶縁容器と、該容
器内に収容される半導体素子を外部電気回路に電気的に
接続するための外部リード端子とから構成されており、
絶縁基体及び蓋体の相対向する主面に予め封止用のガラ
ス部材を被着形成すると共に、絶縁基体主面に外部リー
ド端子を固定し、半導体素子の各電極と外部リード端子
とをワイヤボンド接続した後、絶縁基体及び蓋体のそれ
ぞに被着させた封止用のガラス部材を溶融一体化させる
ことによって内部に半導体素子を気密に封止している。(Prior Art) Conventionally, a package for accommodating a semiconductor element, particularly a package for accommodating a glass-encapsulated semiconductor element sealed by welding glass, includes an insulating base and a lid, and accommodates the semiconductor element inside. And an external lead terminal for electrically connecting a semiconductor element housed in the container to an external electric circuit,
A glass member for sealing is applied in advance on the opposing main surfaces of the insulating base and the lid, and external lead terminals are fixed on the main surface of the insulating base, and each electrode of the semiconductor element and the external lead terminal are wired. After the bond connection, the semiconductor element is hermetically sealed inside by fusing and integrating a sealing glass member attached to each of the insulating base and the lid.
（発明が解決しようとする課題） しかし乍ら、この従来のガラス封止型半導体素子収納
用パッケージは通常、外部リード端子がコバール（29Wt
％ Ni−16Wt％ Co−55Wt％Fe 合金）や42Alloy（42Wt％
Ni−58Wt％ Fe合金）の導電性材料から成っており、該
コバールや42Alloy等は透磁率が高く、且つ導電率が低
いことから以下に述べる欠点を有する。(Problems to be Solved by the Invention) However, this conventional package for housing a glass-sealed semiconductor element usually has an external lead terminal of Kovar (29 Wt).
% Ni-16Wt% Co-55Wt% Fe alloy) and 42Alloy (42Wt%
Ni-58Wt% Fe alloy), and Kovar and 42Alloy have the following disadvantages due to their high magnetic permeability and low electric conductivity.
即ち、 コバールや42Alloyは鉄（Fe）、ニッケル（Ni）、コ
バルト（Co）といった強磁性体金属のみから成ってお
り、その透磁率は250〜700（CGS）と高い。そのための
コバールや42Alloy等から成る外部リード端子に電流が
流れると外部リード端子中に透磁率に比例した大きな自
己インダクタンスが発生し、これが逆起電力を誘発して
ノイズとなると共に、該ノイズが半導体素子に入力され
て半導体素子に誤動作を生じさせる、 コバールや42Alloyはその導電率が3.0〜3.5％（IAC
S）と低い。そのためこのコバールや42Alloy等から成る
外部リード端子に信号を伝搬させた場合、信号の伝搬速
度が極めて遅いものとなり、高速駆動を行う半導体素子
はその収容が不可となってしまう、 半導体素子収納用パッケージの内部に収容する半導体
素子の高密度化、高集積化の進展に伴い、半導体素子の
電極数が大幅に増大しており、半導体素子の各電極を外
部電気回路に接続する外部リード端子の線幅も極めて細
くなってきている。そのため外部リード端子は上記に
記載のコバールや42Alloyの導電率が低いことと相俟っ
て電気抵抗が極めて大きなものになってきており、外部
リード端子に信号を伝搬させると、該外部リード端子の
電気抵抗に起因して信号が大きく減衰し、内部に収容す
る半導体素子に信号を正確に入力することができず、半
導体素子に誤動作を生じさせてしまう、 等の欠点を有していた。That is, Kovar and 42Alloy are made of only ferromagnetic metals such as iron (Fe), nickel (Ni), and cobalt (Co), and have high magnetic permeability of 250 to 700 (CGS). Therefore, when a current flows through the external lead terminal made of Kovar, 42 Alloy, etc., a large self-inductance proportional to the magnetic permeability is generated in the external lead terminal, which induces a counter electromotive force to become noise, and the noise is generated in the semiconductor. Kovar and 42 Alloy, which are input to the device and cause malfunctions in semiconductor devices, have a conductivity of 3.0 to 3.5% (IAC
S) and low. Therefore, when a signal is propagated to an external lead terminal made of Kovar or 42Alloy, the signal propagation speed becomes extremely slow, and semiconductor devices that perform high-speed driving cannot be accommodated. The number of electrodes of a semiconductor element has increased significantly with the progress of higher density and higher integration of semiconductor elements housed inside the semiconductor device, and wires of external lead terminals for connecting each electrode of the semiconductor element to an external electric circuit. The width has also become extremely narrow. Therefore, the external lead terminal has become extremely large in electric resistance in combination with the low conductivity of Kovar or 42Alloy described above, and when a signal is propagated to the external lead terminal, the external lead terminal The signal is greatly attenuated due to the electric resistance, the signal cannot be accurately input to the semiconductor element housed inside, and the semiconductor element has a malfunction.
（発明の目的） 本発明は上記欠点に鑑み案出されたもので、その目的
は外部リード端子で発生するノイズ及び外部リード端子
における信号の減衰を極小となし、内部に収容する半導
体素子への信号の入出力を確実に行うことを可能として
半導体素子を長期間にわたり正常、且つ安定に作動させ
ることができる半導体素子収納用パッケージを提供する
ことにある。(Object of the Invention) The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to minimize the noise generated at the external lead terminals and the signal attenuation at the external lead terminals to minimize the semiconductor device housed therein. An object of the present invention is to provide a package for housing a semiconductor element capable of reliably inputting / outputting a signal and allowing a semiconductor element to operate normally and stably for a long period of time.
また本発明の他の目的は高速駆動を行う半導体素子を
収容することができる半導体素子収納用パッケージを提
供することにある。Another object of the present invention is to provide a semiconductor element housing package capable of housing a semiconductor element which operates at high speed.
（課題を解決するための手段） 本発明は絶縁基体と蓋体とから成り、内部に半導体素
子を収容するための空所を有する絶縁容器と、該容器内
に収容される半導体素子を外部電気回路に接続するため
の外部リード端子とから成る半導体素子収納用パッケー
ジにおいて、前記絶縁基体及び蓋体をスピネルもしくは
ステアタイト質焼結体で、外部リード端子をインバー合
金から成る板状体の上下面に、該板状体の厚みに対し40
乃至60％の厚みの銅板を接合させた金属体で形成したこ
とを特徴とするものである。(Means for Solving the Problem) The present invention comprises an insulating container having an insulating base and a lid, and having a void space for housing a semiconductor element therein, and a semiconductor element housed in the container being electrically connected to an external electrical device. In a package for accommodating a semiconductor element, which comprises external lead terminals for connecting to a circuit, the insulating substrate and the lid are made of spinel or a steatite sintered body, and the external lead terminals are made of an invar alloy. The thickness of the plate is 40
It is characterized by being formed of a metal body in which copper plates having a thickness of 60% to 60% are joined.
（実施例） 次に本発明を添付図面に基づき詳細に説明する。(Example) Next, the present invention will be described in detail with reference to the accompanying drawings.
第１図及び第２図は本発明の半導体素子収納用パッケ
ージの一実施例を示し、１は絶縁基体、２は蓋体であ
る。この絶縁基体１と蓋体２とにより絶縁容器３が構成
される。1 and 2 show an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base and 2 is a lid. The insulating container 3 is constituted by the insulating base 1 and the lid 2.
前記絶縁基体１及び蓋体２はそれぞれの中央部に半導
体素子を収容する空所を形成するための凹部が設けてあ
り、絶縁基体１の凹部底面には半導体素子４が樹脂、ガ
ラス、ロウ剤等の接着剤を介し取着固定される。The insulating base 1 and the lid 2 are each provided with a concave portion for forming a space for accommodating a semiconductor element at the center thereof, and the semiconductor element 4 is formed of resin, glass, brazing agent on the bottom surface of the concave portion of the insulating base 1. It is attached and fixed via an adhesive such as.
前記絶縁基体１及び蓋体２はスピネルもしくはステア
タイト質焼結体から成り、第１図に示すような絶縁基体
１及び蓋体２に対応した形状を有するプレス型内に、ス
ピネルの場合はマグネシア（MgO）、アルミナ（Al2O3）
等の原料粉末を、ステアタイト質焼結体の場合はマグネ
シア（MgO）、シリカ（SiO2）等の原料粉末を充填させ
るとともに一定圧力を印加して成形し、しかる後、成形
品を約1200〜1700℃の温度で焼成することによって製作
される。The insulating substrate 1 and the lid body 2 are made of spinel or a steatite sintered body, and in a press die having a shape corresponding to the insulating substrate 1 and the lid body 2 as shown in FIG. (MgO), Alumina (Al 2 O 3 )
Raw material powder such as magnesia (MgO) or silica (SiO 2 ) in the case of a steatite sintered body, and molding by applying a constant pressure. It is manufactured by firing at a temperature of ~ 1700 ° C.
尚、前記絶縁基体１及び蓋体２を形成するスピネルも
しくはステアタイト質焼結体はその熱膨張係数が70〜85
×10-7/℃であり、後述する封止用ガラス部材の熱膨張
係数との関係において絶縁基体１及び蓋体２と封止用ガ
ラス部材間に大きな熱膨張の差が生じることはない。The spinel or steatite sintered body forming the insulating base 1 and the lid 2 has a coefficient of thermal expansion of 70 to 85.
× 10 −7 / ° C., and there is no large difference in thermal expansion between the insulating base 1 and the lid 2 and the sealing glass member in relation to the coefficient of thermal expansion of the sealing glass member described later.
また前記絶縁基体１及び蓋体２にはその相対向する主
面に封止用のガラス部材６が予め被着形成されており、
該絶縁基体１及び蓋体２の各々に被着されている封止用
ガラス部材６を加熱溶融させ一体化させることにより絶
縁容器３内の半導体素子４を気密に封止する。Further, a glass member 6 for sealing is previously formed on the opposing main surfaces of the insulating base 1 and the lid 2.
The semiconductor element 4 in the insulating container 3 is hermetically sealed by heating and melting the sealing glass member 6 attached to each of the insulating base 1 and the lid 2 to be integrated.
前記絶縁基体１及び蓋体２の相対向する主面に被着さ
れる封止用ガラス部材６は、例えばホウケイ酸鉛系ガラ
スにフィラーを添加したものから成り、原料粉末として
の酸化鉛（PbO）70.0〜90.0Wt％、酸化ホウ素（B2O3）1
2.0〜13.0Wt％、シリカ（SiO2）0.5〜3.0Wt％及びアル
ミナ（Al2O3）0.5〜3.0Wt％にフィラーとしてチタン酸
鉛（PbTiO3）、β−ユークリプタイト（Li2Al2Si
2O8）、コージライト（Mg2Al4Si5O18）、ジルコン（ZrS
iO4）、酸化スズ（SnO2）、ウイレマイト（Zn2SiO4）等
を15〜30Vol％添加混合すると共に、該混合粉末を950〜
1100℃の温度で加熱溶融させることによって製作され
る。このホウケイ酸鉛系のガラスはその熱膨張係数が60
〜90×10-7/℃である。The sealing glass member 6 attached to the opposing main surfaces of the insulating base 1 and the lid 2 is made of, for example, lead borosilicate glass to which a filler is added. ) 70.0~90.0Wt%, boron oxide (B 2 O 3) 1
2.0~13.0Wt%, silica (SiO 2) 0.5~3.0Wt% and alumina (Al 2 O 3) lead titanate as a filler 0.5~3.0Wt% (PbTiO 3), β- eucryptite (Li 2 Al 2 Si
2 O 8 ), cordierite (Mg 2 Al 4 Si 5 O 18 ), zircon (ZrS
iO 4 ), tin oxide (SnO 2 ), willemite (Zn 2 SiO 4 ), etc. are added at 15 to 30% by volume, and the mixed powder is mixed at 950 to
It is manufactured by heating and melting at a temperature of 1100 ° C. This lead borosilicate glass has a coefficient of thermal expansion of 60
9090 × 10 −7 / ° C.
前記封止用ガラス部材６はその熱膨張係数が60〜90×
10-7/℃であり、絶縁基体１及び蓋体２の各々の熱膨張
係数と近似することから絶縁基体１及び蓋体２の各々に
被着されている封止用ガラス部材６を加熱溶融させ一体
化させることにより絶縁容器３内の半導体素子４を気密
に封止する際、絶縁基体１及び蓋体２と封止用ガラス部
材６との間には両者の熱膨張係数の相違に起因する熱応
力が発生することは殆どなく、絶縁基体１と蓋体２とを
封止用ガラス部材６を介し強固に接合することが可能と
なる。The sealing glass member 6 has a thermal expansion coefficient of 60 to 90 ×.
Since the thermal expansion coefficient is 10 −7 / ° C. and approximates the thermal expansion coefficients of the insulating base 1 and the lid 2, the sealing glass member 6 attached to each of the insulating base 1 and the lid 2 is heated and melted. When the semiconductor element 4 in the insulating container 3 is air-tightly sealed by integrating them, the difference in thermal expansion coefficient between the insulating base 1 and the lid 2 and the sealing glass member 6 is caused. Almost no thermal stress is generated, and the insulating base 1 and the lid 2 can be firmly joined via the glass member 6 for sealing.
尚、前記封止用ガラス部材６はフィラーを添加したホ
ウケイ酸鉛系ガラスの粉末に適当な有機溶剤、溶媒を添
加して得たガラスペーストを従来周知の厚膜手法を採用
することによって絶縁基体１及び蓋体２の相対向する主
面に被着形成される。The sealing glass member 6 is made of a glass paste obtained by adding a suitable organic solvent and a solvent to a powder of lead borosilicate glass to which a filler has been added by employing a conventionally well-known thick film method. 1 and the cover 2 are attached to the opposing main surfaces.
また前記封止用ガラス部材６はフィラーを添加したホ
ウケイ酸鉛系のガラスに限定されるものではなく、熱膨
張係数が60〜90×10-7/℃の範囲のガラスであればいか
なるものでも使用することができる。Further, the sealing glass member 6 is not limited to a lead borosilicate glass to which a filler is added, and any glass having a coefficient of thermal expansion in a range of 60 to 90 × 10 −7 / ° C. Can be used.
前記絶縁基体１及び蓋体２との間には導電性材料から
成る外部リード端子５が配されており、該外部リード端
子５は半導体素子４の各電極がワイヤ７を介し電気的に
接続され、外部リード端子５を外部電気回路に接続する
ことによって半導体素子４が外部電気回路に接続される
こととなる。An external lead terminal 5 made of a conductive material is arranged between the insulating substrate 1 and the lid body 2, and each electrode of the semiconductor element 4 is electrically connected to the external lead terminal 5 via a wire 7. By connecting the external lead terminals 5 to the external electric circuit, the semiconductor element 4 is connected to the external electric circuit.
前記外部リード端子５は絶縁基体１と蓋体２の相対向
する主面に被着させた封止用ガラス部材６を溶融一体化
させ、絶縁容器３を気密封止する際に同時に絶縁基体１
と蓋体２との間に取着される。The external lead terminals 5 are formed by melting and integrating a sealing glass member 6 attached to the opposing main surfaces of the insulating base 1 and the lid 2, and simultaneously sealing the insulating container 3 with the insulating base 1.
And the cover 2.
前記外部リード端子５はインバー合金から成る板状体
の上下面に、該板状体の厚みに対し40乃至60％の厚みの
銅板を接合させた金属体から成り、その透磁率は約200
（CGS）、導電率は51.1％（IACS）、熱膨張係数は約82
×10-7/℃である。The external lead terminals 5 are made of a metal body in which a copper plate having a thickness of 40 to 60% is joined to the upper and lower surfaces of a plate body made of Invar alloy, and the magnetic permeability thereof is about 200.
(CGS), conductivity 51.1% (IACS), coefficient of thermal expansion about 82
× 10 −7 / ° C.
尚、前記外部リード端子５はインバー合金（36.5Wt％
Ni−63.5Wt％ Fe合金）から成る板状体の上下面に銅
（Cu）板を圧接し、しかる後、これを圧延することによ
って形成される。The external lead terminal 5 is made of Invar alloy (36.5 Wt%
It is formed by press-contacting a copper (Cu) plate on the upper and lower surfaces of a plate-shaped body made of Ni-63.5Wt% Fe alloy), and then rolling this.
また前記外部リード端子５は板状体と銅板の厚みが上
述の範囲を外れると外部リード端子５は透磁率が所望す
る低い値に、導電率が高い値にならず、また熱膨張係数
も絶縁基体及び蓋体の熱膨張係数と合わなくなる。その
ため外部リード端子５はインバー合金から成る板状体の
上下面に、該板状体の厚みに対し40乃至60％の厚みの銅
板を接合させた金属体で形成することに限定される。When the thicknesses of the plate-shaped body and the copper plate of the external lead terminal 5 deviate from the above range, the external lead terminal 5 does not have a desired low magnetic permeability and a high electrical conductivity, and also has a thermal expansion coefficient of insulation. It does not match the coefficient of thermal expansion of the base and lid. Therefore, the external lead terminal 5 is limited to a metal body in which a copper plate having a thickness of 40 to 60% of the thickness of the plate-like body is joined to the upper and lower surfaces of the plate-like body made of Invar alloy.
前記外部リード端子５はその透磁率が200（CGS）であ
り、透磁率が低いことから外部リード端子５に電流が流
れたとしても外部リード端子５中には大きな自己インダ
クタンスが発生することはなく、その結果、前記自己イ
ンダクタンスにより誘発される逆起電力に起因したノイ
ズを極小となし、内部に収容する半導体素子４を常に正
常に作動させることができる。Since the magnetic permeability of the external lead terminal 5 is 200 (CGS) and the magnetic permeability is low, even if a current flows through the external lead terminal 5, a large self-inductance does not occur in the external lead terminal 5. As a result, the noise caused by the counter electromotive force induced by the self-inductance is minimized, and the semiconductor element 4 housed therein can always be normally operated.
また前記外部リード端子５はその導電率が51.1％（IA
CS）以上であり、電気を流し易いことから外部リード端
子５の信号伝搬速度を極めて速いものとなすことがで
き、絶縁容器３内に収容した半導体素子４を高速駆動さ
せたとしても半導体素子４と外部電気回路との間におけ
る信号の出し入れは常に安定、且つ確実となすことがで
きる。The conductivity of the external lead terminal 5 is 51.1% (IA
CS) or more, and since it is easy to conduct electricity, the signal propagation speed of the external lead terminal 5 can be made extremely high. Even if the semiconductor element 4 housed in the insulating container 3 is driven at high speed, the semiconductor element 4 Signals can be always sent and received between the power supply and the external electric circuit in a stable and reliable manner.
また同時に外部リード端子５の導電率が高いことから
外部リード端子５の線幅が細くなったとしても外部リー
ド端子５の電気抵抗を低く抑えることができ、その結
果、外部リード端子５における信号の減衰を極小として
内部に収容する半導体素子４に外部電気回路から供給さ
れる電気信号を正確に入力することができる。At the same time, since the electrical conductivity of the external lead terminal 5 is high, even if the line width of the external lead terminal 5 is reduced, the electrical resistance of the external lead terminal 5 can be suppressed low. An electric signal supplied from an external electric circuit can be accurately input to the semiconductor element 4 housed therein with the attenuation being minimized.
また更に前記外部リード端子５はその熱膨張係数が約
82×10-7/℃であり、封止用ガラス部材６の熱膨張係数
と近似することから外部リード端子５を絶縁基体１と蓋
体２の間に封止用ガラス部材６を用いて固定する際、外
部リード端子５と封止用ガラス部材６との間には両者の
熱膨張係数の相違に起因する熱応力が発生することはな
く、外部リード端子５を封止用ガラス部材６で強固に固
定することも可能となる。Further, the external lead terminal 5 has a thermal expansion coefficient of about
82 × 10 −7 / ° C., which is close to the coefficient of thermal expansion of the sealing glass member 6, so that the external lead terminal 5 is fixed between the insulating substrate 1 and the lid body 2 by using the sealing glass member 6. In doing so, thermal stress due to the difference in thermal expansion coefficient between the external lead terminal 5 and the sealing glass member 6 does not occur, and the external lead terminal 5 is sealed by the sealing glass member 6. It can also be firmly fixed.
かくして、この半導体素子収納用パッケージによれば
絶縁基体１の凹部底面に半導体素子４を取着固定すると
ともに該半導体素子４の各電極をボンディングワイヤ７
により外部リード端子５に接続させ、しかる後、絶縁基
体１と蓋体２とを該絶縁基体１及び蓋体２の相対向する
主面に予め被着させておいた封止用ガラス部材６を溶融
一体化させることによって接合させ、これによって最終
製品としての半導体装置が完成する。Thus, according to the package for accommodating the semiconductor element, the semiconductor element 4 is attached and fixed to the bottom surface of the concave portion of the insulating base 1 and each electrode of the semiconductor element 4 is connected to the bonding wire 7.
After that, the sealing glass member 6 in which the insulating substrate 1 and the lid 2 are previously adhered to the opposing main surfaces of the insulating substrate 1 and the lid 2 is removed. The semiconductor device as a final product is completed by joining by melting and integrating.
（発明の効果） 本発明の半導体素子収納用パッケージによれば、半導
体素子を収容するための絶縁容器を構成する絶縁基体及
び蓋体をスピネルもしくはステアタイト質焼結体で、外
部リード端子をインバー合金から成る板状体の上下面
に、該板状体の厚みに対し40乃至60％の厚みの銅板を接
合させた透磁率が約200（CGS）、導電率が51.1％（IAC
S）、熱膨張係数が約82×10-7/℃の金属体で形成したこ
とから外部リード端子に電流を流したとしても該外部リ
ード端子中に大きな自己インダクタンスが発生すること
はなく、その結果、前記自己インダクタンスにより誘発
される逆起電力に起因したノイズを極小となし、内部に
収容する半導体素子を常に正常に作動させることが可能
となる。(Effect of the Invention) According to the package for accommodating a semiconductor element of the present invention, the insulating base body and the lid constituting the insulating container for accommodating the semiconductor element are made of spinel or a steatite sintered body, and the external lead terminals are made of invar. A copper plate having a thickness of 40 to 60% is joined to the upper and lower surfaces of a plate-shaped body made of an alloy, the magnetic permeability is about 200 (CGS), and the conductivity is 51.1% (IAC
S), since it is formed of a metal body having a thermal expansion coefficient of about 82 × 10 −7 / ° C., even if a current is applied to the external lead terminal, a large self-inductance does not occur in the external lead terminal. As a result, the noise caused by the counter electromotive force induced by the self-inductance is minimized, and the semiconductor element housed inside can be normally operated normally.
また外部リード端子の信号伝搬速度を極めて速いもの
となすことができ、絶縁容器内に収容した半導体素子を
高速駆動させたとしても半導体素子と外部電気回路との
間における信号の出し入れを常に安定、且つ確実となす
ことが可能となる。In addition, the signal propagation speed of the external lead terminal can be made extremely fast, so that even when the semiconductor element housed in the insulating container is driven at high speed, the transfer of signals between the semiconductor element and the external electric circuit is always stable, In addition, it is possible to make sure.
更に外部リード端子の線幅が細くなったとしても外部
リード端子の電気抵抗を低く抑えることができ、その結
果、外部リード端子における信号の減衰を極小として内
部に収容する半導体素子に外部電気回路から供給される
電気信号を正確に入力することが可能となる。Furthermore, even if the line width of the external lead terminal is reduced, the electric resistance of the external lead terminal can be kept low. The supplied electric signal can be input accurately.
また更に外部リード端子はその熱膨張係数が絶縁基
体、蓋体及び封止用ガラス部材の各々の熱膨張係数と近
似し、絶縁基体と蓋体との間に外部リード端子を挟み、
各々を封止用ガラス部材で取着接合したとしても絶縁基
体及び蓋体と封止用ガラス部材との間、外部リード端子
と封止用ガラス部材との間のいずれにも熱膨張係数の相
違に起因する熱応力は発生せず、すべてを強固に取着接
合することも可能となる。Furthermore, the coefficient of thermal expansion of the external lead terminal approximates to the coefficient of thermal expansion of each of the insulating substrate, the lid and the sealing glass member, and the external lead terminal is sandwiched between the insulating substrate and the lid.
Even if each of them is attached and bonded with a sealing glass member, the thermal expansion coefficient is different between the insulating base and the lid and the sealing glass member, and between the external lead terminal and the sealing glass member. No thermal stress is caused by this, and it is possible to firmly attach and join all of them.
【図面の簡単な説明】 第１図は本発明の半導体素子収納用パッケージの一実施
例を示す断面図、第２図は第１図に示すパッケージの絶
縁基体上面より見た平面図である。 １……絶縁基体、２……蓋体 ３……絶縁容器 ５……外部リード端子 ６……封止用ガラス部材BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an embodiment of a package for housing a semiconductor device of the present invention, and FIG. 2 is a plan view of the package shown in FIG. DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Insulating container 5 ... External lead terminal 6 ... Glass member for sealing
Claims (1)
素子を収容するための空所を有する絶縁容器と、該容器
内に収容される半導体素子を外部電気回路に接続するた
めの外部リード端子とから成る半導体素子収納用パッケ
ージにおいて、前記絶縁基体及び蓋体をスピネルもしく
はステアタイト質焼結体で、外部リード端子をインバー
合金から成る板状体の上下面に、該板状体の厚みに対し
40乃至60％の厚みの銅板を接合させた金属体で形成した
ことを特徴とする半導体素子収納用パッケージ。1. An insulating container comprising an insulating base and a lid, and having a space for housing a semiconductor element therein, and an external container for connecting the semiconductor element housed in the container to an external electric circuit. In a package for accommodating a semiconductor device including lead terminals, the insulating substrate and the lid are made of spinel or steatite sintered body, and the external lead terminals are formed on the upper and lower surfaces of the plate made of Invar alloy. For thickness
A package for housing a semiconductor element, which is formed of a metal body obtained by joining copper plates having a thickness of 40 to 60%.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30860089A JP2691305B2 (en) | 1989-11-27 | 1989-11-27 | Package for storing semiconductor elements |
| US07/573,406 US5057905A (en) | 1989-08-25 | 1990-08-24 | Container package for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30860089A JP2691305B2 (en) | 1989-11-27 | 1989-11-27 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03167856A JPH03167856A (en) | 1991-07-19 |
| JP2691305B2 true JP2691305B2 (en) | 1997-12-17 |
Family
ID=17982991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30860089A Expired - Fee Related JP2691305B2 (en) | 1989-08-25 | 1989-11-27 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2691305B2 (en) |
-
1989
- 1989-11-27 JP JP30860089A patent/JP2691305B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03167856A (en) | 1991-07-19 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |