JP2689606B2 - Method for manufacturing insulated gate field effect transistor - Google Patents

Method for manufacturing insulated gate field effect transistor

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Publication number
JP2689606B2
JP2689606B2 JP1131085A JP13108589A JP2689606B2 JP 2689606 B2 JP2689606 B2 JP 2689606B2 JP 1131085 A JP1131085 A JP 1131085A JP 13108589 A JP13108589 A JP 13108589A JP 2689606 B2 JP2689606 B2 JP 2689606B2
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JP
Japan
Prior art keywords
region
conductivity type
gate
layer
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1131085A
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Japanese (ja)
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JPH02309678A (en
Inventor
勝典 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to JP1131085A priority Critical patent/JP2689606B2/en
Priority to DE4011276A priority patent/DE4011276C2/en
Priority to US07/521,230 priority patent/US5086007A/en
Priority to FR9006240A priority patent/FR2647596B1/en
Publication of JPH02309678A publication Critical patent/JPH02309678A/en
Application granted granted Critical
Publication of JP2689606B2 publication Critical patent/JP2689606B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/126—Power FETs

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、パワーMOSFETや伝導度変調型MOSFET（以下
IGBTと略す）等の絶縁ゲート電界効果型トランジスタに
関し、特にドレイン領域，ゲート及びソース領域が縦方
向に配された半導体構造の絶縁ゲート電界効果型トラン
ジスタの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a power MOSFET and a conductivity modulation type MOSFET (hereinafter
The present invention relates to an insulated gate field effect transistor such as an IGBT (abbreviated as IGBT), and more particularly to a method for manufacturing an insulated gate field effect transistor having a semiconductor structure in which a drain region, a gate and a source region are vertically arranged.

〔従来の技術〕[Conventional technology]

例えば、従来のＮチャネルパワーMOSFETの構造は、第
３図に示すように、高濃度Ｎ型のドレイン層１上に形成
されたＮ型ベース層（ドレイン・ドリフト領域）２と、
この上にゲート酸化膜３を介して形成されたポリシリコ
ンゲート４と、ポリシリコンゲート４をマスクとして２
重拡散により形成されたＰ型ベース領域（チャネル拡散
領域）５及び高濃度Ｎ型のソース領域６と、このソース
領域６に導電接触するソース電極７と、ソース電極７と
ポリシリコンゲート４とを絶縁する層間絶縁膜８と、基
板の裏面側に被着されたドレイン電極９とを有する。こ
れは、ポリシリコンゲート４直下のＰ型ベース５表面に
形成されるチャネル反転層を介してソース領域６からＮ
型ベース層へ電子が横方向に流れた後、ドレイン電極に
向け縦方向に流れるものである。For example, as shown in FIG. 3, the structure of a conventional N-channel power MOSFET has an N-type base layer (drain / drift region) 2 formed on a high-concentration N-type drain layer 1,
A polysilicon gate 4 formed on top of this via a gate oxide film 3 and a polysilicon gate 4 as a mask
A P-type base region (channel diffusion region) 5 and a high-concentration N-type source region 6 formed by heavy diffusion, a source electrode 7 in conductive contact with the source region 6, a source electrode 7 and a polysilicon gate 4 are provided. It has an interlayer insulating film 8 for insulation and a drain electrode 9 attached to the back surface side of the substrate. This is because the source region 6 to the N region are formed through the channel inversion layer formed on the surface of the P-type base 5 just below the polysilicon gate 4.
The electrons flow horizontally to the mold base layer and then vertically to the drain electrode.

またIGBTの構造は、第３図に示す構造においてドレイ
ン層１の下に高濃度Ｐ型の少数キャリア（正孔）注入層
を備えたものであり、MOS部の構造は上記パワーMOSFET
と変わりがない。The structure of the IGBT is the structure shown in FIG. 3 with a high-concentration P-type minority carrier (hole) injection layer provided under the drain layer 1, and the structure of the MOS part is the above power MOSFET.
There is no change.

ところで、上記縦型構造のパワーMOSFETのオン抵抗Ｒ
は、次式で表すことができる。By the way, the on-resistance R of the vertical structure power MOSFET is
Can be expressed by the following equation.

Ｒ＝Rch＋RACC＋Rj＋Rb （１） ここで、RchはMOS部のチャネル反転層のチャネル抵
抗、RACCはＰ型ベース領域５以外のポリシリコンゲート
４直下に生成された電荷蓄積層の抵抗、Rjはセル間に電
子が通るときの抵抗、RbはＮ型ベース層２の抵抗であ
る。Ｎ型ベース層２の抵抗Rbは主にその厚さによって決
定され、その厚さは耐圧によってほぼ一義的に決まって
しまうので、同耐圧を維持しながら、Ｎ型ベース層２の
抵抗を下げることはできない。オン抵抗Ｒに対してはチ
ャネル抵抗Rchが支配的であるため、チャネル抵抗Rchを
小さくするには、短チャネル化などを実現するパターニ
ングの微細化が必要である。R = R ch + R ACC + R j + R b (1) where R ch is the channel resistance of the channel inversion layer of the MOS part, and R ACC is the charge accumulation generated directly under the polysilicon gate 4 other than the P-type base region 5. The resistance of the layer, R j is the resistance when electrons pass between the cells, and R b is the resistance of the N-type base layer 2. The resistance R b of the N-type base layer 2 is mainly determined by its thickness, and the thickness thereof is almost uniquely determined by the breakdown voltage. Therefore, the resistance of the N-type base layer 2 is lowered while maintaining the same breakdown voltage. It is not possible. Since the channel resistance R ch is dominant with respect to the on-resistance R, in order to reduce the channel resistance R ch , it is necessary to miniaturize the patterning for realizing a short channel or the like.

上記縦型のパワーMOSFETの製造方法を説明するに、ま
ず第４図（Ａ）に示すように、Ｎ型ベース層２を備えた
基板上を表面酸化してゲート酸化膜３を形成し、この上
に第４図（Ｂ）に示す如くのポリシリコン層４′をCVD
等で積層する。次に第４図（Ｃ）に示す如く、パターニ
ングしてポリシリコンゲート４を形成した後、第４図
（Ｄ）に示すように、Ｐ型ベース領域を形成すべき不純
物10をイオン注入等で導入し、熱拡散により第４図
（Ｅ）に示すＰ型ベース領域５を形成する。次に第４図
（Ｆ）に示すように、開口部の中央に不純物選択導入用
のフォトレジスト11を被着してイオン注入で不純物12を
導入した後、フォトレジスト11を除去し、第４図（Ｇ）
に示す如く、絶縁膜13を積層する。次に、形成されたソ
ース領域6,6にまたがる開口部8aをパターニングし、ア
ルミニウム等をスパッタ等で被着して第４図（Ｉ）に示
すソース電極７を形成する。To explain the method of manufacturing the vertical power MOSFET, first, as shown in FIG. 4 (A), the surface of the substrate having the N-type base layer 2 is surface-oxidized to form the gate oxide film 3. CVD of polysilicon layer 4'as shown in FIG.
Etc. Next, as shown in FIG. 4 (C), after patterning to form a polysilicon gate 4, as shown in FIG. 4 (D), an impurity 10 for forming a P-type base region is ion-implanted or the like. Then, the P-type base region 5 shown in FIG. 4 (E) is formed by introducing and thermally diffusing. Next, as shown in FIG. 4 (F), a photoresist 11 for selectively introducing impurities is applied to the center of the opening, and the impurities 12 are introduced by ion implantation. Then, the photoresist 11 is removed, and Figure (G)
As shown in, an insulating film 13 is laminated. Next, the opening 8a extending over the formed source regions 6, 6 is patterned, and aluminum or the like is deposited by sputtering or the like to form the source electrode 7 shown in FIG. 4 (I).

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら、上記MOS部構造を有する絶縁ゲート電
界効果型トランジスタにあっては次の問題点がある。However, the insulated gate field effect transistor having the above MOS structure has the following problems.

即ち、相隣るポリシリコンゲート4,4間の距離ａは10
μｍ前後が限界で、それ以下の微細化は技術的困難さと
歩留りの低下を招く。その理由は、セルの大きさでもあ
る平面距離ａの内には、前述の製造方法から明らかな如
く、層間絶縁膜８のパターニング（第４図（Ｈ））及び
ソース領域６とソース電極７とのコンタクト形成（第４
図（Ｉ））が含まれており、層間絶縁膜８のパターニン
グ寸法はソース電極６と半導体のコンタクト寸法である
ので、これを余り小さくすると、その接触抵抗が大きく
なり、かつソース領域との接触がもてなくなるからであ
る。また距離ａを小さくしてパターニング寸法との差を
小さくすると、パターニングずれや絶縁膜８のサイドエ
ッチ等によりソース電極６とポリシリコンゲート４との
接触が起こり、素子不良となる可能性が大きい。つま
り、相隣るポリシリコンゲート間には複数のフォトリソ
グラフィー工程により各領域を作り込んだ構造を有して
いるため、MOS部の微細化には限度があり、チャネル抵
抗の大幅低減が困難であった。That is, the distance a between the adjacent polysilicon gates 4, 4 is 10
The limit is around μm, and further miniaturization leads to technical difficulties and a decrease in yield. The reason is that patterning of the interlayer insulating film 8 (FIG. 4 (H)) and the source region 6 and the source electrode 7 within the plane distance a, which is also the size of the cell, are apparent from the above-described manufacturing method. Contact formation (4th
Since the patterning dimension of the interlayer insulating film 8 is the contact dimension between the source electrode 6 and the semiconductor, the contact resistance is increased and the contact with the source region is included. This is because there will be no fun. Further, if the distance a is reduced to reduce the difference from the patterning dimension, the source electrode 6 and the polysilicon gate 4 may come into contact with each other due to patterning deviation, side etching of the insulating film 8, or the like, which may result in device failure. In other words, because the structure is such that each region is created by multiple photolithography processes between adjacent polysilicon gates, there is a limit to the miniaturization of the MOS part, and it is difficult to significantly reduce the channel resistance. there were.

そこで、本発明の課題は、相隣るゲート間にソース領
域及びソース電極のコンタクト部を設けずに、ゲート上
部に絶縁膜を介してソース領域を設けてMOS部自体を縦
配向で形成することにより、パターニングの微細化を容
易にし、チャネル抵抗の大幅低減を実現する絶縁ゲート
電界効果型トランジスタの製造方法を提供することにあ
る。Therefore, an object of the present invention is to form a MOS region itself in a vertical orientation by providing a source region above the gate via an insulating film without providing a source region and a contact portion of the source electrode between adjacent gates. Accordingly, it is an object of the present invention to provide a method for manufacturing an insulated gate field effect transistor that facilitates fine patterning and realizes a significant reduction in channel resistance.

〔課題を解決するための手段〕[Means for solving the problem]

上記課題を解決するために、本発明の講じた手段は、
第１導電型半導体層（例えばドレイン領域）上に絶縁膜
に包囲されたゲートを設け、このゲートの周囲に上記絶
縁膜を挟んで第２導電型領域（例えばチャネル拡散領
域）を隣接し、上記絶縁膜のうち少なくとも上記ゲート
の上部膜における側面に沿って第１導電型領域（例えば
ソース領域）を添設したものである。Means taken by the present invention to solve the above problems are:
A gate surrounded by an insulating film is provided on the first conductive type semiconductor layer (for example, a drain region), and a second conductive type region (for example, a channel diffusion region) is adjacent to the gate with the insulating film interposed therebetween. A first conductivity type region (for example, a source region) is additionally provided along at least a side surface of the upper film of the gate in the insulating film.

かかる構造の絶縁ゲート電界効果型トランジスタは、
第１導電型半導体基板上に溝を掘り込んで表面酸化した
後、その溝内にゲート材料を埋め込み、次にその溝周囲
に第２導電型領域形成用不純物を拡散し、次に同溝内に
第１導電型領域形成用不純物を含有する絶縁材料を埋め
込み、しかる後、その第１導電型領域形成用不純物を拡
散することにより製造される。The insulated gate field effect transistor having such a structure is
After digging a groove on the first conductivity type semiconductor substrate to oxidize the surface, a gate material is buried in the groove, then a second conductivity type region forming impurity is diffused around the groove, and then in the groove. It is manufactured by burying an insulating material containing an impurity for forming the first conductivity type region, and then diffusing the impurity for forming the first conductivity type region.

また別の製造方法としては、第１導電型半導体基板上
に第２導電型領域を形成した後、第２導電型領域を周囲
に備えるべき溝を掘り込んで表面酸化し、その溝内にゲ
ート材料及び第１導電型形成用不純物を含有する絶縁材
料を順次埋め込み、しかる後、その第１導電型形成用不
純物を拡散するものである。As another manufacturing method, after the second conductivity type region is formed on the first conductivity type semiconductor substrate, a groove which should be provided with the second conductivity type region in the periphery is dug and surface oxidation is performed, and the gate is formed in the groove. An insulating material containing a material and impurities for forming the first conductivity type is sequentially buried, and then the impurities for forming the first conductivity type are diffused.

〔作用〕[Action]

かかる絶縁ゲート電界効果型トランジスタにおいて
は、相隣るゲート間に絶縁膜の側面に沿って第１導電型
領域（例えばソース領域）が添設しており、その第１導
電型領域はゲート上部に縦方向に配向している。したが
って、チャネル反転層はゲートの厚み方向の絶縁膜に沿
って縦方向に形成される。ゲート間にソース領域を基板
深さ方向に拡散形成する必要がなく、チャネル拡散領域
としての第２導電型領域が実質的に存在する構造である
から、パターニングの微細化が容易であり、またソース
領域とソース電極とのコンタクト部がゲート間に介在せ
ず、単にソース領域の上部にそのコンタクト部を形成す
ることができるので、従来に比してパターニングの微細
化が実現される。In such an insulated gate field effect transistor, a first conductivity type region (for example, a source region) is additionally provided between adjacent gates along the side surface of the insulating film, and the first conductivity type region is provided above the gate. Oriented vertically. Therefore, the channel inversion layer is formed in the vertical direction along the insulating film in the thickness direction of the gate. Since the source region does not need to be diffused and formed between the gates in the substrate depth direction, and the second conductivity type region as the channel diffusion region is substantially present, the patterning can be easily miniaturized. Since the contact portion between the region and the source electrode does not intervene between the gates and the contact portion can be simply formed above the source region, finer patterning can be realized as compared with the conventional case.

第１の製造方法においては、ドレイン領域とすべき第
１導電型半導体基板上に溝を掘り込んで表面酸化する
と、溝内を含めて一部ゲート絶縁膜となるべきシリコン
酸化膜が形成される。次にその溝内にゲート材料を埋め
込み、その溝周囲に第２導電型領域形成用不純物を拡散
してチャネル拡散領域としての第２導電型領域を形成し
た後、同溝内に第１導電型領域形成用不純物を含有する
絶縁材料を埋め込み、しかる後、その第１導電型領域形
成用不純物を拡散させると、上部絶縁膜としての絶縁材
料の側面から先に形成された第２導電型領域内へ拡散進
行してその側面に沿って延びるソース領域としての第１
導電型領域が添設される。In the first manufacturing method, when a groove is dug in the first conductivity type semiconductor substrate to be the drain region and surface oxidation is performed, a silicon oxide film that partially serves as a gate insulating film is formed including the inside of the groove. . Next, a gate material is buried in the groove, and a second conductivity type region forming impurity is diffused around the groove to form a second conductivity type region as a channel diffusion region. Then, the first conductivity type region is formed in the groove. When an insulating material containing an impurity for forming a region is buried and then the impurity for forming a region of the first conductivity type is diffused, a side surface of the insulating material as an upper insulating film is formed in a region of the second conductivity type formed first. As a source region that diffuses to and extends along the side surface
A conductivity type region is additionally provided.

第２の製造方法は、第２導電型領域の形成を溝掘り込
み工程以前に行うもので、第１の製造方法と同じく上記
構造の絶縁ゲート電界効果型トランジスタが得られる。In the second manufacturing method, the second conductivity type region is formed before the trench digging step, and the insulated gate field effect transistor having the above structure can be obtained as in the first manufacturing method.

〔実施例〕〔Example〕

次に、本発明の実施例を添付図面に基づいて説明す
る。Next, embodiments of the present invention will be described with reference to the accompanying drawings.

第１図は本発明に係る絶縁ゲート電界効果型トランジ
スタの構造を示す縦断面図である。なお、第１図におい
て第３図に示す部分と同一部分には同一参照符号を付
し、その説明は省略する。FIG. 1 is a vertical sectional view showing the structure of an insulated gate field effect transistor according to the present invention. In FIG. 1, the same parts as those shown in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted.

第１図において、24は埋め込みポリシリコンゲート
で、この底面及び側面はゲート絶縁膜としてシリコン酸
化膜24a,24bで囲まれ、また上面にはリンガラス（PSG）
の埋め込み絶縁層24cが積層されている。相隣るポリシ
リコンゲート24,24間にはチャネル拡散領域としてのＰ
型ベース領域25が形成されている。このＰ型ベース領域
25とＮ型ベース領域２のPN接合面はポリシリコンゲート
24の底面のシリコン酸化膜24aより若干ドレイン層１側
に位置している。埋め込み絶縁層24cの側面にはそれに
沿って高濃度Ｎ型のソース領域26が形成されている。こ
のソース領域26は埋め込み絶縁層24cの側面から若干Ｐ
型ベース領域25にはみ出す程度の縦長領域として形成さ
れている。ソース領域26とＰ型ベース領域25の上面はほ
ぼ平坦で、その上にはソース電極27が被着されている。In FIG. 1, reference numeral 24 denotes a buried polysilicon gate, the bottom and side surfaces of which are surrounded by silicon oxide films 24a and 24b as gate insulating films, and the top surface is made of phosphorus glass (PSG).
Embedded insulating layer 24c is laminated. Between the adjacent polysilicon gates 24, 24, there is P as a channel diffusion region.
A mold base region 25 is formed. This P-type base area
The PN junction surface between 25 and the N-type base region 2 is a polysilicon gate
It is located slightly on the drain layer 1 side from the silicon oxide film 24a on the bottom surface of 24. A high concentration N-type source region 26 is formed along the side surface of the buried insulating layer 24c. The source region 26 is slightly P from the side surface of the buried insulating layer 24c.
The mold base region 25 is formed as a vertically long region that extends beyond the mold base region 25. The upper surfaces of the source region 26 and the P-type base region 25 are substantially flat, and the source electrode 27 is deposited thereon.

この実施例におけるセルの大きさａ′は従来の10〜20
μｍ程度から一挙に２〜３μｍ程度となり、従来の集積
度より約１桁密度の向上が達成された。その理由は、ポ
リシリコンゲート24,24間には実質的にＰ型ベース領域2
5が介在するだけであり、このＰ型ベース領域25はチャ
ネル反転層28を形成すべきチャネル拡散領域であるか
ら、従来のソースコンタクト部を確保するほどに大なる
幅寸法を設定する必要がないからである。即ち、Ｐ型ベ
ース領域25内にはフォトリソグラフィー工程を施さずに
済むからである。ドレイン領域１とゲート24とソース領
域26とは実質上縦方向に配置されており、チャネル反転
層28は側面のシリコン酸化膜24bに沿って縦方向に細長
く配向している。チャネル反転層28の長さはポリシリコ
ンゲート24の厚み程度で、上述の如くポリシリコンゲー
ト24の微細化によりその厚みは相対的に縮小されている
から、チャネル抵抗の大幅低減が達成されている。The cell size a'in this embodiment is 10 to 20 in the conventional case.
From about μm to about 2 to 3 μm at once, the density is improved by about one digit compared with the conventional integration degree. The reason is that the P-type base region 2 is substantially provided between the polysilicon gates 24, 24.
5, the P-type base region 25 is a channel diffusion region in which the channel inversion layer 28 is to be formed, so that it is not necessary to set the width dimension large enough to secure the conventional source contact portion. Because. That is, it is not necessary to perform the photolithography process in the P-type base region 25. The drain region 1, the gate 24, and the source region 26 are arranged substantially vertically, and the channel inversion layer 28 is vertically elongated along the side surface of the silicon oxide film 24b. The length of the channel inversion layer 28 is about the thickness of the polysilicon gate 24, and the thickness thereof is relatively reduced due to the miniaturization of the polysilicon gate 24 as described above, so that the channel resistance is significantly reduced. .

かかる構造をIGBTに適用した場合、ソース電極26とＰ
型ベース領域25のコンタクト部を原理的にはソース領域
26よりＮ型ベース層２側に寄せることが可能で、寄生ト
ランジスタのベース領域としても機能するＰ型ベース領
域の電位上昇を抑制することができ、ラッチアップ防止
に寄与する利益がある。When such a structure is applied to the IGBT, the source electrode 26 and the P
In principle, the contact portion of the mold base region 25 is the source region.
It is possible to bring it closer to the N-type base layer 2 side than 26, and it is possible to suppress an increase in the potential of the P-type base region that also functions as the base region of the parasitic transistor, and there is an advantage that contributes to the prevention of latch-up.

なお、第１図の実施例では、Ｐ型ベース領域25を埋め
込み溝よりも深く形成しているが、これはむしろ浅くて
もかまわない。特に、パワーMOSFETの場合、浅い方が接
合型FETの効果を小さくできるため、縦型MOSFETの特徴
が大きくなる。In the embodiment of FIG. 1, the P-type base region 25 is formed deeper than the buried groove, but it may be rather shallow. In particular, in the case of a power MOSFET, the shallower the effect of the junction FET can be reduced, the characteristics of the vertical MOSFET become larger.

次に上記構造を備えたパワーMOSFETの製造方法を第２
図に基づいて説明する。Next, a second method for manufacturing a power MOSFET having the above structure will be described.
Description will be made based on the drawings.

まず第２図（Ａ）に示すように、Ｎ型ベース層２を備
えた基板上に略Ｕ字溝31をエッチングにより掘り込んだ
後、第２図（Ｂ）に示す如く、熱酸化により表面酸化を
施し、溝31の内も含めてシリコン酸化膜32を形成する。
このシリコン酸化膜32のうち溝内のものはゲート絶縁膜
としてのシリコン酸化膜24a,24b（第１図参照）となる
べきものである。次に第２図（Ｃ）に示す如く、基板表
面にゲート材料としてのポリシリコン層33をCVD法によ
り積層した後、全面エッチングによりポリシリコン層33
の上層部を除去して溝31内にポリシリコンを第２図
（Ｄ）に示す如くポリシリコンゲート24として残す。こ
れによりポリシリコンゲート24の埋め込みが完了する。
次に第２図（Ｅ）に示すように、溝31間の凸部を不純物
拡散によりＰ型ベース領域25とする。しかる後、第２図
（Ｆ）に示す如く、基板上面にリンガラス（PSG）層35
を積層して溝31内に埋め込み、第２図（Ｇ）に示すよう
に、全面エッチングによりリンガラス層35の上層部を除
去して溝31内にリンガラスを埋め込み絶縁層24cとして
残す。この段階ではポリシリコンゲート24はシリコン酸
化膜24a,24b及び埋め込み絶縁層24cに包囲されている。
次に熱処理を加えて、埋め込み絶縁層24cのリンガラス
からリンを拡散させる。埋め込み絶縁層24の側面から拡
散するリンはＰ型ベース領域へ侵入してその側面に沿っ
て添設した縦長のソース領域26が第２図（Ｈ）に示すよ
うに形成される。最後に第２図（Ｉ）に示すように、ス
パッタ等によりソース電極27を形成する。First, as shown in FIG. 2 (A), a substantially U-shaped groove 31 is formed by etching on a substrate having an N-type base layer 2, and then the surface is thermally oxidized as shown in FIG. 2 (B). Oxidation is performed to form the silicon oxide film 32 including the inside of the groove 31.
The portion of the silicon oxide film 32 in the groove should be the silicon oxide films 24a and 24b (see FIG. 1) as gate insulating films. Next, as shown in FIG. 2C, a polysilicon layer 33 as a gate material is deposited on the surface of the substrate by the CVD method, and then the entire surface is etched to form the polysilicon layer 33.
The upper layer is removed to leave polysilicon in the groove 31 as a polysilicon gate 24 as shown in FIG. This completes the filling of the polysilicon gate 24.
Next, as shown in FIG. 2 (E), the convex portions between the grooves 31 are made into P-type base regions 25 by impurity diffusion. Then, as shown in FIG. 2 (F), a phosphorus glass (PSG) layer 35 is formed on the upper surface of the substrate.
Are laminated and embedded in the groove 31, and the upper portion of the phosphorus glass layer 35 is removed by overall etching to leave phosphorus glass in the groove 31 as an embedded insulating layer 24c, as shown in FIG. At this stage, the polysilicon gate 24 is surrounded by the silicon oxide films 24a and 24b and the buried insulating layer 24c.
Next, heat treatment is applied to diffuse phosphorus from the phosphorus glass of the buried insulating layer 24c. Phosphorus diffusing from the side surface of the buried insulating layer 24 penetrates into the P-type base region, and a vertically long source region 26 is formed along the side surface thereof, as shown in FIG. 2 (H). Finally, as shown in FIG. 2 (I), the source electrode 27 is formed by sputtering or the like.

この製造方法は、溝31を形成することにより、ソース
領域26をセルフアラインで形成することができ、微細化
及び高精度化に適している。勿論、セルの大きさａ′を
前述のように２〜３μｍ程度までに縮小化できるが、溝
形成以外にフォトリソグラフィー工程が含まれず、マス
クずれ等の問題がなく、製造コストの低廉化に寄与す
る。In this manufacturing method, the source region 26 can be formed by self-alignment by forming the groove 31, which is suitable for miniaturization and high precision. Of course, the cell size a ′ can be reduced to about 2 to 3 μm as described above, but since the photolithography process other than the groove formation is not included, there is no problem of mask misalignment, which contributes to the reduction of manufacturing cost. To do.

Ｐ型ベース領域25の形成は上記製造方法ではポリシリ
コンゲート24の埋め込み工程と埋め込み絶縁膜24cの形
成工程の間に行われているが、溝31の掘り込み工程前の
基板全面に予め形成しておいても良い。Although the P-type base region 25 is formed between the step of burying the polysilicon gate 24 and the step of forming the buried insulating film 24c in the above manufacturing method, it is previously formed on the entire surface of the substrate before the trench 31 is dug. You can keep it.

なお、上記実施例はＮチャネルMOSFETを例として説明
したが、ＰチャネルMOSFETの場合は各導電型を逆導電型
とすれば良く、ゲート上部の埋め込み絶縁層の材料はボ
ロンガラス（BSG）を採用すれば良い。Although the above embodiment has been described by taking the N-channel MOSFET as an example, in the case of the P-channel MOSFET, each conductivity type may be opposite conductivity type, and the material of the buried insulating layer above the gate is boron glass (BSG). Just do it.

またパワーMOSFETに限らず、ドレイン層下に少数キャ
リア注入層を設けることにより同様の効果を奏するIGBT
を実現できることは云う迄もない。In addition to the power MOSFET, an IGBT that has a similar effect by providing a minority carrier injection layer under the drain layer
Needless to say, can be realized.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明に係る絶縁ゲート電界効
果型トランジスタは、ゲートを包囲する絶縁膜のうち少
なくともその上部膜における側面に沿ってソース領域と
しての第１導電型領域を添設しており、ゲートの周囲に
は絶縁膜を挟んで第２導電型領域が隣接するものである
から、次の効果を奏する。As described above, in the insulated gate field effect transistor according to the present invention, the first conductivity type region as the source region is additionally provided along at least the side surface of the upper film of the insulating film surrounding the gate. Since the second conductivity type region is adjacent to the periphery of the gate with the insulating film interposed therebetween, the following effects can be obtained.

第２導電型領域の占有域にフォトリソグラフィー工程
を施してソースコンタクト部を設けずとも、ゲートのほ
ぼ上部に配されたソース領域の上面に、コンタクト部が
形成されるので、従来に比してパターニングの微細化が
大幅に達成され、チャネル抵抗の大幅低減と高密度集積
化による大電流容量化が達成される。Even if the source contact portion is not provided by performing the photolithography process on the occupied area of the second conductivity type region, the contact portion is formed on the upper surface of the source region disposed substantially above the gate. Substantial miniaturization of patterning is achieved, and a large reduction in channel resistance and high current capacity by high-density integration are achieved.

フォトリソグラフィー工程が削減されるので、従来に
比して歩留りが良く、製造コストの低廉化が図れる。Since the number of photolithography steps is reduced, the yield is higher than that of the conventional method, and the manufacturing cost can be reduced.

また上記構造の絶縁ゲート電界効果型トランジスタの
製造方法によれば、溝掘り込み後、ソース領域がセルフ
アラインで形成されるので、微細化の促進にかかわら
ず、歩留りの向上により製造コストの低廉化に役立つ。Further, according to the method of manufacturing the insulated gate field effect transistor having the above structure, the source region is formed in self-alignment after the trench is dug. To help.

【図面の簡単な説明】[Brief description of the drawings]

第１図は、本発明に係る絶縁ゲート電界効果型トランジ
スタをパワーMOSFETに適用した実施例の構造を示す縦断
面図である。 第２図（Ａ）乃至（Ｉ）は、同パワーMOSFETの製造プロ
セスを説明する縦断面図である。 第３図は、従来の縦型パワーMOSFETの構造を示す縦断面
図である。 第４図（Ａ）乃至（Ｉ）は、同縦型パワーMOSFETの製造
プロセスを説明する縦断面図である。 １……ドレイン層、２……Ｎ型ベース層、９……ドレイ
ン電極、24……埋め込みポリシリコンゲート、24a,24b
……シリコン酸化膜、24c……埋め込み絶縁層、25……
Ｐ型ベース領域、26……ソース領域、27……ソース電
極、28……チャネル反転層、31……溝、32……シリコン
酸化膜、33……ポリシリコン層、35……リンガラス（PS
G）層、ａ……セルの大きさ（ゲート間距離）。FIG. 1 is a longitudinal sectional view showing the structure of an embodiment in which an insulated gate field effect transistor according to the present invention is applied to a power MOSFET. 2A to 2I are vertical cross-sectional views for explaining the manufacturing process of the power MOSFET. FIG. 3 is a vertical sectional view showing the structure of a conventional vertical power MOSFET. 4A to 4I are vertical cross-sectional views for explaining the manufacturing process of the vertical power MOSFET. 1 ... Drain layer, 2 ... N-type base layer, 9 ... Drain electrode, 24 ... Embedded polysilicon gate, 24a, 24b
...... Silicon oxide film, 24c …… Built-in insulating layer, 25 ……
P-type base region, 26 ... Source region, 27 ... Source electrode, 28 ... Channel inversion layer, 31 ... Groove, 32 ... Silicon oxide film, 33 ... Polysilicon layer, 35 ... Phosphor glass (PS
G) layer, a ... Cell size (distance between gates).

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】第１導電型半導体基板上に溝を掘り込んで
表面酸化した後、該溝内にゲート材料を埋め込み、次に
該溝周囲に第２導電型領域形成用不純物を拡散し、次に
該溝内に第１導電型領域形成用不純物を含有する絶縁材
料を埋め込み、しかる後、その第１導電型領域形成用不
純物を拡散することを特徴とする絶縁ゲート電界効果型
トランジスタの製造方法。1. A trench is formed on a first conductivity type semiconductor substrate to oxidize its surface, a gate material is buried in the trench, and then impurities for forming a second conductivity type region are diffused around the trench. Then, an insulating material containing an impurity for forming the first conductivity type region is buried in the groove, and thereafter, the impurity for forming the first conductivity type region is diffused, to manufacture an insulated gate field effect transistor. Method. 【請求項２】第１導電型半導体基板上に第２導電型領域
を形成した後、第２導電型領域を周囲に備えるべく溝を
掘り込んで表面酸化し、該溝内にゲート材料及び第１導
電型領域形成用不純物を含有する絶縁材料を順次埋め込
み、しかる後、その第１導電型領域形成用不純物を拡散
することを特徴とする絶縁ゲート電界効果型トランジス
タの製造方法。2. After forming a second conductivity type region on a first conductivity type semiconductor substrate, a groove is dug to surface-provide the second conductivity type region, and surface oxidation is performed. A method for manufacturing an insulated gate field effect transistor, which comprises sequentially burying an insulating material containing an impurity for forming a first conductivity type region, and then diffusing the impurity for forming a first conductivity type region.
JP1131085A 1989-05-24 1989-05-24 Method for manufacturing insulated gate field effect transistor Expired - Lifetime JP2689606B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1131085A JP2689606B2 (en) 1989-05-24 1989-05-24 Method for manufacturing insulated gate field effect transistor
DE4011276A DE4011276C2 (en) 1989-05-24 1990-04-06 Insulated gate field effect transistor (IGFET) and method for its manufacture
US07/521,230 US5086007A (en) 1989-05-24 1990-05-08 Method of manufacturing an insulated gate field effect transistor
FR9006240A FR2647596B1 (en) 1989-05-24 1990-05-18 INSULATED GRID FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1131085A JP2689606B2 (en) 1989-05-24 1989-05-24 Method for manufacturing insulated gate field effect transistor

Publications (2)

Publication Number Publication Date
JPH02309678A JPH02309678A (en) 1990-12-25
JP2689606B2 true JP2689606B2 (en) 1997-12-10

Family

ID=15049634

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Application Number Title Priority Date Filing Date
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Country Link
US (1) US5086007A (en)
JP (1) JP2689606B2 (en)
DE (1) DE4011276C2 (en)
FR (1) FR2647596B1 (en)

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DE4011276C2 (en) 1996-07-25

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