JPS5861673A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS5861673A JPS5861673A JP56161195A JP16119581A JPS5861673A JP S5861673 A JPS5861673 A JP S5861673A JP 56161195 A JP56161195 A JP 56161195A JP 16119581 A JP16119581 A JP 16119581A JP S5861673 A JPS5861673 A JP S5861673A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- shaped groove
- layer
- sio2
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- 238000005530 etching Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 10
- 229910052681 coesite Inorganic materials 0.000 abstract 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract 5
- 239000000377 silicon dioxide Substances 0.000 abstract 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract 5
- 229910052682 stishovite Inorganic materials 0.000 abstract 5
- 229910052905 tridymite Inorganic materials 0.000 abstract 5
- 230000006866 deterioration Effects 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り１％にＶ字型溝も
しくは、０字塁溝を具える絶縁ゲート型電界効来トラン
ジスタ（以下ＭＯ８ＦＥＴと称す）の電気的特性の向上
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and relates to electrical characteristics of an insulated gate field effect transistor (hereinafter referred to as MO8FET) having a V-shaped groove or a zero-shaped groove in 1%. This is related to the improvement of
従来％ｖＰｆ−型溝もしくはＵ字型溝ＭＯ８ＦＥＴ輯成
する場合、−導電型１例えばＮ型で主面が結晶（１００
）の半導体基板に１反対導電型、例えばＰ型の不純物を
拡散して、Ｐ型半導体領域を形成し。Conventionally, when constructing a %vPf-type groove or U-shaped groove MO8FET, -conductivity type 1 is, for example, N type, and the main surface is crystalline (100
), an impurity of one opposite conductivity type, for example, P type, is diffused into the semiconductor substrate to form a P type semiconductor region.
その後Ｖ字型＃＄１ｒ形成していた。これによりｓ Ｖ
字型層もしくはＵ字型溝と拡散層との傾きが約５４゜７
４０ あり、逆ベベルなので耐圧が小さくなるのに加え
、チャンネル長が不安定になるなど欠点が多かった。ま
た、Ｖ字形＃Ｉを形成した後酸化膜成長ケ行ない、主面
に垂直な方向の酸化層厚の違いによシ、ｖ字形溝以外の
部分にベース・ソース領域をそれぞれ形成し、逆ベベル
になること管防ぐ方法も考えられているが、高耐圧向き
のＵ字形溝にはこの方法分用いると％Ｕ字形隣の底の部
分に不純物拡散されてしまうとかイオン注入によシ。Thereafter, a V-shaped #$1r was formed. This allows s V
The slope of the diffusion layer and the U-shaped layer or U-shaped groove is approximately 54°7.
40, which has many disadvantages such as a reverse bevel, which reduces the withstand voltage and makes the channel length unstable. In addition, after forming the V-shaped #I, an oxide film is grown, and due to the difference in oxide layer thickness in the direction perpendicular to the main surface, base and source regions are formed in parts other than the V-shaped groove, and a reverse bevel is formed. A method has been considered to prevent the tube from becoming a tube, but if this method is used for a U-shaped groove for high voltage resistance, impurities will be diffused into the bottom part next to the U-shaped groove, or ion implantation will cause problems.
不純物領域管形成するので不純物領域の濃度が低くなる
などの欠点がある。Since the impurity region is formed as a tube, there are drawbacks such as a low concentration of the impurity region.
□ 本発明の目的は耐圧を損なわずチャンネル長の短く
、制御のしやすいＶ字型溝もしくはＵ字型溝ＭＯ８ＦＥ
Ｔｅ得ることのできる半導体装置の製造方法を提供する
にある。□ The purpose of the present invention is to create a V-shaped groove or U-shaped groove MO8FE that has a short channel length and is easy to control without sacrificing withstand voltage.
An object of the present invention is to provide a method for manufacturing a semiconductor device that can obtain Te.
本発明のさらに他の目的は、集積度の高いＶ字型溝もし
くはＵ字型溝ＭＯ８ＦＥＴが容易かっ、確実に得られる
半導体装置の製造方法を提供するＫする。Still another object of the present invention is to provide a method for manufacturing a semiconductor device that allows a highly integrated V-groove or U-shaped groove MO8FET to be easily and reliably obtained.
本発明の製造方法は結晶面（１００）を主面とする一導
電型の半導体基板の一主面にＶ字型溝もしくはＵ字型＃
１￥ｒ形成し、このＶ、字型擲もしくは、Ｕ字型溝を含
む表面に他の物質例えば、ポリシリコンを成長させる。In the manufacturing method of the present invention, a V-shaped groove or a U-shaped #
1\r is formed, and another material such as polysilicon is grown on the surface including this V-shaped groove or U-shaped groove.
ポリシリコンの主面に、Ｖ字型溝もしくはＶ字型溝が形
成されていない程度にポリシリコンを成長させ、これを
エツチングしてＶ字型溝もしくはＵ字型溝のみにポリシ
リコンが残っているようにする。つぎに、このポリシリ
コン會利用して前記基板に反対導電型の不純物のイオン
注入もしくは、不純物拡散を行ない前記Ｖ字型溝もしく
はＵ字型溝以外の部分に反対導電型半導体領域？形成し
、つぎに−導電型不純物のイオン注入もしくは、不純物
拡散を行ない前記Ｖ字型溝もＬ〈はｊＵ字型溝以外の部
分の反対導電型半導体領域に一導電型半導体領域号形成
し前記Ｖ字溝もしくはＵ字型溝部分の酸化層表面にゲー
ト電極、前記−導電型半導体領域にソース電極、前記基
板にドレイン電極ｔそれぞれ形成する工程を含んでいる
。Polysilicon is grown on the main surface of the polysilicon to such an extent that no V-shaped groove or V-shaped groove is formed, and this is etched so that polysilicon remains only in the V-shaped groove or U-shaped groove. Make sure you are there. Next, using this polysilicon layer, ions of an impurity of the opposite conductivity type are implanted into the substrate or impurity diffusion is performed to form a semiconductor region of the opposite conductivity type in a portion other than the V-shaped groove or the U-shaped groove. Then, ion implantation of -conductivity type impurities or impurity diffusion is performed to form a semiconductor region of one conductivity type in the semiconductor region of the opposite conductivity type in a portion other than the V-shaped groove. The method includes the steps of forming a gate electrode on the surface of the oxide layer in the V-shaped groove or the U-shaped groove, a source electrode on the - conductivity type semiconductor region, and a drain electrode t on the substrate.
つぎに図倉用いて、詳細に説明する。第１図（ａＸ（ｂ
）、第２図は、従来例である。第１図体）％（ｂ）は。Next, it will be explained in detail using Zukura. Figure 1 (aX(b)
), FIG. 2 shows a conventional example. Figure 1) %(b) is.
Ｎ型基板１にＰ型ネ細物領域６を形成し、つぎにＮ型不
純物領域７１−形成してから％Ｖ字型溝もしくはＵ字型
溝それぞれ形成し、ＭＯＳＦＥＴを形成している。この
形のＭＯＳＦＥＴでは前述したように耐圧、チャンネル
長に問題がある。第２図は。A P-type narrow region 6 is formed on an N-type substrate 1, and then an N-type impurity region 71 is formed, and then a V-shaped groove or a U-shaped groove is formed, respectively, to form a MOSFET. As mentioned above, this type of MOSFET has problems with voltage resistance and channel length. Figure 2 is.
Ｖ字形５１ｋｉ成した後、酸化膜２の成長全行ない主面
に垂直な方向の酸化膜厚の違いＫよりＶ字形溝以外の部
分にベース参ソース領域をそれぞれ形成している。この
形のＭＯＳＦＥＴでは、前述したように不純物領域がイ
オン注入にょ多形成されているため、不純物ｍ度が低く
なるなどの問題があるので、Ｕ字形溝には用いることが
できない。After the V-shaped groove 51ki is formed, the oxide film 2 is completely grown, and base reference and source regions are respectively formed in parts other than the V-shaped groove due to the difference K in the oxide film thickness in the direction perpendicular to the main surface. In this type of MOSFET, as described above, the impurity region is formed by a large number of ion implantations, so there are problems such as a low impurity m degree, and therefore it cannot be used in a U-shaped groove.
つぎに本発明を実施例により説明する。Next, the present invention will be explained by examples.
第３図（ａ）ないしくｄ）は、本発明の製造工程を説明
するための断面図である。ｔず、第３図（ａ）に示すよ
うに、結晶面（１００）ｔ−主面とするＮ型半導体基板
１に酸化膜全マスクにして、異方性エツチング全行いＵ
字型溝を形成し、さらに酸化を行なう。FIGS. 3(a) to 3(d) are cross-sectional views for explaining the manufacturing process of the present invention. First, as shown in FIG. 3(a), anisotropic etching is performed on an N-type semiconductor substrate 1 whose main surface is the (100) crystal plane using a full oxide film mask.
After forming the groove, oxidation is performed.
これらのプロセスによって酸化膜２が形成される。Oxide film 2 is formed by these processes.
つぎに第３図伽）に示すようＫその上にポリシリコン３
を成長させる。ポリシリコン３の主面にＵ字型溝が形成
されない程度に、このポリシリコン３を成長させ、エツ
チングを行ない、第３図（ｃ）Ｋ示すようにポリシリコ
ンのＵ字型溝部分４を残す。Next, as shown in Figure 3, polysilicon 3 is placed on top of K.
grow. The polysilicon 3 is grown to such an extent that no U-shaped groove is formed on the main surface of the polysilicon 3, and etched to leave a U-shaped groove portion 4 of the polysilicon as shown in FIG. 3(c)K. .
ここで、Ｕ字型溝以外の酸化膜を除去しＵ字型溝部のポ
リシリコンを利用して、Ｕ字型溝以外の部分にＰ型不純
物領域６、Ｎ型不純物領域を第３図（ｄ）Ｋ示すように
、形成する。第３図（ｄ）Ｉｃ示すように、Ｎｌｌ不純
物領域７の表面管覆う酸化膜に窓なあけて、ソース電極
８％Ｕ字型溝の酸化膜２．また新しく作り直した酸化膜
の上にゲート電極９、 □基板ｌの裏面側にドレイン電
極ｌＯをそれぞれ設ける。Ｖ字型街の場合も同様に製造
される。Here, the oxide film other than the U-shaped trench is removed, and the polysilicon in the U-shaped trench is used to form a P-type impurity region 6 and an N-type impurity region in the region other than the U-shaped trench, as shown in FIG. )K Form as shown. As shown in FIG. 3(d) Ic, a window is opened in the oxide film covering the surface tube of the Nll impurity region 7, and an oxide film 2 of the source electrode 8% U-shaped groove is formed. Furthermore, a gate electrode 9 is provided on the newly remade oxide film, and a drain electrode 10 is provided on the back side of the substrate 1, respectively. V-shaped streets are manufactured in the same way.
このようにして、製造されたＶ字型もしくは、Ｕ字型Ｍ
Ｏ８ＦＥＴでは、Ｐ型半導体細板６．およびＮ型半導体
領域７をイオン注入もしくは、不純物拡散で形成する際
、不純物が曲率半径をもって拡散されるので、Ｖ字型溝
もしくはＵ字型溝の内面１１に対し、ｔｌぼ直角にＰＮ
接合端が突き当るようになる。これは、従来の不純物拡
散後にＶ字型溝もしくはＵ字型溝を形成した場合には、
ＰＮ接合とＶ字型滴面もしくはＵ字擲面が斜めになるの
に比べ、電界集中が起り鍵くなる。その上、Ｕ字型溝Ｍ
０８ ＦＥＴＫも用いれるので、その効果は、大きくな
る。また、チャンネル長も制御し易くなり短チャンネル
化が可能で高集積化に役立つ。In this way, the V-shaped or U-shaped M
In O8FET, P-type semiconductor thin plate 6. When forming the N-type semiconductor region 7 by ion implantation or impurity diffusion, the impurity is diffused with a radius of curvature.
The joint ends will now touch each other. This means that when a V-shaped groove or U-shaped groove is formed after conventional impurity diffusion,
Compared to the case where the PN junction and the V-shaped droplet surface or U-shaped droplet surface are slanted, electric field concentration occurs, which is the key. Moreover, U-shaped groove M
Since 08 FETK is also used, the effect is greater. In addition, the channel length can be easily controlled, making it possible to shorten the channels, which is useful for high integration.
なお、上側においてＮ導電型を一導電型、反対導電型を
Ｐ型導電型に対応させて説明したが、この対応が逆の場
合も本発明がそのまま適用できるのはいうまでもない。Note that although the N conductivity type has been described above as corresponding to one conductivity type and the opposite conductivity type corresponds to P type conductivity, it goes without saying that the present invention can be applied as is even if the correspondence is reversed.
ｗ、１図（＆）、（ｂ）、第２図は、従来例の溝？有す
る半導体装置の断面図、第３図（ａ）〜（ｄ）は本発明
の一実施例の半導体装置の製造工程全説明するための断
面図である。
な２図において、１・・Ｎ型半導体基板％ ２・・酸化
膜、３，４・・ポリシリコン、５・・Ｎ艷型半尋体基板
、６・・Ｐ型半導体領域、７・・Ｎ型半導体領域、８・
・ソース電極、９・・ゲート電極、１０・・ドレイン電
極、１１・・Ｕ字型溝の内面、である。
（ａン
第 １ 区
第 ２ 図
（１）
第′３ 図w, Figure 1 (&), (b), and Figure 2 are the grooves of the conventional example? 3(a) to 3(d) are cross-sectional views for explaining the entire manufacturing process of a semiconductor device according to an embodiment of the present invention. In Figure 2, 1...N-type semiconductor substrate% 2...Oxide film, 3,4...Polysilicon, 5...N-shaped half-body substrate, 6...P-type semiconductor region, 7...N type semiconductor region, 8.
- Source electrode, 9... Gate electrode, 10... Drain electrode, 11... Inner surface of U-shaped groove. (a) Section 1 Section 2 (1) Section '3
Claims (1)
一生面にＶ字形溝もしくはＵ字形靜を形成し、該Ｖ９字
形溝もしくはＵ字形溝を他の物質により埋め合わせ、前
記−主面に反対導電型不利物を導入し、前記Ｖ字形溝も
しくはＵ字形溝以外部分に反対導電型中導体領域を形成
してさらに一導電型不純物を導入して前記Ｖ字形溝もし
くはＵ字形溝以外の部分に一導電型半導体領域を形成す
る工程を含むこと１％黴とする半導体装置の製造方法。A V-shaped groove or a U-shaped groove is formed on the whole surface of a semiconductor substrate of one conductivity type whose main surface is the crystal plane (100), and the V-shaped groove or U-shaped groove is filled with another substance, and the -main surface is An opposite conductivity type impurity is introduced into the V-shaped groove or the U-shaped groove, an opposite conductivity type intermediate conductor region is formed in the portion other than the V-shaped groove or the U-shaped groove, and an impurity of one conductivity type is further introduced to form the opposite conductivity type in the portion other than the V-shaped groove or the U-shaped groove. A method for manufacturing a semiconductor device including the step of forming a semiconductor region of one conductivity type in a portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56161195A JPS5861673A (en) | 1981-10-09 | 1981-10-09 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56161195A JPS5861673A (en) | 1981-10-09 | 1981-10-09 | Preparation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5861673A true JPS5861673A (en) | 1983-04-12 |
Family
ID=15730386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56161195A Pending JPS5861673A (en) | 1981-10-09 | 1981-10-09 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5861673A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040034A (en) * | 1989-01-18 | 1991-08-13 | Nissan Motor Co., Ltd. | Semiconductor device |
| US5086007A (en) * | 1989-05-24 | 1992-02-04 | Fuji Electric Co., Ltd. | Method of manufacturing an insulated gate field effect transistor |
| US5177572A (en) * | 1990-04-06 | 1993-01-05 | Nissan Motor Co., Ltd. | Mos device using accumulation layer as channel |
-
1981
- 1981-10-09 JP JP56161195A patent/JPS5861673A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040034A (en) * | 1989-01-18 | 1991-08-13 | Nissan Motor Co., Ltd. | Semiconductor device |
| US5086007A (en) * | 1989-05-24 | 1992-02-04 | Fuji Electric Co., Ltd. | Method of manufacturing an insulated gate field effect transistor |
| US5177572A (en) * | 1990-04-06 | 1993-01-05 | Nissan Motor Co., Ltd. | Mos device using accumulation layer as channel |
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