JP2676828B2 - Manufacturing method of hybrid integrated circuit device - Google Patents

Manufacturing method of hybrid integrated circuit device

Info

Publication number
JP2676828B2
JP2676828B2 JP63248739A JP24873988A JP2676828B2 JP 2676828 B2 JP2676828 B2 JP 2676828B2 JP 63248739 A JP63248739 A JP 63248739A JP 24873988 A JP24873988 A JP 24873988A JP 2676828 B2 JP2676828 B2 JP 2676828B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
conductive member
thermosetting resin
resin
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63248739A
Other languages
Japanese (ja)
Other versions
JPH0296343A (en
Inventor
豊 福田
裕之 山川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP63248739A priority Critical patent/JP2676828B2/en
Publication of JPH0296343A publication Critical patent/JPH0296343A/en
Application granted granted Critical
Publication of JP2676828B2 publication Critical patent/JP2676828B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29015—Shape in top view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はフリップチップの半導体チップを基板等にワ
イヤレスボンディングするタイプの混成集積回路装置の
製造方法に関するものである。The present invention relates to a method of manufacturing a hybrid integrated circuit device of a type in which a semiconductor chip of a flip chip is wirelessly bonded to a substrate or the like.

〔従来の技術〕[Conventional technology]

従来、例えば特開昭53−21771号公報に示されている
ように、フリップチップを基板に実装した構造におい
て、チップ・基板間にエポキシ系樹脂，シリコン系樹
脂，光硬化樹脂等の樹脂材料を充填することにより、チ
ップ・基板間の熱膨張差による耐熱疲労性を改善できる
ことが知られている。Conventionally, as shown in, for example, Japanese Unexamined Patent Publication No. 53-21771, in a structure in which a flip chip is mounted on a substrate, a resin material such as an epoxy resin, a silicon resin, or a photocurable resin is provided between the chip and the substrate. It is known that the filling can improve the thermal fatigue resistance due to the difference in thermal expansion between the chip and the substrate.

その製造方法は第３図（ａ），（ｂ）に示すように、
配線102が施された基板101上にフリップチップ103を半
田104を介して半田付けした後（第３図（ａ））、フリ
ップチップ103の周辺に樹脂105を塗布し、その毛細管現
象を利用してチップ・基板間に充填した後、硬化するよ
うにしていた（第３図（ｂ））。The manufacturing method is as shown in FIGS. 3 (a) and 3 (b).
After the flip chip 103 is soldered on the substrate 101 on which the wiring 102 is provided via the solder 104 (FIG. 3 (a)), the resin 105 is applied to the periphery of the flip chip 103, and the capillary phenomenon is used. After filling the space between the chip and the substrate, it was cured (Fig. 3 (b)).

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

この時、チップ・基板間の狭いギャップに樹脂を充填
する為に樹脂の粘度を十分下げる必要があり、その結
果、他の材質特性、例えば熱膨張係数・弾性率に制約が
生じてしまう。又、チップに形成されるバンプの高さの
ばらつきの影響を受けて、チップ・基板間の樹脂厚がば
らついたり、第３図（ｂ）に示すようにチップ周辺にお
いても樹脂厚のばらつきが生じてしまい、延いては樹脂
と基板の熱膨張差により樹脂が割れたり、基板から剥離
してしまうという問題があった。At this time, it is necessary to sufficiently reduce the viscosity of the resin in order to fill the narrow gap between the chip and the substrate with the resin. As a result, other material characteristics such as thermal expansion coefficient and elastic modulus are restricted. Further, the resin thickness between the chip and the substrate varies due to the influence of the height variation of the bumps formed on the chip, and the resin thickness also varies around the chip as shown in FIG. 3B. Therefore, there is a problem that the resin is cracked or separated from the substrate due to the difference in thermal expansion between the resin and the substrate.

そこで本発明は上記の問題点に鑑みなされたものであ
って、上述のような製造過程におけるチップ・基板間の
樹脂厚のばらつきを極力小さくすることがてきる混成集
積回路装置の製造方法を提供することを目的とする。The present invention has been made in view of the above problems, and provides a method for manufacturing a hybrid integrated circuit device capable of minimizing the variation in the resin thickness between the chip and the substrate in the manufacturing process as described above. The purpose is to do.

〔課題を解決するための手段〕[Means for solving the problem]

上記の目的を達成するために本発明は、 所定の熱伝導を有する導電部材と該導電部材より熱伝
導の低い絶縁部材を間に挟み、半導体チップを被搭載部
材に設置する混成集積回路装置の製造方法であって、 前記半導体チップと前記被搭載部材の両ボンディング
部分が前記導電部材を介して対向するように前記絶縁部
材を挟んで前記半導体チップを前記被搭載部材に載置
し、その後の導電部材溶融行程を終了するまでは前記半
導体チップを前記被搭載部材に載置した時点の前記半導
体チップ下面と前記被搭載部材表面の間隙を前記絶縁部
材により実質的に一定に保つ行程と、 そして前記導電部材の融点以上の温度で熱処理を行
い、前記絶縁部材が前記半導体チップを保持する状態で
前記導電部材を溶融する行程と、 しかる後、前記絶縁部材の熱硬化温度以上でかつ前記
導電部材の融点以下の温度にて熱処理を行い前記絶縁部
材を軟化した後に硬化させる行程と からなることを特徴とする。In order to achieve the above object, the present invention provides a hybrid integrated circuit device in which a semiconductor chip is mounted on a mounted member by sandwiching a conductive member having a predetermined heat conduction and an insulating member having a lower heat conduction than the conductive member. A method of manufacturing, wherein the semiconductor chip is placed on the mounted member with the insulating member sandwiched so that both bonding portions of the semiconductor chip and the mounted member face each other via the conductive member, and thereafter, A step of keeping a gap between the lower surface of the semiconductor chip and the surface of the mounted member substantially constant by the insulating member when the semiconductor chip is mounted on the mounted member until the conductive member melting step is completed; A step of performing heat treatment at a temperature equal to or higher than the melting point of the conductive member, and melting the conductive member while the insulating member holds the semiconductor chip; and thereafter, heat the insulating member. And heat treatment at a temperature not lower than the curing temperature and not higher than the melting point of the conductive member to soften the insulating member and then cure the insulating member.

〔作用〕[Action]

そこで本発明によると、半導体チップと被搭載部材と
の間に存在することになる絶縁部材は、半導体チップの
ボンディング後に塗布するのではなく、半導体チップを
設置する際に予めその間に存在している。よって、この
絶縁部材の硬化温度より高い温度により熱処理を行う際
に、絶縁部材は軟化して半導体チップ・被搭載部材間の
良好な状態で十分に充填するようになる。Therefore, according to the present invention, the insulating member to be present between the semiconductor chip and the mounted member is not applied after the bonding of the semiconductor chip but is present between them in advance when the semiconductor chip is installed. . Therefore, when the heat treatment is performed at a temperature higher than the curing temperature of the insulating member, the insulating member is softened and is sufficiently filled in a good state between the semiconductor chip and the mounted member.

また、半導体チップは、導電部材の熱処理が終了され
るまでは、当該半導体チップが被搭載部材に載置された
時点の位置、即ち、被搭載部材表面と半導体チップ下面
の間隙、が絶縁部材により保持されるようになる。これ
により、導電部材を熱処理する際には、半導体チップの
上記載置位置が保持されたまま半導体チップは被搭載部
材上に導電部材によって固着される。そして、しかる後
の絶縁部材硬化工程により、絶縁部材は半導体チップ・
被搭載部材間に良好な状態で硬化されることとなる。In addition, until the heat treatment of the conductive member is completed, the semiconductor chip has a position at the time when the semiconductor chip is mounted on the mounted member, that is, a gap between the surface of the mounted member and the lower surface of the semiconductor chip by the insulating member. Will be retained. As a result, when the conductive member is heat-treated, the semiconductor chip is fixed to the mounted member by the conductive member while maintaining the above-mentioned mounting position of the semiconductor chip. Then, in a subsequent insulating member curing step, the insulating member is removed from the semiconductor chip.
It will be cured in a good state between the members to be mounted.

〔実施例〕〔Example〕

以下、本発明を図面に示す実施例を用いて説明する。 Hereinafter, the present invention will be described using embodiments shown in the drawings.

第１図（ａ）〜（ｄ）は本発明の一実施例を工程順に
説明する為の断面図であり、第１図（ｅ）はそのうち熱
硬化樹脂の平面図をあらわしている。図において１はア
ルミナ基板，ガラス基板等から成る基板であり、本発明
で言う被搭載部材に相当する。この基板１の表面上には
配線２が形成されており、さらに配線２の後述するフリ
ップチップ５とのボンディング部分には迎え半田３が形
成されている。そして、この迎え半田３の部分を開口し
た熱硬化樹脂４を基板１上に設置する（第１図
（ａ））。この熱硬化樹脂４の平面形状は第１図（ｅ）
に示すような平板形状をしており、ボンディング部分に
開口した部分から平面方向の端面42へ延びる溝41を有し
ている。又、その板厚は均一に形成されている。さらに
熱硬化樹脂４は本実施例の場合には固体状のエポキシ系
の樹脂を用いてる。1 (a) to 1 (d) are cross-sectional views for explaining one embodiment of the present invention in the order of steps, and FIG. 1 (e) is a plan view of thermosetting resin. In the figure, reference numeral 1 is a substrate made of an alumina substrate, a glass substrate or the like, which corresponds to the mounted member in the present invention. A wiring 2 is formed on the surface of the substrate 1, and a solder 3 is formed on a bonding portion of the wiring 2 with a flip chip 5 described later. Then, the thermosetting resin 4 having the opening of the solder 3 is placed on the substrate 1 (FIG. 1 (a)). The plane shape of the thermosetting resin 4 is shown in FIG. 1 (e).
And has a groove 41 extending from the portion opened to the bonding portion to the end surface 42 in the plane direction. Moreover, the plate thickness is formed uniformly. Further, in the case of this embodiment, the thermosetting resin 4 is a solid epoxy resin.

次に、電極の半田から成るバンプ６を有するフリップ
チップ５をそのバンプ６が前述のボンディング部に対応
するようにして熱硬化樹脂４上に設置する（第１図
（ｂ））。Next, the flip chip 5 having the bumps 6 made of electrode solder is placed on the thermosetting resin 4 so that the bumps 6 correspond to the above-mentioned bonding portions (FIG. 1 (b)).

そうした上で、第２図の温度プロファイルに示すよう
に、半田の融点（183℃）以上の温度Ta,例えばTa＝260
℃にて約10秒間放置して熱処理を行う（第１図
（ｃ））。この時、10秒間熱処理を行うと、基板1,フリ
ップチップ５等から熱が伝わって半田が完全に溶融する
ようになる。一方、半田より熱伝導が悪い熱硬化樹脂４
では多少軟化し始めるが、このような短時間ではまだ十
分固い状態であり、フリップチップ５の底面を保持して
チップ・基板間距離を一定に保っている。Then, as shown in the temperature profile of FIG. 2, a temperature Ta higher than the melting point (183 ° C.) of the solder, for example Ta = 260.
A heat treatment is carried out by leaving it at ℃ for about 10 seconds (Fig. 1 (c)). At this time, if heat treatment is performed for 10 seconds, heat is transferred from the substrate 1, the flip chip 5, etc., so that the solder is completely melted. On the other hand, thermosetting resin 4 which has poorer thermal conductivity than solder
Then, it begins to soften somewhat, but in such a short time it is still sufficiently hard, and the bottom surface of the flip chip 5 is held to keep the distance between the chip and the substrate constant.

その後、熱処理の温度を下げて、第２図に示すように
熱硬化樹脂４の硬化可能温度以上で且つ半田の融点より
低い温度Tb、例えばTb＝160℃にて約４時間熱を加え
る。この時ボンディング部分の半田は固形化して柱状半
田７となり、熱硬化樹脂４はまず軟化して液状となり、
その表面張力により柱状半田７の周囲を含むチップ・基
板間に充填するようになる。その後、熱処理が進むにつ
れて熱硬化樹脂４は硬化して第１図（ｄ）に示すような
状態になる。ここで、熱硬化樹脂４が軟化している状態
においても柱状半田７が固体状であるので、半導体チッ
プ５と基板１との間隔は一定に保たれており、熱硬化樹
脂４の硬化後においてもその間隔を均一に保つことがで
きる。After that, the temperature of the heat treatment is lowered, and as shown in FIG. 2, heat is applied for about 4 hours at a temperature Tb which is higher than the curable temperature of the thermosetting resin 4 and lower than the melting point of the solder, for example, Tb = 160 ° C. At this time, the solder at the bonding portion is solidified to form the columnar solder 7, and the thermosetting resin 4 is first softened to become liquid,
Due to the surface tension, it is filled between the chip and the substrate including the periphery of the columnar solder 7. After that, as the heat treatment progresses, the thermosetting resin 4 is cured into a state as shown in FIG. 1 (d). Here, since the columnar solder 7 is solid even when the thermosetting resin 4 is softened, the distance between the semiconductor chip 5 and the substrate 1 is kept constant, and after the thermosetting resin 4 is hardened. The distance can be kept uniform.

そこで本実施例によると、熱硬化樹脂４は基板１とフ
リップチップ５との間に予じめ存在しているので十分に
充填することができ、従来技術のように樹脂厚がばらつ
くというような不具合はなく、又、樹脂の粘度は任意の
ものを使用できる。又、半田のリフローおよび熱硬化樹
脂４の軟化・硬化の工程はその際にそれぞれが固い状態
である熱硬化樹脂４および柱状半田７にてフリップチッ
プ５を保持した状態で行われるのでフリップチップ５・
基板１間の間隔は均一に保たれ、その間の樹脂厚にばら
つきがほとんど生じなくなる。尚、フリップチップ５・
基板１間の間隔は第１図（ａ）の状態における固体状の
熱硬化樹脂４の板厚により設定されるので、固体状の熱
硬化樹脂４はその平面方向にわたって所望の均一な板厚
にする必要がある。Therefore, according to this embodiment, since the thermosetting resin 4 is preliminarily present between the substrate 1 and the flip chip 5, the thermosetting resin 4 can be sufficiently filled, and the resin thickness varies as in the prior art. There is no problem, and any resin viscosity can be used. Further, the steps of reflowing the solder and softening / curing the thermosetting resin 4 are performed while the flip chip 5 is held by the thermosetting resin 4 and the columnar solder 7, which are in a hard state, respectively.・
The space between the substrates 1 is kept uniform, and the resin thickness between them hardly varies. Flip chip 5
Since the distance between the substrates 1 is set by the plate thickness of the solid thermosetting resin 4 in the state of FIG. 1 (a), the solid thermosetting resin 4 has a desired uniform plate thickness in the plane direction. There is a need to.

又、本実施例では熱硬化樹脂４の形状を第１図（ｅ）
に示すように溝41を形成した形状としているので、第１
図（ｄ）を用いて説明した工程において、熱硬化樹脂４
が軟化し、硬化する際にこの熱硬化樹脂４と柱状半田７
との間に存在していたエアを外部に抜くことができ、硬
化後の熱硬化樹脂４内にはボイド（気泡）が存在しなく
なる。又、熱硬化樹脂４の体積を所定の値にしておけば
硬化後にフリップチップ５からの樹脂のはみだしのない
構成が実現できる。尚、熱硬化樹脂４はその硬化工程に
おいて約10％の体積減少があるので、予じめその大きさ
はフリップチップ５の大きさより少し大きくしておく必
要がある。In this embodiment, the shape of the thermosetting resin 4 is shown in FIG.
Since the groove 41 is formed as shown in FIG.
In the process described with reference to FIG. 3D, the thermosetting resin 4
When the resin softens and hardens, the thermosetting resin 4 and the columnar solder 7
The air existing between and can be discharged to the outside, and voids (air bubbles) do not exist in the thermosetting resin 4 after curing. Further, if the volume of the thermosetting resin 4 is set to a predetermined value, a configuration in which the resin does not overflow from the flip chip 5 after curing can be realized. Since the volume of the thermosetting resin 4 is reduced by about 10% in the curing step, it is necessary to make the size of the thermosetting resin 4 a little larger than the size of the flip chip 5 in advance.

さらに、第３図を用いて説明した従来技術によると半
田リフローの為の加熱工程の後に一度温度を下げ、その
後に樹脂の加熱の為に再び温度を上げる必要があり製造
時間が長くなってしまうという不具合があるのに対し
て、本実施例によると半田リフローを行った後、引続き
樹脂の軟化・硬化工程を行っているのでその分製造時間
を短くすることができ有利である。Further, according to the conventional technique described with reference to FIG. 3, it is necessary to lower the temperature once after the heating process for solder reflow, and then to raise the temperature again for heating the resin, which increases the manufacturing time. In contrast to this problem, according to this embodiment, since the resin softening / curing process is continuously performed after the solder reflow, the manufacturing time can be shortened accordingly.

以上、本発明を上記実施例を用いて説明したが本発明
はそれに規定されることはなく、その主旨を逸脱しない
限り例えば以下に示す如く種々変形可能である。Although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modifications can be made, for example, as shown below, without departing from the spirit of the present invention.

半田のリフロー工程における「短時間」とは、熱硬化
樹脂４が十分固くフリップチップ５を保持できる範囲の
時間であり、上記の例ではリフロー温度がTa＝260℃で
ありその場合には約１分間ぐらいで熱硬化樹脂４で軟か
くなってしまうのでそれよりも短い時間である。The “short time” in the solder reflow process is a time within a range in which the thermosetting resin 4 is sufficiently hard and can hold the flip chip 5. In the above example, the reflow temperature is Ta = 260 ° C. The time is shorter than that, because the thermosetting resin 4 softens in about one minute.

上記の例では半田として共晶半田（融点183℃）を用
いているが、64半田（融点200℃）等の他の半田を用い
てもよい。又、熱硬化樹脂４も例えばエポキシ変性フェ
ノール，フェノール変形エポキシ等の他の熱硬化樹脂を
用いてもよい。Although eutectic solder (melting point 183 ° C.) is used as the solder in the above example, other solder such as 64 solder (melting point 200 ° C.) may be used. Further, as the thermosetting resin 4, other thermosetting resins such as epoxy modified phenol and phenol modified epoxy may be used.

上記実施例ではフリップチップタイプのものについて
本発明を適用しているが、本発明は他の表面実装タイプ
の混成集積回路装置にも適用可能であり、例えばTAB方
式に適用する場合には本発明で言う被搭載部材はリード
に相当する。Although the present invention is applied to the flip chip type in the above embodiments, the present invention is also applicable to other surface mounting type hybrid integrated circuit devices. For example, when the present invention is applied to the TAB method, the present invention is applied. The mounted member referred to in (1) corresponds to a lead.

〔発明の効果〕〔The invention's effect〕

以上述べたように、本発明によると、半導体チップが
被搭載部材に載置された時点の位置、即ち、被搭載部材
表面と半導体チップ下面の間隙、が軟化前の絶縁部材に
より決定されるので、製造過程におけるばらつきによら
ず半導体チップ・被搭載部材間は常に均一に保たれ、耐
熱疲労性に優れた混成集積回路装置を製造することがで
きる。As described above, according to the present invention, the position at the time when the semiconductor chip is mounted on the mounted member, that is, the gap between the surface of the mounted member and the lower surface of the semiconductor chip is determined by the insulating member before softening. It is possible to manufacture a hybrid integrated circuit device which is always kept uniform between the semiconductor chip and the mounted member regardless of variations in the manufacturing process, and which has excellent thermal fatigue resistance.

【図面の簡単な説明】[Brief description of the drawings]

第１図（ａ）〜（ｄ）は本発明の一実施例を工程順に説
明する為の断面図、第１図（ｅ）は熱硬化樹脂の平面
図、第２図は各熱処理工程の温度プロファイルを表わす
図、第３図（ａ），（ｂ）は従来技術を説明する為の断
面図である。 １……基板,2……配線,3……迎え半田,4……熱硬化樹
脂,5フリップチップ,6……バンプ,7……柱状半田,41…
…溝。1 (a) to 1 (d) are cross-sectional views for explaining one embodiment of the present invention in the order of steps, FIG. 1 (e) is a plan view of thermosetting resin, and FIG. 2 is the temperature of each heat treatment step. FIGS. 3 (a) and 3 (b) showing a profile are sectional views for explaining the prior art. 1 ... Substrate, 2 ... Wiring, 3 ... Welding solder, 4 ... Thermosetting resin, 5 Flip chip, 6 ... Bump, 7 ... Column solder, 41 ...
…groove.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】所定の熱伝導を有する導電部材と該導電部
材より熱伝導の低い絶縁部材を間に挟み、半導体チップ
を被搭載部材に設置する混成集積回路装置の製造方法で
あって、 前記半導体チップと前記被搭載部材の両ボンディング部
分が前記導電部材を介して対向するように前記絶縁部材
を挟んで前記半導体チップを前記被搭載部材に載置し、
その後の導電部材溶融行程を終了するまでは前記半導体
チップを前記被搭載部材に載置した時点の前記半導体チ
ップ下面と前記被搭載部材表面の間隙を前記絶縁部材に
より実質的に一定に保つ行程と、 そして前記導電部材の融点以上の温度で熱処理を行い、
前記絶縁部材が前記半導体チップを保持する状態で前記
導電部材を溶融する行程と、 しかる後、前記絶縁部材の熱硬化温度以上でかつ前記導
電部材の融点以下の温度にて熱処理を行い前記絶縁部材
を軟化した後に硬化させる行程と からなることを特徴とする混成集積回路装置の製造方
法。1. A method of manufacturing a hybrid integrated circuit device, comprising: mounting a semiconductor chip on a mounted member, with a conductive member having a predetermined heat conductivity and an insulating member having a lower heat conductivity than the conductive member sandwiched therebetween. Place the semiconductor chip on the mounted member with the insulating member sandwiched so that both bonding portions of the semiconductor chip and the mounted member face each other via the conductive member,
Until the subsequent conductive member melting step is completed, a step of keeping the gap between the lower surface of the semiconductor chip and the surface of the mounted member substantially constant by the insulating member when the semiconductor chip is mounted on the mounted member, and Then, heat treatment is performed at a temperature equal to or higher than the melting point of the conductive member,
A step of melting the conductive member in a state where the insulating member holds the semiconductor chip; and thereafter, a heat treatment is performed at a temperature not lower than the thermosetting temperature of the insulating member and not higher than the melting point of the conductive member. A method for manufacturing a hybrid integrated circuit device, comprising the steps of softening and then hardening.
JP63248739A 1988-09-30 1988-09-30 Manufacturing method of hybrid integrated circuit device Expired - Lifetime JP2676828B2 (en)

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JPH0296343A JPH0296343A (en) 1990-04-09
JP2676828B2 true JP2676828B2 (en) 1997-11-17

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