JP5175003B2 - Manufacturing method of integrated circuit device having three-dimensional laminated structure - Google Patents

Manufacturing method of integrated circuit device having three-dimensional laminated structure Download PDF

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JP5175003B2
JP5175003B2 JP2005259824A JP2005259824A JP5175003B2 JP 5175003 B2 JP5175003 B2 JP 5175003B2 JP 2005259824 A JP2005259824 A JP 2005259824A JP 2005259824 A JP2005259824 A JP 2005259824A JP 5175003 B2 JP5175003 B2 JP 5175003B2
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semiconductor circuit
circuit layer
electrode
adhesive film
adhesive
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JP2007073775A (en
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光正 小柳
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光正 小柳
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Priority to JP2005259824A priority Critical patent/JP5175003B2/en
Priority to TW095133066A priority patent/TWI433244B/en
Priority to PCT/JP2006/317716 priority patent/WO2007037106A1/en
Publication of JP2007073775A publication Critical patent/JP2007073775A/en
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Abstract

A method for manufacturing a three-dimensional multilayer integrated circuit device in which an electrically insulating adhesive can be placed in the spacing between semiconductor circuit layers and the portion of the eclectically insulating adhesive sticking out of the spacing does not need to be removed. Buried interconnection members (conductive plugs) (15) are formed in a first semiconductor circuit layer (1a), and the ends thereof are exposed from the back surface of the first semiconductor layer (1a). Bump electrodes (43a) are formed in positions corresponding to the plugs (15) on the front surface of a second semiconductor layer (2). An electrically insulating adhesive film (44a) patterned into a shape not overlapping with the bump electrodes (43a) is formed on the front surface of the second semiconductor circuit layer (2). The first and second semiconductor circuit layers (1a, 2) are made to approach each other, with the back surface of the first semiconductor circuit layer (1a) opposed to the front surface of the second one (2). Thus, the adhesive film (44a) is deformed and at least part of the bump electrodes (43a) are crushed. As a result, the buried interconnection members (15) and the bump electrodes (43a) are mechanically interconnected, and both circuit layers (1a, 2) are bonded with the adhesive film (44a).

Description

本発明は、種々の機能を持つ複数の半導体回路層を積層してなる三次元積層構造を持つ集積回路装置（三次元積層集積回路装置）の製造方法に関し、さらに言えば、積層された前記半導体回路層間の縦方向（積層方向）の機械的・電気的接続を行うための接着剤の配置工程と埋込配線の機械的接続工程とを含む、三次元積層集積回路装置の製造方法に関する。ここに「埋込配線（buried interconnections）」とは、前記半導体回路層の各々の内部に埋設される積層方向の電気的接続用の配線（導体）を言う。   The present invention relates to a method for manufacturing an integrated circuit device (three-dimensional stacked integrated circuit device) having a three-dimensional stacked structure formed by stacking a plurality of semiconductor circuit layers having various functions, and more specifically, the stacked semiconductors. The present invention relates to a method for manufacturing a three-dimensional stacked integrated circuit device, which includes an adhesive placement step for mechanical / electrical connection between circuit layers in the vertical direction (stacking direction) and a mechanical connection step for embedded wiring. Here, “buried interconnections” refer to wirings (conductors) for electrical connection in the stacking direction embedded in each of the semiconductor circuit layers.

近年、複数の半導体チップを積層して三次元構造とした半導体装置が提案されている。例えば、栗野らは１９９９年に発行された「１９９９アイ・イー・ディー・エム テクニカル・ダイジェスト」において、「三次元構造を持つインテリジェント・イメージセンサ・チップ」を提案している（非特許文献１参照）。   In recent years, semiconductor devices having a three-dimensional structure formed by stacking a plurality of semiconductor chips have been proposed. For example, Kurino et al. Proposed an “intelligent image sensor chip having a three-dimensional structure” in “1999 IDM Technical Digest” published in 1999 (see Non-Patent Document 1). ).

このイメージセンサ・チップは、４層構造を持っており、第１半導体回路層にプロセッサ・アレイと出力回路を配置し、第２半導体回路層にデータラッチとマスキング回路を配置し、第３半導体回路層に増幅器とアナログ・デジタル変換器を配置し、第４半導体回路層にイメージセンサ・アレイを配置している。イメージセンサ・アレイの最上面は、マイクロレンズ・アレイを含む石英ガラス層で覆われており、マイクロレンズ・アレイはその石英ガラス層の表面に形成されている。イメージセンサ・アレイ中の各イメージセンサには、半導体受光素子としてフォトダイオードが形成されている。４層構造を構成する各半導体回路層の間は、接着剤を用いて機械的に接続されていると共に、導電性プラグを用いた埋込配線とそれら埋込配線に接触せしめられたマイクロバンプ電極とを用いて電気的に接続されている。   This image sensor chip has a four-layer structure, a processor array and an output circuit are arranged in a first semiconductor circuit layer, a data latch and a masking circuit are arranged in a second semiconductor circuit layer, and a third semiconductor circuit An amplifier and an analog / digital converter are arranged in the layer, and an image sensor array is arranged in the fourth semiconductor circuit layer. The uppermost surface of the image sensor array is covered with a quartz glass layer including the microlens array, and the microlens array is formed on the surface of the quartz glass layer. Each image sensor in the image sensor array is formed with a photodiode as a semiconductor light receiving element. The semiconductor circuit layers constituting the four-layer structure are mechanically connected using an adhesive, and embedded wirings using conductive plugs and microbump electrodes brought into contact with the embedded wirings And are electrically connected.

このイメージセンサ・チップは、各半導体回路層の間の電気的接続にボンディング・ワイヤは使用されていない。したがって、支持基板上に複数の半導体チップを積層・一体化すると共にそれら半導体チップの周囲にボンディング・ワイヤを配置し、それボンディング・ワイヤによって前記半導体チップ間の電気的接続を実現した三次元構造の半導体装置（これは特許文献１に開示されているように従来より公知である）とは異なっている。   This image sensor chip does not use bonding wires for electrical connection between the semiconductor circuit layers. Accordingly, a three-dimensional structure in which a plurality of semiconductor chips are stacked and integrated on a support substrate and bonding wires are arranged around the semiconductor chips, and electrical connection between the semiconductor chips is realized by the bonding wires. It is different from a semiconductor device (this is conventionally known as disclosed in Patent Document 1).

また、李らは、２０００年４月に発行された「日本応用物理学会誌」において、「高度並列画像処理チップ用の三次元集積技術の開発」とのタイトルで、栗野らの提案した上記固体イメージセンサと同様のイメージセンサを含む画像処理チップを提案している（非特許文献２）。   Also, Lee et al. In the “Journal of the Japan Society of Applied Physics” published in April 2000 titled “Development of three-dimensional integration technology for highly parallel image processing chips” proposed by Kurino et al. An image processing chip including an image sensor similar to the image sensor has been proposed (Non-Patent Document 2).

李らの画像処理チップは、栗野らが上記論文で提案した固体イメージセンサとほぼ同じ構造を持っている。   Lee's image processing chip has almost the same structure as the solid-state image sensor proposed by Kurino et al.

上述した三次元積層構造を持つ従来のイメージセンサ・チップと画像処理チップは、いずれも、所望の半導体回路を内蔵した複数の半導体ウェハー（以下、単にウェハーともいう）を積層して互いに固着させた後、得られたウェハー積層体を切断（ダイシング）して複数のチップ群に分割することにより製造される。すなわち、内部に半導体回路を形成した半導体ウェハーをウェハーレベルで積層・一体化することにより三次元積層構造を形成し、それを分割してイメージセンサ・チップまたは画像処理チップを得ているのである。   Both the conventional image sensor chip and the image processing chip having the above-described three-dimensional stacked structure are formed by laminating a plurality of semiconductor wafers (hereinafter also simply referred to as wafers) containing desired semiconductor circuits and fixing them together. Thereafter, the obtained wafer laminate is cut (diced) and divided into a plurality of chip groups. That is, a semiconductor wafer having a semiconductor circuit formed therein is laminated and integrated at a wafer level to form a three-dimensional laminated structure, which is divided to obtain an image sensor chip or an image processing chip.

なお、これら従来のイメージセンサ・チップと画像処理チップでは、当該チップの内部の積層された複数の半導体回路のそれぞれが「半導体回路層」を構成する。
栗野ら、「三次元構造を持つインテリジェント・イメージセンサ・チップ」、１９９９年アイ・イー・ディー・エム テクニカル・ダイジェストｐ．３６．４．１〜３６．４．４（H. Kurino et al.,” Intelligent Image Sensor Chip with Three Dimensional Structure”, 1999 IEDM Technical Digest, pp. 36.4.1 - 36.4.4, 1999） 李ら、「高度並列画像処理チップ用の三次元集積技術の開発」、「日本応用物理学会誌」第３９巻、ｐ．２４７３〜２４７７、第１部４Ｂ、２０００年４月、（K. Lee et al.,” Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip”, Jpn. J. Appl. Phys. Vol. 39, pp. 2474 - 2477, April 2000） 特開２００２−１１０９０２号公報（図１、図４） In these conventional image sensor chips and image processing chips, each of a plurality of stacked semiconductor circuits in the chip constitutes a “semiconductor circuit layer”.
Kurino et al., “Intelligent Image Sensor Chip with Three-Dimensional Structure”, 1999 IDM Technical Digest p. 36.4.1-36.4.4 (H. Kurino et al., “Intelligent Image Sensor Chip with Three Dimensional Structure”, 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4, 1999) Li et al., “Development of three-dimensional integration technology for highly parallel image processing chips”, “The Journal of Japan Society of Applied Physics”, Volume 39, p. 2473-2477, Part 1B, April 2000, (K. Lee et al., “Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip”, Jpn. J. Appl. Phys. Vol. 39 , pp. 2474-2477, April 2000) Japanese Patent Laid-Open No. 2002-110902 (FIGS. 1 and 4)

上述した従来の三次元積層構造を持つイメージセンサ・チップと画像処理チップの製造工程では、ウェハー積層体（これは複数の半導体ウェハーを積層・一体化して構成される）の内部における半導体回路層（ここでは半導体ウェハー）間の縦方向（積層方向）の電気的接続は、各半導体回路層を積層方向に貫通して形成された微細な埋込配線（あるいは導電性プラグ）と、それら埋込配線の端に固着されたマイクロバンプ電極とを使用して行われている。しかし、埋込配線とマイクロバンプ電極の具体的な形成方法は明示されていない。埋込配線もマイクロバンプ電極も数μｍ程度の大きさであって極めて微細であるだけでなく、多数が近接して配置されるので、これらを実現するのは容易ではない。このため、そのような埋込配線とマイクロバンプ電極を使用した信頼性の高い積層方向の電気的接続を実現する方法が要望されている。   In the manufacturing process of the image sensor chip and the image processing chip having the conventional three-dimensional stacked structure described above, the semiconductor circuit layer (which is configured by stacking and integrating a plurality of semiconductor wafers) inside the wafer stack ( Here, the electrical connection in the vertical direction (stacking direction) between the semiconductor wafers is made by fine embedded wirings (or conductive plugs) formed through the semiconductor circuit layers in the stacking direction, and these embedded wirings. This is done using a micro-bump electrode fixed to the end. However, a specific method for forming the embedded wiring and the microbump electrode is not specified. The embedded wiring and the micro bump electrode are not only very fine and have a size of about several μm, but a large number of them are arranged close to each other, so that it is not easy to realize them. Therefore, there is a demand for a method for realizing a highly reliable electrical connection in the stacking direction using such embedded wiring and microbump electrodes.

また、ウェハー積層体の内部において、当該ウェハー積層体を構成する半導体回路層同士（ここでは半導体ウェハー同士）を、高い信頼性をもって機械的に接続する方法も要望されている。これは、マイクロバンプ電極を用いる上述した電気的接続によっても実現は可能であるが、機械的接続の強度と信頼性を増すためには、隣接する半導体回路層間の隙間に電気的絶縁性の接着剤を配置してその接着剤によりそれら半導体回路層同士を接着することが好ましい。この場合、液状または流動状にした接着剤を前記隙間に注入する方法が考えられるが、その際には前記隙間を完全に充填するためにその隙間の容積よりも多めに接着剤を注入する必要がある。その結果、注入後に前記隙間よりはみ出た余分の接着剤を除去するという後処理が必要となる、という難点が生じる。この後処理では、余分の接着剤の除去処理のために薬剤を使用するため、その薬剤が各半導体回路層に与える影響を防止する処置が必要になる等、面倒な作業が増加するからである。よって、このような難点をなくすと共に製造工程数を減らすことのできる方法が望まれるところである。   There is also a demand for a method of mechanically connecting semiconductor circuit layers (here, semiconductor wafers) constituting the wafer laminate with high reliability inside the wafer laminate. This can also be realized by the above-described electrical connection using microbump electrodes. However, in order to increase the strength and reliability of the mechanical connection, an electrically insulating adhesive is provided in the gap between adjacent semiconductor circuit layers. It is preferable to dispose an agent and bond the semiconductor circuit layers to each other with the adhesive. In this case, a method of injecting liquid or fluidized adhesive into the gap can be considered, but in that case, in order to completely fill the gap, it is necessary to inject the adhesive more than the volume of the gap. There is. As a result, there arises a problem that post-treatment is required to remove excess adhesive protruding from the gap after injection. In this post-processing, since a chemical is used to remove excess adhesive, troublesome work such as the need to prevent the influence of the chemical on each semiconductor circuit layer is increased. . Therefore, there is a demand for a method that can eliminate such difficulties and reduce the number of manufacturing steps.

これら二つの要望は、上述した従来の三次元積層構造を持つイメージセンサ・チップと画像処理チップの製造工程において、「ウェハー積層体」に代えて、複数の半導体チップを積層・一体化してなる「チップ積層体」を使用する場合にも言えることである。   These two requests are made by stacking and integrating a plurality of semiconductor chips in place of the “wafer stack” in the manufacturing process of the image sensor chip and the image processing chip having the conventional three-dimensional stacked structure described above. This is also true when using a “chip stack”.

本発明は、これらの点を考慮してなされたものであって、その目的とするところは、積層された半導体回路層間の積層方向の機械的接続及び電気的接続を、埋込配線を使用して容易にかつ高い信頼性をもって実現することができる、三次元積層構造を持つ集積回路装置の製造方法を提供することにある。   The present invention has been made in consideration of these points, and the object of the present invention is to use embedded wiring for mechanical connection and electrical connection in the stacking direction between stacked semiconductor circuit layers. Another object of the present invention is to provide a method for manufacturing an integrated circuit device having a three-dimensional stacked structure, which can be realized easily and with high reliability.

本発明の他の目的は、積層された半導体回路層間の隙間に電気的絶縁性の接着剤を確実に配置することができると共に、前記隙間よりはみ出た余分の接着剤を除去するという後処理を省略することもできる、三次元積層構造を持つ集積回路装置の製造方法を提供することにある。   Another object of the present invention is to perform post-processing of ensuring that an electrically insulating adhesive can be disposed in the gap between the stacked semiconductor circuit layers and removing excess adhesive protruding from the gap. An object of the present invention is to provide a method of manufacturing an integrated circuit device having a three-dimensional stacked structure, which can be omitted.

ここに明記しない本発明の他の目的は、以下の説明及び添付図面から明らかになるであろう。   Other objects of the present invention which are not specified here will become apparent from the following description and the accompanying drawings.

（１） 本発明の集積回路装置の製造方法は、
複数の半導体回路層を支持基板上に積層してなる三次元積層構造を持つ集積回路装置の製造方法であって、
前記三次元積層構造を構成する一つの半導体回路層の内部に、一端が当該半導体回路層の裏面から露出せしめられた複数の埋込配線を形成する工程と、
前記半導体回路層の裏面、あるいは前記三次元積層構造を構成する他の半導体回路層の表面、またはそれらの双方に、複数のバンプ電極を形成する工程と、
前記半導体回路層の裏面、あるいは前記他の半導体回路層の表面、またはそれらの双方に、前記埋込配線の露出端または前記バンプ電極とは重ならない形状を持つ電気的絶縁性の接着剤膜を形成する工程と、
前記接着剤膜を間に介在させながら、前記半導体回路層の裏面と前記他の半導体回路層の表面とを相互に対向させる工程と、
相互に対向せしめられた前記半導体回路層の裏面と前記他の半導体回路層の表面の間隔を狭めることにより、前記接着剤膜を前記半導体回路層の裏面と前記他の半導体回路層の表面との間に残存する隙間内で変形させながら、前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方を変形させて直接、または他の導電性部材を介して相互に機械的接続する工程とを備え、
前記接着剤膜は、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程の終了時に、前記隙間全体に充填せしめられることを特徴とするものである。 (1) A method of manufacturing an integrated circuit device according to the present invention includes:
A method of manufacturing an integrated circuit device having a three-dimensional stacked structure in which a plurality of semiconductor circuit layers are stacked on a support substrate,
Forming a plurality of embedded wirings, one end of which is exposed from the back surface of the semiconductor circuit layer, inside one semiconductor circuit layer constituting the three-dimensional stacked structure;
Forming a plurality of bump electrodes on the back surface of the semiconductor circuit layer, or on the surface of another semiconductor circuit layer constituting the three-dimensional stacked structure, or both of them;
An electrically insulating adhesive film having a shape that does not overlap the exposed end of the embedded wiring or the bump electrode on the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or both of them. Forming, and
Making the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer face each other while interposing the adhesive film therebetween,
By narrowing the distance between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer opposed to each other, the adhesive film is placed between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. A step of deforming at least one of the exposed end of the embedded wiring and the bump electrode while being deformed in a gap remaining therebetween, and mechanically connecting to each other directly or via another conductive member; Prepared,
The adhesive film is filled in the entire gap at the end of the mechanical connection step between the exposed end of the embedded wiring and the bump electrode.

（２） 本発明の集積回路装置の製造方法では、上述したように、三次元積層構造を構成する一つの半導体回路層の内部に一端が当該半導体回路層の裏面から露出せしめられた複数の埋込配線を形成する一方、前記半導体回路層の裏面、あるいは前記三次元積層構造を構成する他の半導体回路層の表面、またはそれらの双方に、複数のバンプ電極を形成する。その後、前記半導体回路層の裏面、あるいは前記他の半導体回路層の表面、またはそれらの双方に、前記埋込配線の露出端または前記バンプ電極とは重ならない形状を持つ電気的絶縁性の接着剤膜を形成する。さらに、前記接着剤膜を間に介在させながら前記半導体回路層の裏面と前記他の半導体回路層の表面とを相互に対向させた後、前記半導体回路層の裏面と前記他の半導体回路層の表面の間隔を狭め、もって前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方を変形させて直接、または他の導電性部材を介して相互に機械的接続する。この時、前記接着剤膜は、前記半導体回路層の裏面と前記他の半導体回路層の表面との間に残存する隙間内で変形せしめられると共に、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程の終了時に前記隙間全体に充填せしめられる。   (2) In the method of manufacturing an integrated circuit device according to the present invention, as described above, a plurality of buried portions in which one end is exposed from the back surface of the semiconductor circuit layer inside one semiconductor circuit layer constituting the three-dimensional stacked structure. While forming the embedded wiring, a plurality of bump electrodes are formed on the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer constituting the three-dimensional stacked structure, or both of them. Thereafter, an electrically insulating adhesive having a shape that does not overlap the exposed end of the embedded wiring or the bump electrode on the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or both of them. A film is formed. Further, after the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer are opposed to each other with the adhesive film interposed therebetween, the back surface of the semiconductor circuit layer and the other semiconductor circuit layer The distance between the surfaces is narrowed, so that at least one of the exposed end and the bump electrode of the embedded wiring is deformed and mechanically connected to each other directly or via another conductive member. At this time, the adhesive film is deformed in a gap remaining between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer, and the exposed end of the embedded wiring and the bump electrode The entire gap is filled at the end of the mechanical connection process.

このため、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程の終了時に前記接着剤膜の全体積が前記半導体回路層と前記他の半導体回路層の間の隙間に残存する前記隙間の体積にほぼ等しくなるように、前記接着剤膜の全体積を調整することにより、前記隙間に必要量の接着剤を配置することが可能となり、しかもその接着剤が前記隙間よりはみ出ないようにすることができる。よって、三次元積層構造を構成する積層された半導体回路層間の隙間に電気的絶縁性の接着剤を確実に配置することができると共に、前記隙間よりはみ出た余分の接着剤を除去するという後処理を省略することができる、という効果が得られる。   Therefore, the entire volume of the adhesive film remains in the gap between the semiconductor circuit layer and the other semiconductor circuit layer at the end of the mechanical connection process between the exposed end of the embedded wiring and the bump electrode. By adjusting the total volume of the adhesive film so as to be substantially equal to the volume of the gap, it becomes possible to arrange a necessary amount of adhesive in the gap, and the adhesive does not protrude from the gap. Can be. Therefore, it is possible to reliably dispose the electrically insulating adhesive in the gap between the laminated semiconductor circuit layers constituting the three-dimensional laminated structure, and to remove the excess adhesive protruding from the gap The effect that can be omitted is obtained.

また、前記埋込配線の前記露出端と前記バンプ電極との機械的接続は、前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方を変形させて直接、または他の導電性部材を介して間接的に実行されるので、前記埋込配線の前記露出端と前記バンプ電極との機械的接続が強固になる。しかも、前記接着剤膜は、変形によって前記隙間に充填されるので、前記半導体回路層と前記他の半導体回路層の接着も確実になる。このように、上記したような容易な工程の組み合わせによって、前記半導体回路層と前記他の半導体回路層の機械的接続及び電気的接続に高い信頼性が得られる。換言すれば、三次元積層構造を構成する積層された半導体回路層間の積層方向の機械的接続及び電気的接続を、埋込配線を使用して容易かつ高い信頼性をもって実現することができる、という効果が得られる。   Further, the mechanical connection between the exposed end of the embedded wiring and the bump electrode may be performed directly or through another conductive member by deforming at least one of the exposed end of the embedded wiring and the bump electrode. Therefore, the mechanical connection between the exposed end of the embedded wiring and the bump electrode is strengthened. In addition, since the adhesive film fills the gaps by deformation, the bonding between the semiconductor circuit layer and the other semiconductor circuit layer is ensured. As described above, high reliability can be obtained in mechanical connection and electrical connection between the semiconductor circuit layer and the other semiconductor circuit layer by a combination of the easy processes as described above. In other words, the mechanical connection and electrical connection in the stacking direction between the stacked semiconductor circuit layers constituting the three-dimensional stacked structure can be realized easily and with high reliability using the embedded wiring. An effect is obtained.

（３） 本発明の集積回路装置の製造方法において、「支持基板」は、複数の半導体回路層を支持するに足る剛性を持つものであればよく、その材質は任意である。半導体であってもよいし、ガラスであってもよいし、その他の材質であってもよい。内部に回路が形成された半導体基板、すなわち、いわゆるＬＳＩウェハーでもよい。   (3) In the method for manufacturing an integrated circuit device of the present invention, the “support substrate” may be any material as long as it has sufficient rigidity to support a plurality of semiconductor circuit layers, and the material thereof is arbitrary. It may be a semiconductor, glass, or other material. A semiconductor substrate having a circuit formed therein, that is, a so-called LSI wafer may be used.

「半導体回路層」と「他の半導体回路層」は、いずれも、半導体回路の層、換言すれば、層状に形成された半導体回路を意味する。したがって、「半導体回路層」は、「半導体基板」と、その半導体基板の内部または表面に形成された「素子」または「回路」とを有していればよく、他の構成は任意である。   The “semiconductor circuit layer” and the “other semiconductor circuit layer” mean a semiconductor circuit layer, in other words, a semiconductor circuit formed in a layer shape. Therefore, the “semiconductor circuit layer” may include a “semiconductor substrate” and “elements” or “circuits” formed inside or on the surface of the semiconductor substrate, and other configurations are arbitrary.

前記「半導体基板」の内部または表面には、何らかの「回路」（例えば、増幅回路、信号処理回路など、あるいは所定の機能を提供する集積回路）が形成されるのが通常であるが、何らかの「素子」（例えば、受光素子）のみが形成されていてもよい。例えば、アレイ状に配置された多数の「受光素子」だけが、「半導体基板」の内部または表面に形成されていてもよい。「素子」としては、トランジスタ等の能動素子と、抵抗器等の受動素子とがあるが、いずれであってもよい。「能動素子」としては、典型的には、占有面積の小ささ等を考慮してＭＯＳ電界効果トランジスタ（Metal-Oxide-Semiconductor Field-Effect Transistor、ＭＯＳＦＥＴ、以下「ＭＯＳトランジスタ」という）が使用されるが、ＭＯＳトランジスタ以外のトランジスタでもよいし、ダイオード等でもよい。「受動素子」としては、例えば抵抗器、容量素子等が使用される。   Usually, some “circuit” (for example, an amplifier circuit, a signal processing circuit, or an integrated circuit providing a predetermined function) is formed inside or on the surface of the “semiconductor substrate”. Only an “element” (for example, a light receiving element) may be formed. For example, only a large number of “light receiving elements” arranged in an array may be formed inside or on the surface of the “semiconductor substrate”. “Elements” include active elements such as transistors and passive elements such as resistors. As the “active element”, a MOS field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET, hereinafter referred to as “MOS transistor”) is typically used in consideration of a small occupied area and the like. However, a transistor other than a MOS transistor, a diode, or the like may be used. As the “passive element”, for example, a resistor, a capacitive element or the like is used.

前記「半導体基板」は、単一の半導体部材（例えば半導体ウェハーまたは半導体チップ）により形成されていてもよいし、複数の半導体部材（例えば半導体ウェハーまたは半導体チップ）により形成されていてもよい。また、前記「半導体基板」の物理寸法には制限はなく、半導体ウェハーのサイズ（ウェハーサイズ）でもよいし、半導体ウェハーを分割して得られるチップのサイズ（チップサイズ）でもよいし、ウェハーサイズとチップサイズの中間のサイズであってもよいし、ウェハーサイズより大きいサイズであってもよい。また、前記「半導体基板」の材質は任意であり、所望の半導体素子や回路を形成できるものであれば、シリコンでもよいし、化合物半導体でもよいし、その他の半導体でもよい。「半導体基板」の構造も任意であり、半導体製の単なる板でもよいし、いわゆるＳＯＩ（Silicon On Insulator）基板でもよい。   The “semiconductor substrate” may be formed of a single semiconductor member (for example, a semiconductor wafer or a semiconductor chip), or may be formed of a plurality of semiconductor members (for example, a semiconductor wafer or a semiconductor chip). The physical dimensions of the “semiconductor substrate” are not limited, and may be the size of a semiconductor wafer (wafer size), the size of a chip obtained by dividing a semiconductor wafer (chip size), or the wafer size. It may be an intermediate size of the chip size or a size larger than the wafer size. The material of the “semiconductor substrate” is arbitrary, and may be silicon, a compound semiconductor, or other semiconductors as long as a desired semiconductor element or circuit can be formed. The structure of the “semiconductor substrate” is also arbitrary, and may be a simple plate made of a semiconductor or a so-called SOI (Silicon On Insulator) substrate.

「埋込配線」とは、半導体回路層の各々の内部に埋設される積層方向の電気的接続用の配線または導体を言う。「埋込配線」は、通常、半導体基板に形成された「トレンチ」の内壁面全体を覆う「絶縁膜」と、その絶縁膜の内側の空間に充填された（埋め込まれた）「導電性材料」（「導電性プラグ」と呼ばれることが多い）とから構成される。しかし、この構成に限定されるわけではない。   “Built-in wiring” refers to a wiring or conductor for electrical connection in the stacking direction embedded in each semiconductor circuit layer. The “embedded wiring” is usually an “insulating film” that covers the entire inner wall surface of the “trench” formed in the semiconductor substrate, and a “conductive material” that is filled (embedded) in the space inside the insulating film. "(Often referred to as" conductive plug "). However, it is not necessarily limited to this configuration.

ここで、「トレンチ」とは、所望の深さを持ち、埋込配線となる導電性材料を収容するものであればよく、構成は任意である。「トレンチ」の深さ、開口形状、開口寸法、断面形状等は、必要に応じて任意に設定できる。「トレンチ」の形成方法は、半導体基板をその表面側から選択的に除去して形成できるものであれば、任意の方法が使用できる。例えば、マスクを用いた異方性エッチング法が好適に使用できる。   Here, the “trench” may have any desired depth as long as it has a desired depth and accommodates a conductive material that becomes an embedded wiring. The depth, opening shape, opening size, cross-sectional shape, etc. of the “trench” can be arbitrarily set as required. As a method for forming the “trench”, any method can be used as long as it can be formed by selectively removing the semiconductor substrate from the surface side. For example, an anisotropic etching method using a mask can be suitably used.

「トレンチ」の内壁面を覆う「絶縁膜」は、半導体基板と「トレンチ」の内部に充填される「導電性材料」とを電気的に絶縁できるものであれば、任意の絶縁膜が使用できる。例えば、二酸化シリコン（ＳｉＯ2）、窒化シリコン（ＳｉＮx）等が好適に使用できる。「絶縁膜」の形成方法は、任意である。 As the “insulating film” covering the inner wall surface of the “trench”, any insulating film can be used as long as it can electrically insulate the semiconductor substrate and the “conductive material” filled in the “trench”. . For example, silicon dioxide (SiO 2 ), silicon nitride (SiN x ), etc. can be suitably used. A method of forming the “insulating film” is arbitrary.

「トレンチ」の内部に充填される「導電性材料」は、半導体回路層間の電気的接続に使用できるものであればよく、任意の材料が使用できる。例えば、ポリシリコン等の半導体、タングステン（Ｗ）、銅（Ｃｕ）、アルミニウム（Ａｌ）等の金属が好適に使用できる。「導電性材料」の充填方法は、半導体基板の片面から「導電性材料」を「トレンチ」の内部に充填できるものであれば、任意の方法が使用できる。   The “conductive material” filled in the “trench” may be any material that can be used for electrical connection between the semiconductor circuit layers, and any material can be used. For example, a semiconductor such as polysilicon or a metal such as tungsten (W), copper (Cu), or aluminum (Al) can be preferably used. As the filling method of the “conductive material”, any method can be used as long as the “conductive material” can be filled into the “trench” from one side of the semiconductor substrate.

「バンプ電極」とは、半導体回路層間の積層方向の電気的接続に使用可能なバンプ（bump、こぶ）状の電極であれば、任意の構成のものを使用できる。「バンプ電極」の材料としては、半導体回路層間の積層方向の電気的接続に使用可能な導電性を有していれば、任意のものを使用できる。   The “bump electrode” may have any configuration as long as it is a bump-like electrode that can be used for electrical connection in the stacking direction between semiconductor circuit layers. As the material of the “bump electrode”, any material can be used as long as it has conductivity that can be used for electrical connection in the stacking direction between the semiconductor circuit layers.

「埋込配線」の露出端及び「バンプ電極」の少なくとも一方は、前記接着剤膜を間に介在させながら二つの半導体回路層を相互に対向させてから両者の間隔を狭めることにより、前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方が変形し、直接または他のバンプ電極を介して相互に機械的接続されるものである必要がある。「バンプ電極」は、こうして変形することによって相手部材（埋込配線や他のバンプ電極など）との接触面積が広がり、その結果として両者の機械的・電気的接続の信頼性が向上する。前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方の「変形」は、塑性変形でもよいし、少なくとも一部が軟化または流動化することによる変形でもよい。   At least one of the exposed end of the “embedded wiring” and the “bump electrode” is formed by allowing the two semiconductor circuit layers to face each other while interposing the adhesive film therebetween, and then reducing the distance between the two. It is necessary that at least one of the exposed end of the embedded wiring and the bump electrode is deformed and mechanically connected to each other directly or via another bump electrode. By deforming the “bump electrode” in this way, the contact area with the mating member (embedded wiring, other bump electrode, etc.) is expanded, and as a result, the reliability of the mechanical and electrical connection between the two is improved. “Deformation” of at least one of the exposed end of the embedded wiring and the bump electrode may be plastic deformation, or may be deformation due to softening or fluidization of at least a part thereof.

「バンプ電極」の材質が、「バンプ電極」と埋込配線とを加熱・加圧しながら接触させた時に両者が互いに接合するもの（例えば、インジウム（Ｉｎ）と金（Ａｕ）の積層体、すなわちＩｎ／Ａｕ）であれば、両者を直接接触させて機械的に接続すればよい。しかし、バンプ電極の材質が、当該バンプ電極と埋込配線とを加熱・加圧しながら接触させても両者が互いに接合しない場合（例えば、タングステン（Ｗ））は、適当な接合用金属を挟んで両者の機械的接続を行う必要がある。接合用金属としては、例えば、Ｉｎ−Ａｕ合金、錫（Ｓｎ）−金（Ａｇ）合金、Ｉｎ単体、Ｓｎ単体等を使用することができる。この場合、その接合用金属が「他の導電性部材」となる。   The material of the “bump electrode” is a material in which the “bump electrode” and the embedded wiring are brought into contact with each other while being heated and pressed (for example, a laminate of indium (In) and gold (Au), In / Au), the two may be brought into direct contact and mechanically connected. However, if the material of the bump electrode is not bonded to each other even if the bump electrode and the embedded wiring are brought into contact with each other while being heated and pressed (for example, tungsten (W)), an appropriate bonding metal is sandwiched between them. It is necessary to make a mechanical connection between them. As the bonding metal, for example, an In—Au alloy, a tin (Sn) -gold (Ag) alloy, an In simple substance, an Sn simple substance, or the like can be used. In this case, the joining metal becomes “another conductive member”.

「バンプ電極」の構成と形成方法は任意であるから、別個に形成されたバンプ状の導電性材料片を、前記半導体回路層の裏面あるいは前記他の半導体回路層の表面、またはそれらの双方の所定位置に固着させて形成してもよいし、前記半導体回路層の裏面あるいは前記他の半導体回路層の表面、またはそれらの双方の所定位置に導電性材料をメッキ法等によって直接堆積させて形成してもよい。また、前記半導体回路層の裏面あるいは前記他の半導体回路層の表面に形成された配線を利用して形成してもよい。   Since the configuration and formation method of the “bump electrode” are arbitrary, a separately formed bump-shaped conductive material piece is attached to the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or both of them. It may be formed by being fixed at a predetermined position, or formed by directly depositing a conductive material on the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or a predetermined position on both of them by a plating method or the like. May be. Moreover, you may form using the wiring formed in the back surface of the said semiconductor circuit layer, or the surface of the said other semiconductor circuit layer.

「他の導電性部材」は、半導体回路層間の電気的接続に使用できるものであれば任意の部材が使用できる。典型的には、上述した「バンプ電極」と同様のバンプ電極が使用されるが、これに限定されるわけではない。上述した「接合用金属」も「他の導電性部材」として使用可能である。   As the “other conductive member”, any member can be used as long as it can be used for electrical connection between the semiconductor circuit layers. Typically, a bump electrode similar to the “bump electrode” described above is used, but is not limited thereto. The “joining metal” described above can also be used as “other conductive member”.

「電気的絶縁性の接着剤膜」は、前記半導体回路層と前記他の半導体回路層とを接着して一体化することができる電気的絶縁性の接着剤の膜であって、前記埋込配線の露出端または前記バンプ電極とは重ならない形状にパターン化した後も粘性を有しており且つ所定条件下で少なくとも一部が軟化または流動化するものである。例えば、ポリイミド樹脂、ＳＯＧ（Spin On Glass）材料等が使用できる。これらの接着剤の中では、ポリイミド樹脂が特に好ましい。ポリイミド樹脂は、取り扱いが容易であり、しかも化学的安定性が高いからである。   The “electrically insulating adhesive film” is an electrically insulating adhesive film capable of bonding and integrating the semiconductor circuit layer and the other semiconductor circuit layer. It remains viscous even after patterning into a shape that does not overlap the exposed end of the wiring or the bump electrode, and at least part of the wiring is softened or fluidized under a predetermined condition. For example, polyimide resin, SOG (Spin On Glass) material, etc. can be used. Among these adhesives, polyimide resin is particularly preferable. This is because the polyimide resin is easy to handle and has high chemical stability.

「相互に対向せしめられた前記半導体回路層の裏面と前記他の半導体回路層の表面の間隔を狭めることにより、前記接着剤膜を前記半導体回路層の裏面と前記他の半導体回路層の表面との間に残存する隙間内で変形させながら、前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方を変形させて直接、または他の導電性部材を介して相互に機械的接続する工程」を実施する方法は、特に限定されない。典型的には、「溶着」または「圧接」によって、前記埋込配線の露出端部と対応する前記バンプ電極とを直接、または他の導電性部材を介して機械的接続するが、これ以外の方法でもよい。直接的に「溶着」または「圧接」ができない場合は、適当な接合用金属を間に挟んで機械的接続を行ってもよい。   “By narrowing the distance between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer opposed to each other, the adhesive film is formed between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. A process of deforming at least one of the exposed end of the embedded wiring and the bump electrode while being deformed in a gap remaining between the two, and mechanically connecting to each other directly or via another conductive member. The method of implementing is not particularly limited. Typically, the exposed end portion of the embedded wiring and the corresponding bump electrode are mechanically connected directly or through another conductive member by “welding” or “pressure welding”. It may be a method. In the case where “welding” or “pressure welding” cannot be performed directly, mechanical connection may be performed with an appropriate bonding metal interposed therebetween.

この工程は、例えば、公知の半導体ウェハー積層装置（例えば、特開平５−１６０３４０号公報（特許第２９８４４４１号）に記載の「三次元ＬＳＩ積層装置」を参照）を用いて実施することができる。同様の装置は、下記の論文にも開示されている。   This step can be performed using, for example, a known semiconductor wafer laminating apparatus (for example, see “three-dimensional LSI laminating apparatus” described in Japanese Patent Laid-Open No. 5-160340 (Japanese Patent No. 2984441)). Similar devices are also disclosed in the following articles:

松本ら、「接着剤注入法を用いた新三次元ウェハー接合技術」、１９９８年、応用物理学会誌、１（３Ｂ）、ｐ．１２１７−１２２１（Takuji Matsumoto, Masakazu Satoh, Katsuyuki Sakuma, Hiroyuki Kurino, Nobuaki Miyakawa, Hikotaro Itani and Mitsumasa Koyanagi, “New three-dimensional wafer bonding technology using the adhesive injection method,” Jpn. J. Appl. Phys., 1 (3B), pp.1217-1221, 1998）
「前記接着剤膜を前記半導体回路層の裏面と前記他の半導体回路層の表面との間に残存する隙間内で変形させながら、前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方を変形させて直接、または他の導電性部材を介して相互に機械的接続する」ために、前記埋込配線及び前記バンプ電極を所定温度まで加熱するのが好ましい。その理由は、加熱により、前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方が部分的に溶融状態になって変形し、あるいは、前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方が軟化して加圧変形可能となるため、容易に所望の機械的接続を実現できるからである。同様に、加熱によって、前記接着剤膜の少なくとも一部が軟化あるいは流動化するため、前記半導体回路層の裏面と前記他の半導体回路層の表面の間隔を狭めることによって前記接着剤膜も変形可能となり、前記隙間全体への充填が実現できるからである。 Matsumoto et al., “New 3D Wafer Bonding Technology Using Adhesive Injection Method”, 1998, Journal of Applied Physics, 1 (3B), p. 1217-1221 (Takuji Matsumoto, Masakazu Satoh, Katsuyuki Sakuma, Hiroyuki Kurino, Nobuaki Miyakawa, Hikotaro Itani and Mitsumasa Koyanagi, “New three-dimensional wafer bonding technology using the adhesive injection method,” Jpn. J. Appl. Phys., 1 (3B), pp.1217-1221, 1998)
“At least one of the exposed end of the embedded wiring and the bump electrode is deformed while the adhesive film is deformed in a gap remaining between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. It is preferable to heat the embedded wiring and the bump electrode to a predetermined temperature in order to be deformed and mechanically connected to each other directly or via another conductive member. The reason is that at least one of the exposed end of the embedded wiring and the bump electrode is partially melted and deformed by heating, or at least the exposed end of the embedded wiring and the bump electrode This is because one side is softened and can be deformed under pressure, so that a desired mechanical connection can be easily realized. Similarly, since at least a part of the adhesive film is softened or fluidized by heating, the adhesive film can be deformed by reducing the distance between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. This is because the entire gap can be filled.

「前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程の終了時に、前記隙間全体に充填せしめられる前記接着剤膜」は、当該機械的接続工程の中で、あるいはその後に実施される硬化工程において、適当な方法で硬化せしめられる。前記接着剤膜の硬化方法としては、実施の容易性から考えて、所定温度への加熱（とその後の放熱冷却）が好適であるが、これに限定されるわけではない。例えば、紫外線の透過が可能であれば紫外線照射等によっても硬化させることができるし、適当な薬剤の添加によっても硬化可能である。   “The adhesive film filled in the entire gap at the end of the mechanical connection step between the exposed end of the embedded wiring and the bump electrode” is performed during or after the mechanical connection step. In the curing step to be performed, curing is performed by an appropriate method. As a method for curing the adhesive film, in view of ease of implementation, heating to a predetermined temperature (and subsequent heat radiation cooling) is preferable, but is not limited thereto. For example, if ultraviolet rays can be transmitted, they can be cured by ultraviolet irradiation or the like, or can be cured by adding an appropriate drug.

（４） 本発明の集積回路装置の製造方法の好ましい例では、前記接着剤膜が、複数の島状の接着剤要素に分割された構成を持つ。この場合、前記半導体回路層の裏面と前記他の半導体回路層の表面との間に残存する気体を、前記半導体回路層の裏面と前記他の半導体回路層の表面との間の前記隙間が狭められた後であっても、島状の接着剤要素の間を通って外部に逃がしやすいという利点がある。   (4) In a preferred example of the method for manufacturing an integrated circuit device according to the present invention, the adhesive film has a configuration in which the adhesive film is divided into a plurality of island-shaped adhesive elements. In this case, the gap between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer is narrowed by the gas remaining between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer. Even after being applied, there is an advantage that it is easy to escape outside through the island-like adhesive elements.

本発明の集積回路装置の製造方法の他の好ましい例では、前記埋込配線の前記露出端または前記バンプ電極と重なる領域と、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程の終了時に前記埋込配線の前記露出端、前記バンプ電極及び前記他の導電性部材の少なくとも一つが変形することによって生じる変形分を吸収するための領域とを除いて、前記接着剤膜が、複数の接着剤要素に分割されずに連続的に形成された構成を持つ。この場合、複数の島状の接着剤要素に分割される場合よりも、前記接着剤膜のパターン化が容易であるという利点がある。   In another preferred example of the method for manufacturing an integrated circuit device of the present invention, the exposed end of the embedded wiring or a region overlapping the bump electrode, and mechanical connection between the exposed end of the embedded wiring and the bump electrode Except for the region for absorbing deformation caused by deformation of at least one of the exposed end of the embedded wiring, the bump electrode, and the other conductive member at the end of the process, the adhesive film , Having a structure formed continuously without being divided into a plurality of adhesive elements. In this case, there is an advantage that patterning of the adhesive film is easier than the case where the adhesive film is divided into a plurality of island-shaped adhesive elements.

この例では、前記接着剤膜が、相互に対向せしめられた前記半導体回路層の裏面と前記他の半導体回路層の表面の間隔を狭める際に、前記半導体回路層の裏面と前記他の半導体回路層の表面との間の隙間内に存在する気体を外部に逃がす空隙（スリット等）を有しているのが好ましい。前記空隙を介して前記気体の排除がより効率的に行われるからである。   In this example, when the gap between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer that are opposed to each other is reduced, the adhesive film forms the back surface of the semiconductor circuit layer and the other semiconductor circuit. It is preferable to have a gap (such as a slit) that allows gas existing in the gap between the layers to escape to the outside. This is because the gas is more efficiently eliminated through the gap.

本発明の集積回路装置の製造方法のさらに他の好ましい例では、前記埋込配線または前記バンプ電極とは重ならない形状にパターン化された電気的絶縁性の他の接着剤膜を、前記他の半導体回路層の表面に形成する工程を含んでおり、前記埋込配線の前記露出端と前記バンプ電極とが機械的に接続される際に、前記接着剤膜と前記他の接着剤膜とが相互に接着される。この例では、２枚の接着剤膜を使用するので、前記半導体回路層の裏面と前記他の半導体回路層の表面との間の隙間が比較的大きい場合でも、その隙間全体に確実に接着剤を充填することができるという利点がある。   In still another preferable example of the method for manufacturing an integrated circuit device of the present invention, another electrically insulating adhesive film patterned in a shape that does not overlap with the embedded wiring or the bump electrode is formed on the other circuit. A step of forming on the surface of the semiconductor circuit layer, and when the exposed end of the embedded wiring and the bump electrode are mechanically connected, the adhesive film and the other adhesive film are Bonded to each other. In this example, since two adhesive films are used, even when the gap between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer is relatively large, the adhesive is surely applied to the entire gap. There is an advantage that can be filled.

この例では、種々の組み合わせが可能である。例えば、（ａ）前記半導体回路層の裏面に形成される前記接着剤膜と、前記他の半導体回路層の表面に形成される前記他の接着剤膜との双方が、複数の島状の接着剤要素に分割された構成を持つ。あるいは、（ｂ）前記埋込配線の前記露出端または前記バンプ電極と重なる領域と、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程の終了時に前記埋込配線の前記露出端、前記バンプ電極及び前記他の導電性部材の少なくとも一つが変形することによって生じる変形分を吸収するための領域とを除いて、前記半導体回路層の裏面に形成される前記接着剤膜と、前記他の半導体回路層の表面に形成される前記他の接着剤膜との双方が、複数の接着剤要素に分割されずに連続的に形成された構成を持つ。あるいは、（ｃ）前記半導体回路層の裏面に形成される前記接着剤膜と、前記他の半導体回路層の表面に形成された前記他の接着剤膜とのいずれか一方が、複数の島状の接着剤要素に分割された構成を持ち、他方が、前記埋込配線の前記露出端または前記バンプ電極と重なる領域と、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程の終了時に前記埋込配線の前記露出端、前記バンプ電極及び前記他の導電性部材の少なくとも一つが変形することによって生じる変形分を吸収するための領域とを除いて、複数の接着剤要素に分割されずに連続的に形成された構成を持つ。   In this example, various combinations are possible. For example, (a) both the adhesive film formed on the back surface of the semiconductor circuit layer and the other adhesive film formed on the surface of the other semiconductor circuit layer have a plurality of island-shaped bonds. It has a structure divided into agent elements. Alternatively, (b) the exposure of the embedded wiring at the end of the mechanical connection step between the exposed end of the embedded wiring or the bump electrode and the exposed end of the embedded wiring and the bump electrode. The adhesive film formed on the back surface of the semiconductor circuit layer, except for an end, a region for absorbing deformation caused by deformation of at least one of the bump electrode and the other conductive member, Both the other adhesive film formed on the surface of the other semiconductor circuit layer have a configuration formed continuously without being divided into a plurality of adhesive elements. Or (c) any one of the adhesive film formed on the back surface of the semiconductor circuit layer and the other adhesive film formed on the surface of the other semiconductor circuit layer has a plurality of island shapes A mechanical connection step between the exposed end of the embedded wiring or the bump electrode and the exposed end of the embedded wiring and the bump electrode. At the end of the plurality of adhesive elements, except for an area for absorbing deformation caused by deformation of at least one of the exposed end of the embedded wiring, the bump electrode, and the other conductive member. It has a structure formed continuously without being divided.

本発明の集積回路装置の製造方法のさらに他の好ましい例では、複数の前記埋込配線の前記露出端の各々に直接、前記バンプ電極が接合せしめられる。この場合、前記埋込配線の側にバンプ電極等の導電性部材を形成する工程が不要となるから、工程数が減少するという利点がある。   In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, the bump electrode is bonded directly to each of the exposed ends of the plurality of embedded wirings. In this case, there is an advantage that the number of steps is reduced because a step of forming a conductive member such as a bump electrode on the side of the embedded wiring becomes unnecessary.

この例では、好ましくは、前記埋込配線の前記露出端が、前記半導体回路層の裏面から突出して形成される。この場合、前記埋込配線の側にバンプ電極等の導電性部材を形成する工程が不要となるだけでなく、前記埋込配線と前記バンプ電極との機械的接続がいっそう容易であるという利点がある。   In this example, it is preferable that the exposed end of the embedded wiring protrudes from the back surface of the semiconductor circuit layer. In this case, not only is a step of forming a conductive member such as a bump electrode on the side of the embedded wiring unnecessary, but there is an advantage that mechanical connection between the embedded wiring and the bump electrode is easier. is there.

本発明の集積回路装置の製造方法のさらに他の好ましい例では、複数の前記埋込配線の前記露出端の各々に、前記他の導電性部材として他のバンプ電極を形成する工程を含んでおり、前記他のバンプ電極を介して前記埋込配線の前記露出端と前記バンプ電極とが相互に機械的接続される。この場合、前記他のバンプ電極を形成する工程が必要になるが、前記他のバンプ電極の分だけ前記バンプ電極の高さ（厚さ）を減少することができ、その結果、前記バンプ電極の形成が容易になるという利点がある。   According to still another preferred example of the method for manufacturing an integrated circuit device of the present invention, the method includes a step of forming another bump electrode as the other conductive member at each of the exposed ends of the plurality of embedded wirings. The exposed end of the embedded wiring and the bump electrode are mechanically connected to each other through the other bump electrode. In this case, although the step of forming the other bump electrode is required, the height (thickness) of the bump electrode can be reduced by the amount of the other bump electrode. There is an advantage that formation becomes easy.

本発明の集積回路装置の製造方法のさらに他の好ましい例では、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程が、加熱下で実行され、その際に前記接着剤膜の少なくとも一部が軟化または流動化するように加熱温度が設定される。この例では、当該機械的接続工程が容易に実行できるという利点がある。   In still another preferred example of the method for manufacturing an integrated circuit device according to the present invention, a mechanical connection step between the exposed end of the embedded wiring and the bump electrode is performed under heating, and the adhesive film is formed at that time. The heating temperature is set so that at least a part of the material is softened or fluidized. In this example, there exists an advantage that the said mechanical connection process can be performed easily.

本発明の集積回路装置の製造方法のさらに他の好ましい例では、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程が、加熱下で実行され、その際に前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方が塑性変形して、直接または前記他の導電性部材を介して相互に機械的接続されるように加熱温度が設定される。この例では、当該機械的接続工程が容易に実行できるという利点がある。   In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, a mechanical connection step between the exposed end of the embedded wiring and the bump electrode is performed under heating, and at that time, the embedded wiring The heating temperature is set so that at least one of the exposed end and the bump electrode is plastically deformed and mechanically connected to each other directly or via the other conductive member. In this example, there exists an advantage that the said mechanical connection process can be performed easily.

本発明の集積回路装置の製造方法のさらに他の好ましい例では、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程が、加熱下で実行され、その際に前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一部が軟化または流動化することによって変形して、直接または前記他の導電性部材を介して相互に機械的接続されるように加熱温度が設定される。この例では、当該機械的接続工程が容易に実行できるという利点がある。   In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, a mechanical connection step between the exposed end of the embedded wiring and the bump electrode is performed under heating, and at that time, the embedded wiring A heating temperature is set such that at least a part of the exposed end of the bump and the bump electrode are deformed by being softened or fluidized and mechanically connected to each other directly or via the other conductive member. . In this example, there exists an advantage that the said mechanical connection process can be performed easily.

本発明の集積回路装置の製造方法のさらに他の好ましい例では、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程において前記半導体回路層の裏面と前記他の半導体回路層の表面との間隔を狭めた時に、前記埋込配線の前記露出端と前記バンプ電極とが直接、または前記他の導電性部材を介して接触する前に、前記接着剤膜がその対向する面（すなわち、前記半導体回路層の裏面、前記他の半導体回路層の表面、または他の接着剤膜の面）に接触するように、前記埋込配線の突出高さと前記バンプ電極の高さと前記接着剤膜の厚さとが設定される。この場合、前記埋込配線の前記露出端と前記バンプ電極とが直接的または間接的に接触する前に前記接着剤膜がその対向する面に接触するので、前記接着剤膜の変形量が大きくなる。したがって、この例は、前記埋込配線及び前記バンプ電極のレイアウトの関係から、前記接着剤膜の変形量を大きくせざるを得ない場合（例えば、バンプ電極の材料として変形しにくい材料を使っているような場合）に好適に使用できる。   In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, the back surface of the semiconductor circuit layer and the other semiconductor circuit layer are mechanically connected in the mechanical connection step between the exposed end of the embedded wiring and the bump electrode. When the gap between the surface and the surface of the adhesive film is reduced, before the exposed end of the embedded wiring and the bump electrode come into contact directly or via the other conductive member, That is, the protruding height of the embedded wiring, the height of the bump electrode, and the adhesive so as to contact the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or the surface of another adhesive film) The thickness of the film is set. In this case, since the adhesive film contacts the opposite surface before the exposed end of the embedded wiring and the bump electrode are directly or indirectly contacted, the deformation amount of the adhesive film is large. Become. Therefore, in this example, the amount of deformation of the adhesive film must be increased due to the layout of the embedded wiring and the bump electrode (for example, using a material that is difficult to deform as the material of the bump electrode). In such a case).

本発明の集積回路装置の製造方法のさらに他の好ましい例では、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程において前記半導体回路層の裏面と前記他の半導体回路層の表面との間隔を狭めた時に、前記接着剤膜がその対向する面（すなわち、前記半導体回路層の裏面、前記他の半導体回路層の表面、または他の接着剤膜の面）に接触する前に、前記埋込配線の前記露出端と前記バンプ電極とが直接、または前記他の導電性部材を介して接触するように、前記埋込配線の突出高さと前記バンプ電極の高さと前記接着剤膜の厚さとが設定される。この場合、前記接着剤膜がその対向する面に接触する前に前記埋込配線の前記露出端と前記バンプ電極とが直接的または間接的に接触するので、前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方の変形量が大きくなる。したがって、この例は、前記埋込配線及び前記バンプ電極のレイアウトの関係から、前記接着剤膜の変形量を大きくできない場合（例えば、接着剤膜の変形量を大きくすると接着剤膜が対向する二つのバンプ電極間の間隙に入り込んでしまうような場合や、接着剤膜の材料として変形しにくい材料を使っているような場合）に好適に使用できる。   In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, the back surface of the semiconductor circuit layer and the other semiconductor circuit layer are mechanically connected in the mechanical connection step between the exposed end of the embedded wiring and the bump electrode. Before the adhesive film comes into contact with the opposing surface (that is, the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or the surface of another adhesive film) when the distance from the front surface is narrowed Further, the protruding height of the embedded wiring, the height of the bump electrode, and the adhesive so that the exposed end of the embedded wiring and the bump electrode are in direct contact with each other or through the other conductive member. The thickness of the film is set. In this case, since the exposed end of the embedded wiring and the bump electrode come into direct or indirect contact before the adhesive film contacts the opposite surface, the exposed end of the embedded wiring and The deformation amount of at least one of the bump electrodes is increased. Therefore, in this example, when the deformation amount of the adhesive film cannot be increased due to the layout of the embedded wiring and the bump electrode (for example, when the deformation amount of the adhesive film is increased, the adhesive film faces the opposite direction). In the case of entering the gap between the two bump electrodes or the case where a material that is difficult to deform is used as the material of the adhesive film).

本発明の集積回路装置の製造方法のさらに他の好ましい例では、前記埋込配線の前記露出端と前記バンプ電極との機械的接続工程において前記半導体回路層の裏面と前記他の半導体回路層の表面との間隔を狭めた時に、前記埋込配線の前記露出端と前記バンプ電極とが直接、または前記他の導電性部材を介して接触するのとほぼ同時に、前記接着剤膜がその対向する面（すなわち、前記半導体回路層の裏面、前記他の半導体回路層の表面または他の接着剤膜の面）に接触するように、前記埋込配線の突出高さと前記バンプ電極の高さと前記接着剤膜の厚さとが設定される。この場合、前記埋込配線の前記露出端と前記バンプ電極とが直接的または間接的に接触するのと前記接着剤膜がその対向する面に接触するのとがほぼ同時に起こるので、この例は、前記埋込配線及び前記バンプ電極のレイアウトの関係から、前記接着剤膜の変形量を大きくできないと共に、前記埋込配線の前記露出端及び前記バンプ電極の少なくとも一方の変形量も大きくできない場合（例えば、バンプ電極と接着剤膜の双方に変形しにくい材料を使っているような場合）に好適に使用できる。   In still another preferred example of the method of manufacturing an integrated circuit device according to the present invention, the back surface of the semiconductor circuit layer and the other semiconductor circuit layer are mechanically connected in the mechanical connection step between the exposed end of the embedded wiring and the bump electrode. When the distance from the surface is narrowed, the adhesive film faces the exposed end of the embedded wiring and the bump electrode directly or almost simultaneously with the other conductive member. The protruding height of the embedded wiring, the height of the bump electrode, and the adhesion so as to come into contact with the surface (that is, the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or the surface of another adhesive film) The thickness of the agent film is set. In this case, since the exposed end of the embedded wiring and the bump electrode are in direct or indirect contact with each other and the adhesive film is in contact with the opposing surface, this example is The amount of deformation of the adhesive film cannot be increased due to the layout of the embedded wiring and the bump electrode, and the amount of deformation of at least one of the exposed end of the embedded wiring and the bump electrode cannot be increased ( For example, it can be suitably used for a case where a material that hardly deforms is used for both the bump electrode and the adhesive film.

（５） 上述した本発明の集積回路装置の製造方法は、三次元積層構造を持つ任意の集積回路装置に適用可能であり、そのサイズは問わない。三次元積層集積回路装置がウェハーサイズ（この場合、三次元積層構造を構成する半導体回路層の各々がウェハーサイズとなる）であってもよいし、チップサイズ（この場合、前記半導体回路層の各々がチップサイズとなる）であってもよいし、ウェハーサイズとチップサイズの中間のサイズ（この場合、三次元積層構造を構成する半導体回路層の各々がウェハーサイズとチップサイズの中間のサイズとなる）であってもよいし、ウェハーサイズより大きいサイズ（この場合、三次元積層構造を構成する半導体回路層の各々がウェハーサイズより大きいサイズとなる）であってもよい。ここに「ウェハーサイズ」とは、半導体ウェハーとほぼ同じサイズ（例えば直径８インチ）を意味する。本発明において半導体回路層の積層数は任意であるから、三次元積層集積回路装置の高さも任意である。   (5) The method for manufacturing an integrated circuit device of the present invention described above can be applied to any integrated circuit device having a three-dimensional stacked structure, and the size thereof is not limited. The three-dimensional stacked integrated circuit device may be a wafer size (in this case, each of the semiconductor circuit layers constituting the three-dimensional stacked structure is a wafer size) or a chip size (in this case, each of the semiconductor circuit layers). May be an intermediate size between the wafer size and the chip size (in this case, each of the semiconductor circuit layers constituting the three-dimensional stacked structure is an intermediate size between the wafer size and the chip size). Or a size larger than the wafer size (in this case, each of the semiconductor circuit layers constituting the three-dimensional stacked structure is larger than the wafer size). Here, “wafer size” means substantially the same size as a semiconductor wafer (for example, 8 inches in diameter). In the present invention, since the number of stacked semiconductor circuit layers is arbitrary, the height of the three-dimensional stacked integrated circuit device is also arbitrary.

前記半導体回路層の各々は、一つの半導体ウェハーまたは二次元に配置された複数の半導体ウェハーから形成されていてもよいし、一つの半導体チップ（あるいは半導体部材）または二次元に配置された複数の半導体チップ（あるいは半導体部材）から形成されていてもよい。   Each of the semiconductor circuit layers may be formed of one semiconductor wafer or a plurality of semiconductor wafers arranged two-dimensionally, or one semiconductor chip (or a semiconductor member) or a plurality of two-dimensionally arranged semiconductor wafers. You may form from the semiconductor chip (or semiconductor member).

本発明の集積回路装置の製造方法では、（ｉ）積層された半導体回路層間の隙間に電気的絶縁性の接着剤を確実に配置することができると共に、前記隙間よりはみ出た余分の接着剤を除去するという後処理を省略することもできる、（ｉｉ）積層された半導体回路層間の積層方向の機械的接続及び電気的接続を、埋込配線を使用して容易にかつ高い信頼性をもって実現することができる、という効果が得られる。   In the method of manufacturing an integrated circuit device according to the present invention, (i) an electrically insulating adhesive can be reliably disposed in a gap between stacked semiconductor circuit layers, and an excess adhesive protruding from the gap is removed. The post-processing of removing can be omitted. (Ii) The mechanical connection and the electrical connection in the stacking direction between the stacked semiconductor circuit layers are easily and highly reliable using the embedded wiring. The effect that it can be obtained.

以下、本発明の好適な実施の形態について、添付図面を参照して詳細に説明する。   DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.

（第１実施形態）
図１（ａ）〜図８（ｍ）は、本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図である。また、図９（ａ）、（ｂ）は、図５の工程の詳細を示す部分拡大断面図、図１０（ｃ）、（ｄ）は、図６と図７の工程の詳細をそれぞれ示す部分拡大断面図である。この第１実施形態は、半導体ウェハーを積み重ねて三次元積層構造を持つ集積回路装置を製造する例である。 (First embodiment)
FIG. 1A to FIG. 8M are partial cross-sectional views showing, for each step, a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to the first embodiment of the present invention. FIGS. 9A and 9B are partial enlarged sectional views showing details of the process of FIG. 5, and FIGS. 10C and 10D are parts showing details of the processes of FIGS. It is an expanded sectional view. The first embodiment is an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

まず最初に、図１（ａ）に示すように、半導体基板として単結晶シリコン（Ｓｉ）よりなるウェハー（Ｓｉウェハー）１１を用意する。次に、そのウェハー（半導体基板）１１の表面（第１主面）に二酸化シリコン（ＳｉＯ2）膜１２（厚さ１０ｎｍ程度）を形成し、当該表面の全体をＳｉＯ2膜１２で覆う。続いて、ＳｉＯ2膜１２の上に、窒化シリコン（Ｓｉ3Ｎ4）膜１２ａ（厚さ５０ｎｍ程度）を形成し、ＳｉＯ2膜１２の表面全体をＳｉ3Ｎ4膜１２ａで覆う。さらに、Ｓｉ3Ｎ4膜１２ａの上に、所望のトレンチ１３が得られるようにパターン化されたフォトレジスト膜１７を形成する。 First, as shown in FIG. 1A, a wafer (Si wafer) 11 made of single crystal silicon (Si) is prepared as a semiconductor substrate. Next, a silicon dioxide (SiO 2 ) film 12 (thickness of about 10 nm) is formed on the surface (first main surface) of the wafer (semiconductor substrate) 11, and the entire surface is covered with the SiO 2 film 12. Subsequently, on the SiO 2 film 12, a silicon nitride (Si 3 N 4) film 12a (a thickness of about 50 nm), it covers the entire surface of the SiO 2 film 12 with the Si 3 N 4 film 12a. Further, a photoresist film 17 patterned so as to obtain a desired trench 13 is formed on the Si 3 N 4 film 12a.

その後、フォトレジスト膜１７をマスクとして、その下のＳｉ3Ｎ4膜１２ａを選択的に除去し、トレンチ１３を形成すべき箇所に開口を形成する。続いて、こうして開口が形成されたＳｉ3Ｎ4膜１２ａをマスクとして、その下のＳｉＯ2膜１２とＳｉ基板（ウェハー）１１を順に選択的に除去する。ここでは、公知の異方性エッチング法（ドライエッチング法）を用いる。こうして、基板（ウェハー）１１の内部の所定位置にその表面側から、所望深さのトレンチ１３を複数個形成する。トレンチ１３は、Ｓｉ基板（ウェハー）１１の積層方向の電気的接続を行うための埋込配線（ここでは導電体プラグ）を形成すべき箇所にそれぞれ配置される。この時の状態は図１（ａ）に示す通りである。 Thereafter, using the photoresist film 17 as a mask, the underlying Si 3 N 4 film 12a is selectively removed, and an opening is formed at a location where the trench 13 is to be formed. Subsequently, using the Si 3 N 4 film 12a thus formed with the opening as a mask, the underlying SiO 2 film 12 and the Si substrate (wafer) 11 are selectively removed in order. Here, a known anisotropic etching method (dry etching method) is used. In this way, a plurality of trenches 13 having a desired depth are formed from a surface side at a predetermined position inside the substrate (wafer) 11. The trenches 13 are respectively arranged at positions where embedded wiring (here, conductor plugs) for electrical connection in the stacking direction of the Si substrate (wafer) 11 is to be formed. The state at this time is as shown in FIG.

エッチング終了後、マスクとして使用されたフォトレジスト膜１７を除去する。なお、マスクとして使用されたフォトレジスト膜１７は、Ｓｉ3Ｎ4膜１２ａのエッチングの終了後、ＳｉＯ2膜１２をエッチングする前に除去してもよい。 After the etching is completed, the photoresist film 17 used as a mask is removed. The photoresist film 17 used as a mask may be removed after the etching of the Si 3 N 4 film 12a and before the etching of the SiO 2 film 12.

その後、Ｓｉ基板（ウェハー）１１の表面にＳｉ3Ｎ4膜１２ａを残したままで、熱酸化法により、これらトレンチ１３の露出面（内壁面）にＳｉＯ2膜１４（厚さ５００ｎｍ程度）を選択的に形成する。ＳｉＯ2膜１４は、トレンチ１３の内壁面全体を覆うと共に、基板１１の表面を覆うＳｉＯ2膜１２とつながって一体になる。この時の状態は図１（ｂ）に示す通りである。熱酸化終了後、公知の方法でＳｉ3Ｎ4膜１２ａを除去する。 Thereafter, with the Si 3 N 4 film 12a left on the surface of the Si substrate (wafer) 11, the SiO 2 film 14 (thickness of about 500 nm) is selected on the exposed surface (inner wall surface) of these trenches 13 by thermal oxidation. Form. The SiO 2 film 14 covers the entire inner wall surface of the trench 13 and is connected to and integrated with the SiO 2 film 12 covering the surface of the substrate 11. The state at this time is as shown in FIG. After the thermal oxidation, the Si 3 N 4 film 12a is removed by a known method.

次に、露出面がＳｉＯ2膜１４で覆われた各トレンチ１３の内部に、公知の方法で、基板１１の表面側から適当な導電性材料を選択的に埋め込み、導電性プラグ１５を形成する。例えば、ＣＶＤ（Chemical Vapor Deposition）法によりＳｉ基板（ウェハー）１１の全面にわたって導電性材料の膜を堆積させた後、エッチバック法またはＣＭＰ（Chemical Mechanical Polishing）（化学機械研磨）法によりその導電性材料膜のＳｉＯ2膜１２上にある部分を選択的に除去すると共に、トレンチ１３の内部にある部分を残すことにより、各トレンチ１３の内部に導電性プラグ１５が得られる。ここで使用する導電性材料としては、例えばポリシリコン等の半導体や、タングステン（Ｗ）、銅（Ｃｕ）、アルミニウム（Ａｌ）等の金属があるが、これらに限定されるわけではない。 Next, an appropriate conductive material is selectively embedded from the surface side of the substrate 11 into each trench 13 whose exposed surface is covered with the SiO 2 film 14 by a known method to form the conductive plug 15. . For example, after a conductive material film is deposited over the entire surface of the Si substrate (wafer) 11 by a CVD (Chemical Vapor Deposition) method, the conductivity is obtained by an etch back method or a CMP (Chemical Mechanical Polishing) method. By selectively removing the portion of the material film on the SiO 2 film 12 and leaving the portion inside the trench 13, the conductive plug 15 is obtained inside each trench 13. Examples of the conductive material used here include semiconductors such as polysilicon and metals such as tungsten (W), copper (Cu), and aluminum (Al), but are not limited thereto.

そして、基板１１の表面のトレンチ１３が形成されていない箇所に、換言すれば、基板１１の表面のトレンチ１３と重ならない位置に、公知の方法で、必要個数のＭＯＳトランジスタを形成し、必要に応じてＭＯＳトランジスタ以外の素子（図示省略））も形成して、所望の回路とする。各ＭＯＳトランジスタは、基板１１の内部に間隔をあけて形成された一対のソース・ドレイン領域１６と、それらソース・ドレイン領域１６の間に形成されたゲート絶縁膜１２ｂと、ゲート絶縁膜１２ｂの上に形成されたゲート電極１８とから構成される。ゲート絶縁膜１２ｂは、ＳｉＯ2膜１２とは別工程で形成されたＳｉＯ2膜から形成されている。すなわち、ゲート絶縁膜１２ｂを形成すべき箇所でＳｉＯ2膜１２を選択的に除去し、その後に改めて同じ箇所にＳｉＯ2膜を形成することにより、形成されている。この時の状態は図１（ｃ）に示すようになる。 Then, a necessary number of MOS transistors are formed by a known method at a position where the trench 13 on the surface of the substrate 11 is not formed, in other words, at a position not overlapping with the trench 13 on the surface of the substrate 11. Accordingly, elements other than MOS transistors (not shown) are also formed to obtain a desired circuit. Each MOS transistor includes a pair of source / drain regions 16 formed in the substrate 11 at intervals, a gate insulating film 12b formed between the source / drain regions 16, and a gate insulating film 12b. And the gate electrode 18 formed on the substrate. The gate insulating film 12 b is formed from a SiO 2 film formed in a separate process from the SiO 2 film 12. That is, it is formed by selectively removing the SiO 2 film 12 at a position where the gate insulating film 12b is to be formed, and then forming a SiO 2 film again at the same position. The state at this time is as shown in FIG.

次に、図２（ｄ）に示すように、絶縁膜１２上にＳｉ基板（ウェハー）１１の全面にわたって層間絶縁膜１９を形成し、この層間絶縁膜１９によってＭＯＳトランジスタとそれらより露出した面の全体を覆う。層間絶縁膜１９としては、公知の有機あるいは無機の絶縁膜が任意に使用される。そして、層間絶縁膜１９を選択的にエッチングして、所望のソース・ドレイン領域１６及び各トレンチ１３の内部の導電性プラグ１５まで達する貫通孔をそれぞれ形成する。次に、公知の方法により、絶縁膜１９のソース・ドレイン領域１６に対応する貫通孔の内部に導電性材料２１を充填する。その後、絶縁膜１９の上に導電性金属膜（図示せず）を形成してから当該金属膜を選択的にエッチングし、金属配線膜２０を得る。この金属配線膜２０は、層間絶縁膜１９の対応する貫通孔を通して各導電性プラグ１５に接触しており、それによって金属配線膜２０と導電性プラグ１５とが電気的に接続されている。この金属配線膜２０はまた、層間絶縁膜１９の対応する貫通孔の内部に充填された導電性材料２１を介してソース・ドレイン領域１６に電気的に接続されている。   Next, as shown in FIG. 2D, an interlayer insulating film 19 is formed on the entire surface of the Si substrate (wafer) 11 on the insulating film 12, and the interlayer insulating film 19 forms the MOS transistor and the surface exposed from them. Cover the whole. As the interlayer insulating film 19, a known organic or inorganic insulating film is arbitrarily used. Then, the interlayer insulating film 19 is selectively etched to form through holes reaching the desired source / drain regions 16 and the conductive plugs 15 in the respective trenches 13. Next, the conductive material 21 is filled into the through holes corresponding to the source / drain regions 16 of the insulating film 19 by a known method. Thereafter, a conductive metal film (not shown) is formed on the insulating film 19 and then the metal film is selectively etched to obtain the metal wiring film 20. The metal wiring film 20 is in contact with each conductive plug 15 through a corresponding through-hole in the interlayer insulating film 19, whereby the metal wiring film 20 and the conductive plug 15 are electrically connected. The metal wiring film 20 is also electrically connected to the source / drain region 16 via a conductive material 21 filled in the corresponding through hole of the interlayer insulating film 19.

続いて、金属配線膜２０の上に、公知の方法によって多層配線構造３０を形成する。この多層配線構造３０は、絶縁材料３１と、絶縁材料３１の内部に埋め込まれた三つの配線層３２、３３、３４と、主としてそれら配線層３２、３３、３４の層間接続に用いられる導電体３５、３６とを有する。多層配線構造３０の構成・使用材料や形成方法は、公知であるから、それらの詳細な説明は省略する。なお、本発明において、配線構造はこのような多層配線構造３０に限定されるわけではなく、一つの配線層のみを有する単層配線構造であってもよいことは言うまでもない。   Subsequently, a multilayer wiring structure 30 is formed on the metal wiring film 20 by a known method. The multilayer wiring structure 30 includes an insulating material 31, three wiring layers 32, 33, and 34 embedded in the insulating material 31, and a conductor 35 that is mainly used for interlayer connection between the wiring layers 32, 33, and 34. , 36. Since the configuration / materials used and the formation method of the multilayer wiring structure 30 are known, a detailed description thereof will be omitted. In the present invention, it is needless to say that the wiring structure is not limited to such a multilayer wiring structure 30 and may be a single-layer wiring structure having only one wiring layer.

そして、多層配線構造３０（すなわち絶縁材料３１）の表面（平坦化されている）に、公知の方法によって複数のマイクロバンプ電極（小型のバンプ電極）３７を形成する。この時の状態は図２（ｄ）に示す通りである。これらマイクロバンプ電極３７は、それぞれ、多層配線構造３０内の配線層３２、３３または３４と導電体３５または３６とを介して、トレンチ１３の内部の対応する導電性プラグ１５に対して電気的に接続される。こうして、多層配線構造３０の表面にあるマイクロバンプ電極３７と、多層配線構造３０の下方にある導電性プラグ１５とが、電気的に相互接続され、これを通じてＳｉ基板１１の縦方向（積層方向）の電気的相互接続が可能となる。他方、Ｓｉ基板１１に形成されたＭＯＳトランジスタ（すなわち回路）は、必要に応じて、多層配線構造３０や導電性プラグ１５に金属配線膜２０を介して電気的に接続されているので、マイクロバンプ電極３７や導電性プラグ１５を介してＭＯＳトランジスタ（回路）に対する電気信号の入力・出力も可能となる。   Then, a plurality of micro bump electrodes (small bump electrodes) 37 are formed on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) by a known method. The state at this time is as shown in FIG. These micro bump electrodes 37 are electrically connected to the corresponding conductive plugs 15 in the trench 13 via the wiring layers 32, 33 or 34 and the conductors 35 or 36 in the multilayer wiring structure 30, respectively. Connected. In this way, the micro bump electrodes 37 on the surface of the multilayer wiring structure 30 and the conductive plugs 15 below the multilayer wiring structure 30 are electrically interconnected, and through this, the vertical direction (stacking direction) of the Si substrate 11 Can be electrically interconnected. On the other hand, the MOS transistor (that is, the circuit) formed on the Si substrate 11 is electrically connected to the multilayer wiring structure 30 and the conductive plug 15 via the metal wiring film 20 as necessary. It is also possible to input and output electric signals to the MOS transistor (circuit) via the electrode 37 and the conductive plug 15.

マイクロバンプ電極３７は、任意の公知の方法で形成する。別個に形成された導電性材料片を多層配線構造３０の表面に固着させて形成してもよいし、多層配線構造３０の表面に導電性材料をメッキ法等によって直接堆積させて形成してもよい。また、多層配線構造３０の導電体３６等を利用してマイクロバンプ電極３７を形成してもよい。   The micro bump electrode 37 is formed by any known method. A piece of conductive material formed separately may be fixed to the surface of the multilayer wiring structure 30 or may be formed by directly depositing a conductive material on the surface of the multilayer wiring structure 30 by a plating method or the like. Good. Further, the micro bump electrode 37 may be formed using the conductor 36 of the multilayer wiring structure 30 or the like.

ＭＯＳトランジスタ（回路）を有するＳｉ基板（Ｓｉウェハー）１１と、基板１１上に形成された多層配線構造３０とは、第１半導体回路層１を構成する。   The Si substrate (Si wafer) 11 having the MOS transistor (circuit) and the multilayer wiring structure 30 formed on the substrate 11 constitute the first semiconductor circuit layer 1.

続いて、多層配線構造３０の表面に形成されたマイクロバンプ電極３７を利用して、第１半導体回路層１を適当な支持基板４０に固着させる。換言すれば、マイクロバンプ電極３７を利用して、第１半導体回路層１と支持基板４０との機械的接続を行う。支持基板４０としては、例えばガラス、単結晶Ｓｉ製のウェハー等が好適に使用できるが、ここではＳｉウェハー（半導体回路を内蔵したＬＳＩウェハー）を用いている。マイクロバンプ電極３７により、第１半導体回路層１は、Ｓｉウェハーよりなる支持基板４０内に形成された半導体回路（図示省略）に対して機械的・電気的に接続される。Ｓｉウェハーとしては、半導体回路を内蔵していない単なるウェハーでもよい。   Subsequently, the first semiconductor circuit layer 1 is fixed to an appropriate support substrate 40 using the micro bump electrodes 37 formed on the surface of the multilayer wiring structure 30. In other words, the first semiconductor circuit layer 1 and the support substrate 40 are mechanically connected using the micro bump electrode 37. As the support substrate 40, for example, a glass, a single crystal Si wafer or the like can be suitably used, but here, a Si wafer (LSI wafer incorporating a semiconductor circuit) is used. The first semiconductor circuit layer 1 is mechanically and electrically connected to the semiconductor circuit (not shown) formed in the support substrate 40 made of Si wafer by the microbump electrode 37. The Si wafer may be a simple wafer that does not contain a semiconductor circuit.

この状態では、多層配線構造３０と支持基板４０との間にマイクロバンプ電極３７の厚さに相当する隙間があいている。そこで、その隙間に電気的絶縁性の接着剤３９を充填して硬化させる。接着剤３９としては、ポリイミド樹脂やエポキシ樹脂等が好適に使用できる。こうして、接着剤３９とマイクロバンプ電極３７により、第１半導体回路層１は支持基板４０に対して電気的・機械的に接続される。   In this state, there is a gap corresponding to the thickness of the microbump electrode 37 between the multilayer wiring structure 30 and the support substrate 40. Therefore, the gap 39 is filled with an electrically insulating adhesive 39 and cured. As the adhesive 39, polyimide resin, epoxy resin, or the like can be suitably used. Thus, the first semiconductor circuit layer 1 is electrically and mechanically connected to the support substrate 40 by the adhesive 39 and the microbump electrode 37.

なお、支持基板４０がガラスにより形成される場合や、半導体回路を内蔵していない半導体ウェハーにより形成される場合は、マイクロバンプ電極３７は、第１半導体回路層１と支持基板４０との間の機械的接続のためだけに使用されることになる。しかし、この場合は、マイクロバンプ電極３７を省略して、接着剤で第１半導体回路層１を支持基板４０に直接接着してもよく、その方がより効率的である。さらに、接着剤３９は、多層配線構造３０の表面または支持基板４０の対向面に、後述するパターン化された接着剤膜４４ａと同様に、パターン化した膜として形成しておき、その後、マイクロバンプ電極３７を用いて多層配線構造３０と支持基板４０を電気的・機械的に相互接続するようにしてもよい。   When the support substrate 40 is formed of glass or formed of a semiconductor wafer that does not incorporate a semiconductor circuit, the microbump electrode 37 is located between the first semiconductor circuit layer 1 and the support substrate 40. It will be used only for mechanical connection. However, in this case, the micro bump electrode 37 may be omitted, and the first semiconductor circuit layer 1 may be directly bonded to the support substrate 40 with an adhesive, which is more efficient. Further, the adhesive 39 is formed as a patterned film on the surface of the multilayer wiring structure 30 or the opposite surface of the support substrate 40 in the same manner as a patterned adhesive film 44a described later. The multilayer wiring structure 30 and the support substrate 40 may be electrically and mechanically interconnected using the electrode 37.

その後、支持基板４０を用いて第１半導体回路層１を保持しながら、機械研磨法とＣＭＰ法により、Ｓｉ基板１１の裏面（第１半導体回路層１の第２主面）側を内部の各トレンチ１３の下端からの距離が例えば１μｍ程度になるまで研磨し、基板１１全体の厚さを小さくする。こうして研磨されて薄くなった第１半導体回路層１を、以後は１ａで示す。この時の状態は図２（ｅ）に示す通りである。   Thereafter, while holding the first semiconductor circuit layer 1 using the support substrate 40, the back surface (second main surface of the first semiconductor circuit layer 1) side of the Si substrate 11 is placed inside each of the inside by mechanical polishing and CMP. Polishing is performed until the distance from the lower end of the trench 13 is about 1 μm, for example, to reduce the thickness of the entire substrate 11. The first semiconductor circuit layer 1 thus polished and thinned is denoted by 1a hereinafter. The state at this time is as shown in FIG.

次に、薄くなった第１半導体回路層１ａ（すなわちＳｉ基板１１）の裏面側を、ウェット・エッチングまたはプラズマ・エッチング等の等方性エッチングにより選択的に除去し、図３（ｆ）に示すように、トレンチ１３の内壁面を覆うＳｉＯ2膜１４を第１半導体回路層１ａの裏面側に露出させる。この時のエッチング量は、エッチング終了時に導電性プラグ１５の下端が基板１１の裏面から所定距離だけ突出するように調整する。 Next, the back surface side of the thinned first semiconductor circuit layer 1a (that is, the Si substrate 11) is selectively removed by isotropic etching such as wet etching or plasma etching, as shown in FIG. Thus, the SiO 2 film 14 covering the inner wall surface of the trench 13 is exposed on the back surface side of the first semiconductor circuit layer 1a. The etching amount at this time is adjusted so that the lower end of the conductive plug 15 protrudes from the back surface of the substrate 11 by a predetermined distance at the end of etching.

続いて、図３（ｇ）に示すように、基板１１の裏面と露出したＳｉＯ2膜１４の上に、ＳｉＯ2膜４１をＣＶＤ法等の公知の方法で形成する。ＳｉＯ2膜４１の厚さは、例えば０．２μｍ程度とする。こうして形成したＳｉＯ2膜４１をＣＭＰ法で研磨することにより、このＳｉＯ2膜４１と共にＳｉＯ2膜１４並びに導電性プラグ１５の裏面側の端部を選択的に除去し、図４（ｈ）に示すように、トレンチ１３の内部の導電性プラグ１５の下端を露出させる。残存したＳｉＯ2膜４１は、半導体基板１１の裏面の導電性プラグ１５以外の部分を覆っており、基板１１の裏面全体は平坦になっている、換言すれば、第１半導体回路層１ａの裏面全体が平坦になっている。 Subsequently, as shown in FIG. 3G, a SiO 2 film 41 is formed on the back surface of the substrate 11 and the exposed SiO 2 film 14 by a known method such as a CVD method. The thickness of the SiO 2 film 41 is, for example, about 0.2 μm. The SiO 2 film 41 by polishing by CMP thus formed, together with the SiO 2 film 41 an end portion of the rear surface side of the SiO 2 film 14 and conductive plug 15 is selectively removed, in FIG. 4 (h) As shown, the lower end of the conductive plug 15 inside the trench 13 is exposed. The remaining SiO 2 film 41 covers a portion other than the conductive plug 15 on the back surface of the semiconductor substrate 11, and the entire back surface of the substrate 11 is flat, in other words, the back surface of the first semiconductor circuit layer 1a. The whole is flat.

その後、公知の方法により、図４（ｉ）に示すように、露出した各導電性プラグ１５の下端にそれぞれマイクロバンプ電極４２を形成する。これらの電極４２は、例えば、図４（ｈ）に示す状態にある基板１１（第１半導体回路層１ａ）の裏面全体に導電膜（図示せず）を形成した後、その導電膜をリソグラフィー及びエッチングによって選択的に除去して形成することもできるし、リフトオフ法やメッキ法を使用して形成することもできる。リフトオフ法を使用する場合は、まず図４（ｈ）に示す状態にある基板１ａの裏面全体に、マイクロバンプ電極４２を形成すべき箇所に透孔を有するレジスト膜（図示せず）を形成し、次にそのレジスト膜の上に導電層（図示せず）を形成してからそのレジスト膜を引き剥がす。すると、レジスト膜の透孔を介して半導体回路層１ａの裏面に接触している前記導電膜の部分のみが選択的に残存し、電極４２となる。各電極４２は、図４（ｉ）に示すように、対応する導電性プラグ１５の下端に固着する。メッキ法の場合も、リフトオフ法の場合と同様にして形成できる。   Thereafter, as shown in FIG. 4I, a micro bump electrode 42 is formed on each exposed lower end of each conductive plug 15 by a known method. These electrodes 42 are formed, for example, by forming a conductive film (not shown) on the entire back surface of the substrate 11 (first semiconductor circuit layer 1a) in the state shown in FIG. It can be formed by selective removal by etching, or can be formed using a lift-off method or a plating method. When using the lift-off method, first, a resist film (not shown) having through holes is formed on the entire back surface of the substrate 1a in the state shown in FIG. Then, after forming a conductive layer (not shown) on the resist film, the resist film is peeled off. Then, only the portion of the conductive film that is in contact with the back surface of the semiconductor circuit layer 1a through the through hole of the resist film selectively remains and becomes the electrode 42. Each electrode 42 is fixed to the lower end of the corresponding conductive plug 15 as shown in FIG. The plating method can be formed in the same manner as the lift-off method.

基板１１の裏面を基準としたマイクロバンプ電極４２の高さは、図９（ａ）に示すように、Ｈｃである。電極４２の高さＨｃは、例えば１μｍとされる。   The height of the micro bump electrode 42 with respect to the back surface of the substrate 11 is Hc as shown in FIG. The height Hc of the electrode 42 is, for example, 1 μm.

次に、第１半導体回路層１ａの裏面に、以下のようにして、第２半導体回路層２を固着させる。ここでは、説明を簡単にするため、第２半導体回路層２は、第１半導体回路層１とほぼ同一の構成を有しており、また第１半導体回路層１と同一の方法で製造されると仮定し、対応する要素には第１半導体回路層１の場合と同一符号を付してその説明を省略する。なお、必要に応じて、第２半導体回路層２を第１半導体回路層１とは異なる構成としてもよいことは言うまでもない。   Next, the second semiconductor circuit layer 2 is fixed to the back surface of the first semiconductor circuit layer 1a as follows. Here, for simplicity of explanation, the second semiconductor circuit layer 2 has substantially the same configuration as the first semiconductor circuit layer 1 and is manufactured by the same method as the first semiconductor circuit layer 1. It is assumed that the corresponding elements are denoted by the same reference numerals as those of the first semiconductor circuit layer 1 and description thereof is omitted. Needless to say, the second semiconductor circuit layer 2 may be configured differently from the first semiconductor circuit layer 1 as necessary.

第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の平坦化された表面（第２半導体回路層２の第１主面）には、図５（ｊ）及び図９（ａ）に示すように、複数のマイクロバンプ電極４３ａが形成される。これらの電極４３ａは、第１半導体回路層１ａのマイクロバンプ電極４２と同一の方法で形成される。ここでは、第１半導体回路層１ａ（Ｓｉウェハー１１）の裏面に設けられた電極４２の各々について、４個の電極４３ａが対応している。換言すれば、１個の電極４２に対して４個の電極４３ａ（各々が矩形の各頂点に位置している）が接合せしめられるようになっている。詳細は図３２を参照して後述する。   On the planarized surface (the first main surface of the second semiconductor circuit layer 2) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2, FIG. 5 (j) and FIG. 9 (a). As shown in FIG. 4, a plurality of micro bump electrodes 43a are formed. These electrodes 43a are formed by the same method as the micro bump electrodes 42 of the first semiconductor circuit layer 1a. Here, four electrodes 43a correspond to each of the electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (Si wafer 11). In other words, four electrodes 43a (each positioned at each vertex of a rectangle) are joined to one electrode 42. Details will be described later with reference to FIG.

図９（ａ）に示すように、多層配線構造３０の表面を基準とした電極４３ａの高さは、Ｈｂであり、例えば、２μｍに設定される。   As shown in FIG. 9A, the height of the electrode 43a with respect to the surface of the multilayer wiring structure 30 is Hb, and is set to 2 μm, for example.

また、電極４２と４３ａを互いに加圧接触させた時に、電極４３ａのみが選択的に潰れる（塑性変形）ようにするため、電極４３ａは電極４２よりも硬度が十分低い導電性材料から形成されている。例えば、電極４２をタングステン（Ｗ）により形成した場合、電極４３ａはインジウム（Ｉｎ）と金（Ａｕ）の積層体（Ｉｎ／Ａｕ）により形成するのが好ましい。また、電極４２を銅（Ｃｕ）により形成した場合は、電極４３ａは錫（Ｓｎ）と銀（Ａｇ）の積層体（Ｓｎ／Ａｇ）により形成するのが好ましい。   Further, when the electrodes 42 and 43a are brought into pressure contact with each other, only the electrode 43a is selectively crushed (plastic deformation), so that the electrode 43a is made of a conductive material whose hardness is sufficiently lower than that of the electrode 42. Yes. For example, when the electrode 42 is formed of tungsten (W), the electrode 43a is preferably formed of a laminate (In / Au) of indium (In) and gold (Au). Moreover, when the electrode 42 is formed of copper (Cu), the electrode 43a is preferably formed of a laminate (Sn / Ag) of tin (Sn) and silver (Ag).

次に、第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の表面に、図５（ｊ）及び図９（ａ）に示すように、パターン化された電気的絶縁性の接着剤膜４４ａが形成される。この接着剤膜４４ａは、ポリイミド樹脂やＳＯＧ（Spin On Glass）材料等の電気絶縁性の接着剤を室温でパターン化することにより形成されたものであって、所定形状にパターン化（硬化）せしめられた後も粘性（接着性）を有しており、また、所定温度に加熱することによりその表面（露出面）を軟化または流動化させることが可能である（換言すれば、加熱軟化性または加熱流動性を有している）。   Next, as shown in FIGS. 5 (j) and 9 (a), a patterned electrically insulating adhesive is adhered to the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2. An agent film 44a is formed. The adhesive film 44a is formed by patterning an electrically insulating adhesive such as polyimide resin or SOG (Spin On Glass) material at room temperature, and is patterned (cured) into a predetermined shape. The surface (exposed surface) can be softened or fluidized by heating to a predetermined temperature (in other words, heat softening property or It has heat fluidity).

接着剤膜４４ａは、バンプ状（島状）に形成された多数の部分（以下、この島状部分を「接着剤要素」ともいう）４４ａａから構成されており、それらの部分（接着剤要素）４４ａａは多層配線構造３０の表面に規則的に分布せしめられている。接着剤膜４４ａは、電極４３ａのいずれとも重ならない形状を持ち、電極４３ａが形成された箇所とその近傍を除いて配置されている。したがって、接着剤膜４４ａ（すなわち、すべての接着剤要素４４ａａ）は、第１半導体回路層１ａの電極４２（導電性プラグ１５）とも重ならない。   The adhesive film 44a includes a plurality of portions (hereinafter referred to as “adhesive elements”) 44aa formed in a bump shape (island shape), and these portions (adhesive elements). 44aa is regularly distributed on the surface of the multilayer wiring structure 30. The adhesive film 44a has a shape that does not overlap any of the electrodes 43a, and is disposed except for the portion where the electrode 43a is formed and the vicinity thereof. Therefore, the adhesive film 44a (that is, all the adhesive elements 44aa) does not overlap with the electrode 42 (conductive plug 15) of the first semiconductor circuit layer 1a.

図９（ａ）に示すように、多層配線構造３０の表面を基準とした接着剤要素４４ａａの高さＨａは、例えば、４μｍである。   As shown in FIG. 9A, the height Ha of the adhesive element 44aa on the basis of the surface of the multilayer wiring structure 30 is, for example, 4 μm.

接着剤膜４４ａの全体積（より正確にいえば硬化後の全体積）は、電極４２と４３ａを用いて第２半導体回路層２と第１半導体回路層１ａとを機械的・電気的に接続した際に、それら二つの回路層１ａと２の間に生じる隙間全体が接着剤膜４４ａによって充填され、且つその隙間から余分の接着剤膜４４ａがはみ出ないような値に設定される。これは、回路層１ａと２の接続後に、当該隙間からはみ出た余分な接着剤膜４４ａを除去する作業を避けることができるようにするためである。   The total volume of the adhesive film 44a (more precisely, the total volume after curing) is a mechanical and electrical connection between the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a using the electrodes 42 and 43a. In this case, the entire gap formed between the two circuit layers 1a and 2 is filled with the adhesive film 44a, and the value is set so that the excess adhesive film 44a does not protrude from the gap. This is to avoid the operation of removing the excess adhesive film 44a protruding from the gap after the circuit layers 1a and 2 are connected.

接着剤膜４４ａは、電極４２と４３ａがある箇所とその近傍には存在しないため、また、島状の接着剤要素４４ａａの間に隙間があいているため、図９（ａ）に示すように、各接着剤要素４４ａａの高さＨａ（これは接着剤膜４４ａの厚さに等しい）は、電極４３ａの高さＨｂよりも大きく設定されており（Ｈａ＞Ｈｂ）、且つ、各接着剤要素４４ａａの高さＨａが、電極４２の高さＨｃと電極４３ａの高さＨｂの和よりも大きく設定されている（Ｈａ＞（Ｈｂ＋Ｈｃ））。これは、第２半導体回路層２と第１半導体回路層１ａとを接続した際に、加圧によって各接着剤要素４４ａａが押し潰されて電極４２と電極４３ａの周囲にまで広がり、回路層１ａと２の間に残存する隙間全体に充填されるようにするためである。   Since the adhesive film 44a does not exist in the vicinity of the electrode 42 and 43a and there is a gap between the island-shaped adhesive elements 44aa, as shown in FIG. The height Ha of each adhesive element 44aa (which is equal to the thickness of the adhesive film 44a) is set larger than the height Hb of the electrode 43a (Ha> Hb), and each adhesive element The height Ha of 44aa is set to be larger than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a (Ha> (Hb + Hc)). This is because, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, each adhesive element 44aa is crushed by pressurization and spreads around the electrodes 42 and 43a, so that the circuit layer 1a This is to fill the entire gap remaining between 2 and 2.

後述するが、第２半導体回路層２と第１半導体回路層１ａとを接続した際に、各電極４３ａも押し潰されて塑性変形しその周囲に広げられる。その結果、各電極４２に対応する４個の電極４３ａは相互に接続されて一体化される。   As will be described later, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, each electrode 43a is also crushed, plastically deformed, and spread around it. As a result, the four electrodes 43a corresponding to each electrode 42 are connected and integrated.

接着剤膜４４ａが多数の接着剤要素４４ａａに分割されているのは、第２半導体回路層２と第１半導体回路層１ａとを接続する際に、回路層２と１ａの間に存在する空気を外部に逃がしやすくするため（つまり脱ガスの容易化のため）である。すなわち、回路層２と１ａがほとんど接続された状態でも、両層２、１ａの間に残存する気体（空気）が隣接する接着剤要素４４ａａの間の隙間を通って外部に押し出されるようにするためである。   The adhesive film 44a is divided into a large number of adhesive elements 44aa because the air existing between the circuit layers 2 and 1a when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected to each other. This is to make it easier to escape to the outside (that is, to facilitate degassing). That is, even when the circuit layers 2 and 1a are almost connected, the gas (air) remaining between the layers 2 and 1a is pushed out through the gap between the adjacent adhesive elements 44aa. Because.

接着剤膜４４ａは、例えば、次のような方法で形成される。第２半導体回路層２の表面全体に、電気的絶縁性の接着剤膜を塗布法等により形成して硬化させた後、その上にパターン化されたレジスト膜を公知の方法で形成してから、公知のリソグラフィー法で当該接着剤膜を選択的に除去する。こうして厚さＨａのパターン化された接着剤膜４４ａが得られる。他の方法としては、感光性の接着剤を用いて、公知のリソグラフィー法で当該接着剤膜を選択的に除去する、という方法がある。   The adhesive film 44a is formed by the following method, for example. After an electrically insulating adhesive film is formed and cured on the entire surface of the second semiconductor circuit layer 2 by a coating method or the like, a patterned resist film is formed thereon by a known method. Then, the adhesive film is selectively removed by a known lithography method. Thus, a patterned adhesive film 44a having a thickness Ha is obtained. As another method, there is a method of selectively removing the adhesive film by a known lithography method using a photosensitive adhesive.

ここでは、マイクロバンプ電極４３ａを形成してから接着剤膜４４ａを形成しているが、接着剤膜４４ａを形成してからマイクロバンプ電極４３ａを形成してもよい。   Here, the adhesive film 44a is formed after the microbump electrode 43a is formed, but the microbump electrode 43a may be formed after the adhesive film 44a is formed.

続いて、図５（ｊ）及び図９（ａ）に示すように、支持基板４０を介して固定された第１半導体回路層１ａの裏面に、下方から第２半導体回路層２の表面を対向させる。（逆に、第２半導体回路層２を固定しておき、上方から支持基板４０に固定された第１半導体回路層１ａを対向させてもよい。）その後、回路層２と１ａの間に押圧力を加えて回路層２と１ａを相互に近接させると、各接着剤要素４４ａａの高さ（すなわち、接着剤膜４４ａの厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きく（Ｈａ＞Ｈｂ）、且つ、各接着剤要素４４ａａの高さＨａは、電極４２の高さＨｃと電極４３ａの高さＨｂの和よりも大きい（Ｈａ＞（Ｈｂ＋Ｈｃ））ので、最初に、図９（ｂ）に示すように、第２半導体回路層２の接着剤膜４４ａ（接着剤要素４４ａａ）の先端（頂部）が第１半導体回路層１ａの裏面に接触せしめられる。   Subsequently, as shown in FIGS. 5J and 9A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1a fixed via the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1a fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1a. When pressure is applied to bring the circuit layers 2 and 1a close to each other, the height of each adhesive element 44aa (that is, the thickness of the adhesive film 44a) Ha is larger than the height Hb of the electrode 43a (Ha> Hb), and the height Ha of each adhesive element 44aa is larger than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a (Ha> (Hb + Hc)). ), The tip (top) of the adhesive film 44a (adhesive element 44aa) of the second semiconductor circuit layer 2 is brought into contact with the back surface of the first semiconductor circuit layer 1a.

その後、回路層２と１ａの間に押圧力を加えて両者間の距離を狭めることにより、図６（ｋ）及び図１０（ｃ）に示すように、第２半導体回路層２の各電極４３ａを対応する第１半導体回路層１ａの電極４２に接触させる。この時の第１半導体回路層１ａの裏面と第２半導体回路層２の表面との距離、すなわち層間ギャップをＧ１とすると、層間ギャップＧ１は電極４２の厚さと電極４３ａの厚さの和に等しい、すなわちＧ１＝Ｈｃ＋Ｈｂである。この時、接着剤膜４４ａは押し潰されて変形し、回路層１と２の間の隙間のほぼ全体に押し広げられるが、接着剤膜４４ａは島状の接着剤要素４４ａａに分割されているので、接着剤膜４４ａは当該隙間中にほぼ均一に広がる。また、変形せしめられた接着剤膜４４ａと第１半導体回路層１ａの裏面との間（と隣接する接着剤要素４４ａａの間）には、空隙４５が形成されやすいことから、当該隙間中に残存する空気が空隙４５を通って外部に確実に排出されることができ、最終的に硬化せしめられた接着剤膜４４ａ中に気泡が生じる恐れをなくすことができる。   After that, by applying a pressing force between the circuit layers 2 and 1a to reduce the distance between the two, as shown in FIGS. 6 (k) and 10 (c), each electrode 43a of the second semiconductor circuit layer 2 is obtained. Is brought into contact with the electrode 42 of the corresponding first semiconductor circuit layer 1a. When the distance between the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2 at this time, that is, the interlayer gap is G1, the interlayer gap G1 is equal to the sum of the thickness of the electrode 42 and the thickness of the electrode 43a. That is, G1 = Hc + Hb. At this time, the adhesive film 44a is crushed and deformed, and is spread over almost the entire gap between the circuit layers 1 and 2, but the adhesive film 44a is divided into island-shaped adhesive elements 44aa. Therefore, the adhesive film 44a spreads almost uniformly in the gap. Further, since a gap 45 is easily formed between the deformed adhesive film 44a and the back surface of the first semiconductor circuit layer 1a (and between the adjacent adhesive elements 44aa), it remains in the gap. The air to be discharged can be surely discharged to the outside through the gap 45, and the risk of bubbles being generated in the finally cured adhesive film 44a can be eliminated.

上述した第１半導体回路層１ａと第２半導体回路層２とを対向させてから電極４２と４３ａを相互接触させる工程は、室温で行う。第１半導体回路層１ａと第２半導体回路層２との距離Ｇ１の値は、例えば２μｍ〜１０μｍの範囲で適宜決定されるが、典型的には４μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、２μｍ以下とすることも可能である。この場合、距離Ｇ１の値は、例えば０．１μｍ〜２μｍの範囲で適宜決定される。   The step of bringing the electrodes 42 and 43a into contact with each other after the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature. The value of the distance G1 between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, but is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example.

その後、互いに接触せしめられた電極４３ａと電極４２を、以下のようにして相互に接続させる。   Thereafter, the electrodes 43a and 42 brought into contact with each other are connected to each other as follows.

すなわち、図６（ｋ）及び図１０（ｃ）の状態にある第２半導体回路層２と第１半導体回路層１ａを室温から所定温度まで加熱する。その温度は、加圧変形状態にある接着剤膜４４ａの表面（露出面）がわずかに軟化するか、その表面がわずかに流動状態になる温度に設定する。その温度は、接着剤膜４４ａに使用する接着剤の種類によって異なるが、電極４２と電極４３ａとが「圧接」する温度を考慮しながら、例えば１００〜４００℃の範囲内で任意に設定される。このとき、設定する加熱温度によっては、電極４２及び電極４３ａの少なくとも一方が部分的に溶融状態となり、その表面が湾曲することがある。   That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a in the states of FIGS. 6K and 10C are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surface (exposed surface) of the adhesive film 44a in a pressure-deformed state is slightly softened or the surface is slightly fluidized. The temperature varies depending on the type of adhesive used for the adhesive film 44a, but is arbitrarily set within a range of 100 to 400 ° C., for example, in consideration of the temperature at which the electrode 42 and the electrode 43a are “press-contacted”. . At this time, depending on the heating temperature to be set, at least one of the electrode 42 and the electrode 43a may be partially melted and the surface thereof may be curved.

続いて、押圧力を印加することにより、第１半導体回路層１ａに対して下方から第２半導体回路層２をさらに近づけ、あるいは第２半導体回路層２に対して上方から第１半導体回路層１ａを下降させることにより、図８（ｍ）及び図１０（ｄ）に示すように、回路層１ａと２の間の隙間を狭める。換言すれば、回路層１ａと２の層間ギャップをＧ１からそれより小さいＧ２（Ｇ２＜Ｇ１）とする。この時、第２半導体回路層２の電極４３ａと第１半導体回路層１ａの電極４２の間には、圧縮力が作用する。その結果、電極４２よりも機械的強度が低い電極４３ａのみが選択的に押し潰されて、電極４２と電極４３とが「圧接」によって相互に接合せしめられると共に、接着剤要素４４ａａがさらに押し広げられて前記隙間内で完全に連結・一体化される。このとき、１個の電極４２に対応する４個の電極４３ａが潰されて一体的になり、その結果、電極４２と電極４３ａとが一対一対応になる。こうして、相互に圧接された電極４３ａと電極４２の箇所を除いて、回路層２と１ａの間の隙間全体が接着剤膜４４ａによって充填され、余分の接着剤膜４４ａが当該隙間からはみ出ることもない。この時の状態は図８（ｍ）及び図１０（ｄ）に示すようになる。   Subsequently, by applying a pressing force, the second semiconductor circuit layer 2 is made closer to the first semiconductor circuit layer 1a from below, or the first semiconductor circuit layer 1a is viewed from above with respect to the second semiconductor circuit layer 2. Is lowered, the gap between the circuit layers 1a and 2 is narrowed as shown in FIG. 8 (m) and FIG. 10 (d). In other words, the interlayer gap between the circuit layers 1a and 2 is set to G2 (G2 <G1) smaller than G1. At this time, a compressive force acts between the electrode 43a of the second semiconductor circuit layer 2 and the electrode 42 of the first semiconductor circuit layer 1a. As a result, only the electrode 43a having a mechanical strength lower than that of the electrode 42 is selectively crushed so that the electrode 42 and the electrode 43 are joined to each other by “pressure contact”, and the adhesive element 44aa is further expanded. And completely connected and integrated within the gap. At this time, the four electrodes 43a corresponding to one electrode 42 are crushed and integrated, and as a result, the electrodes 42 and the electrodes 43a have a one-to-one correspondence. In this way, the entire gap between the circuit layers 2 and 1a is filled with the adhesive film 44a except for the electrode 43a and the electrode 42 which are in pressure contact with each other, and the extra adhesive film 44a may protrude from the gap. Absent. The state at this time is as shown in FIG. 8 (m) and FIG. 10 (d).

加熱時に電極４２及び電極４３ａの少なくとも一方が部分的に溶融状態となった場合は、電極４２と電極４３ａの接合は、溶融した電極４２、４３ａの「再凝固」により行われるか、「圧接」と「再凝固」が混合した形で行われる。   When at least one of the electrode 42 and the electrode 43a is partially melted during heating, the electrode 42 and the electrode 43a are joined by “re-solidification” of the melted electrodes 42 and 43a or “pressure welding”. And “re-solidification” are performed in a mixed form.

この加熱圧接工程では、層間ギャップがＧ１からＧ２に減少せしめられる際に、回路層１ａと２の間の隙間に存在する空気（大気）が確実に除去されること、そして、回路層１ａと回路層２が相互に接着されることが重要である。この第１実施形態では、接着剤膜４４ａが多数の接着剤要素４４ａａに分割されているので、当該隙間に存在する空気は、第１半導体回路層１ａの裏面と接着剤膜４４ａ（これは加熱によって表面が軟化または流動状態となっている）との間の空隙４５と、隣接する接着剤要素４４ａａの間に残存する微小空間とを通って、外部に確実に排出されることができる。また、接着剤膜４４ａの表面が軟化または流動化しているので、層間ギャップがＧ２になった時に回路層１ａと２が確実に相互接着されることができる。   In this heating and pressure welding process, when the interlayer gap is reduced from G1 to G2, air (atmosphere) existing in the gap between the circuit layers 1a and 2 is surely removed, and the circuit layer 1a and the circuit It is important that the layers 2 are glued together. In the first embodiment, since the adhesive film 44a is divided into a large number of adhesive elements 44aa, the air present in the gaps is separated from the back surface of the first semiconductor circuit layer 1a and the adhesive film 44a (this is heated). The surface is softened or fluidized) and the minute space remaining between the adjacent adhesive elements 44aa can be reliably discharged to the outside. Further, since the surface of the adhesive film 44a is softened or fluidized, the circuit layers 1a and 2 can be reliably bonded to each other when the interlayer gap becomes G2.

層間ギャップＧ２の値は、例えば１μｍ〜９μｍの範囲で適宜決定されるが、典型的には３μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、１μｍ以下とすることも可能である。この場合、距離Ｇ２の値は、例えば０．０５μｍ〜１μｍの範囲で適宜決定される。   The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

第２半導体回路層２は、以上のようにして、電極４２と電極４３ａを用いて第１半導体回路層１ａの裏面側に固着（つまり機械的に接続）せしめられると共に、両回路層１ａ及び２の間の電気的接続も同時に行われる。また、それと同時に、両回路層１ａ及び２は、互いに接続された電極４３ａと電極４２の箇所を除いて回路層１ａと２の間の隙間全体に充填された接着剤膜４４ａによって、相互に接着される。   As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1a using the electrode 42 and the electrode 43a, and both the circuit layers 1a and 2 are connected. The electrical connection between is also made simultaneously. At the same time, the circuit layers 1a and 2 are bonded to each other by the adhesive film 44a filled in the entire gap between the circuit layers 1a and 2 except for the portions of the electrodes 43a and 42 connected to each other. Is done.

以上のようにして電極４２と電極４３ａの機械的・電気的接続と接着剤膜４４ａの接着が終わると、相互に接合された回路層１と２ａは室温まで自然冷却される。そこで、加熱、紫外線照射、薬剤添加等によって接着剤膜４４ａを最終的に硬化させる。処理が容易であることから、加熱により硬化させるのが好ましい。加熱温度は、接着剤膜４４ａとして使用した接着剤の性質に応じて、例えば１２０〜５００℃の範囲内で適宜設定される。こうして、二つの半導体回路層１ａと２の間の機械的接続と電気的接続が完了する。   When the mechanical and electrical connection between the electrode 42 and the electrode 43a and the bonding of the adhesive film 44a are completed as described above, the circuit layers 1 and 2a bonded to each other are naturally cooled to room temperature. Therefore, the adhesive film 44a is finally cured by heating, ultraviolet irradiation, chemical addition, or the like. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive film 44a. Thus, the mechanical connection and the electrical connection between the two semiconductor circuit layers 1a and 2 are completed.

その後の工程は、第１半導体回路層１ａの場合と同じである。すなわち、第１半導体回路層１ａに接合せしめられた第２半導体回路層２について、第１半導体回路層１ａの場合と同様に、ＣＭＰ法により、Ｓｉ基板（ウェハー）１１の裏面側を各トレンチ１３の下端からの距離が例えば１μｍ程度となるまで研磨する。こうして厚さが薄くされた第２半導体回路層２を、以後は２ａと表示する。   The subsequent steps are the same as those for the first semiconductor circuit layer 1a. That is, with respect to the second semiconductor circuit layer 2 bonded to the first semiconductor circuit layer 1a, the rear surface side of the Si substrate (wafer) 11 is formed on each trench 13 by CMP, as in the case of the first semiconductor circuit layer 1a. Polishing is performed until the distance from the lower end of the metal becomes, for example, about 1 μm. The second semiconductor circuit layer 2 thus reduced in thickness is hereinafter referred to as 2a.

次に、第１半導体回路層１ａの場合と同じ方法によって、第２半導体回路層２ａの基板（ウェハー）１１の下部を選択的に除去してトレンチ１３の内部のＳｉＯ2膜１４を露出させ、基板１１の裏面と露出せしめられたＳｉＯ2膜１４の上にＳｉＯ2膜４１を形成し、ＳｉＯ2膜４１とＳｉＯ2膜１４を選択的に除去して導電性プラグ１５の下端を露出させ、さらに、露出した導電性プラグ１５の下端にそれぞれマイクロバンプ電極４２を形成する。こうして、半導体回路層２ａの構成は図８（ｍ）に示すようになる。図８（ｍ）の第２半導体回路層２ａは、図４（ｉ）に示された第１半導体回路層１ａと実質的に同じ状態にある。 Next, the lower part of the substrate (wafer) 11 of the second semiconductor circuit layer 2a is selectively removed by the same method as in the case of the first semiconductor circuit layer 1a to expose the SiO 2 film 14 inside the trench 13, An SiO 2 film 41 is formed on the back surface of the substrate 11 and the exposed SiO 2 film 14, and the SiO 2 film 41 and the SiO 2 film 14 are selectively removed to expose the lower end of the conductive plug 15. Further, the microbump electrodes 42 are respectively formed on the lower ends of the exposed conductive plugs 15. Thus, the configuration of the semiconductor circuit layer 2a is as shown in FIG. The second semiconductor circuit layer 2a in FIG. 8 (m) is substantially in the same state as the first semiconductor circuit layer 1a shown in FIG. 4 (i).

当該集積回路装置が第１及び第２の半導体回路層１ａと２ａより構成される二層構造の三次元積層集積回路装置である場合は、第２半導体回路層２ａの裏面に形成されたマイクロバンプ電極４２が、外部回路接続用のマイクロバンプ電極として使用される。当該集積回路装置が第３あるいはそれ以上の半導体回路層を有する場合は、必要に応じて、上記と同様の方法により、第２の半導体回路層２ａに重ねて第３、第４、第５・・・・の半導体回路層（図示せず）が積層・固着され、三次元積層構造を持つ集積回路装置が製造される。   In the case where the integrated circuit device is a three-dimensional stacked integrated circuit device having a two-layer structure composed of the first and second semiconductor circuit layers 1a and 2a, micro bumps formed on the back surface of the second semiconductor circuit layer 2a The electrode 42 is used as a micro bump electrode for external circuit connection. When the integrated circuit device has third or more semiconductor circuit layers, the third, fourth, fifth, fifth,... Are stacked on the second semiconductor circuit layer 2a by the same method as described above, if necessary. The semiconductor circuit layers (not shown) are stacked and fixed to produce an integrated circuit device having a three-dimensional stacked structure.

この段階では、図７（ｌ）及び図１０（ｄ）より明らかなように、第１半導体回路層１ａの内部の回路は、一方では、第１半導体回路層１ａ内の多層配線構造３０中の配線と電極３７を介して、上位にある支持基板４０内の回路に対して電気的に接続され、他方では、第１半導体回路層１ａ内の導電性プラグ１５と電極４２及び４３と第２半導体回路層２ａ内の多層配線構造３０中の配線を介して、第２半導体回路層２ａ内の回路に対して電気的に接続される。同様にして、第２半導体回路層２ａ内の回路は、第２半導体回路層２ａ内の導電性プラグ１５と電極４２（及び４３）を介して、下位にある外部回路または第３半導体回路層内の回路に対して電気的に接続される。   At this stage, as is apparent from FIGS. 7 (l) and 10 (d), the circuit inside the first semiconductor circuit layer 1a, on the other hand, is in the multilayer wiring structure 30 in the first semiconductor circuit layer 1a. It is electrically connected to the circuit in the upper support substrate 40 via the wiring and the electrode 37, and on the other hand, the conductive plug 15, the electrodes 42 and 43 in the first semiconductor circuit layer 1a, and the second semiconductor. It is electrically connected to the circuit in the second semiconductor circuit layer 2a via the wiring in the multilayer wiring structure 30 in the circuit layer 2a. Similarly, the circuit in the second semiconductor circuit layer 2a is connected to the lower external circuit or third semiconductor circuit layer via the conductive plug 15 and the electrode 42 (and 43) in the second semiconductor circuit layer 2a. The circuit is electrically connected.

ここで、図３２を参照しながら、第１半導体回路層１ａの電極４２と第２半導体回路層２の電極４３ａとの間の位置関係、並びに、第２半導体回路層２の表面に形成されたパターン化された接着剤膜４４ａの構成を詳細に説明する。図３２（ａ）は電極４２と４３ａの間の位置関係を示す拡大平面図であり、図３２（ｂ）は接着剤膜４４ａの構成を示す拡大平面図である。   Here, with reference to FIG. 32, the positional relationship between the electrode 42 of the first semiconductor circuit layer 1a and the electrode 43a of the second semiconductor circuit layer 2 and the surface of the second semiconductor circuit layer 2 were formed. The configuration of the patterned adhesive film 44a will be described in detail. FIG. 32A is an enlarged plan view showing the positional relationship between the electrodes 42 and 43a, and FIG. 32B is an enlarged plan view showing the configuration of the adhesive film 44a.

図３２（ａ）に示すように、第１半導体回路層１ａの裏面（導電性プラグ１５の端面）に設けられたマイクロバンプ電極４２の各々は、二辺の長さをＬｃ１、Ｌｃ２（Ｘ方向の長さをＬｃ１、Ｙ方向の長さをＬｃ２）とする矩形の平面形状を持つ。電極４２の二辺はＸ方向に平行であり、他の二辺はＹ方向に平行である。電極４２の平面形状と大きさは、対応する導電性プラグ１５の端面の平面形状と大きさにそれぞれ等しい。   As shown in FIG. 32A, each of the micro bump electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (the end surface of the conductive plug 15) has a length of two sides Lc1 and Lc2 (X direction). Has a rectangular planar shape with Lc1 as the length and Lc2) as the length in the Y direction. The two sides of the electrode 42 are parallel to the X direction, and the other two sides are parallel to the Y direction. The planar shape and size of the electrode 42 are equal to the planar shape and size of the end face of the corresponding conductive plug 15, respectively.

第２半導体回路層２の表面に形成されたマイクロバンプ電極４３ａは、４個が一組になって、一つのマイクロバンプ電極４２に対応している。４個の電極４３ａの各々は、二辺の長さをＬｂ１、Ｌｂ２（Ｘ方向の長さをＬｂ１、Ｙ方向の長さをＬｂ２）とする矩形の平面形状を持つ。４個の電極４３ａの平面形状と大きさは、互いに同一である。各電極４３ａの二辺はＸ方向に平行であり、他の二辺はＹ方向に平行である。   Four microbump electrodes 43a formed on the surface of the second semiconductor circuit layer 2 form a set and correspond to one microbump electrode. Each of the four electrodes 43a has a rectangular planar shape in which the lengths of two sides are Lb1 and Lb2 (the length in the X direction is Lb1 and the length in the Y direction is Lb2). The four electrodes 43a have the same planar shape and size. Two sides of each electrode 43a are parallel to the X direction, and the other two sides are parallel to the Y direction.

４個の電極４３ａは、対応する一つの電極４２の四つの角にそれぞれ対応して配置されている。Ｘ方向に隣接する２個の電極４３ａは、隙間Ｐ１をあけて並べられている。Ｙ方向に隣接する２個の電極４３ａは、隙間Ｐ２をあけて並べられている。したがって、Ｌ１＝Ｌｂ１＋Ｐ１＋Ｌｂ１、Ｌ２＝Ｌｂ２＋Ｐ２＋Ｌｂ２が成り立つ。   The four electrodes 43a are arranged corresponding to the four corners of the corresponding one electrode 42, respectively. Two electrodes 43a adjacent in the X direction are arranged with a gap P1 therebetween. The two electrodes 43a adjacent in the Y direction are arranged with a gap P2. Therefore, L1 = Lb1 + P1 + Lb1 and L2 = Lb2 + P2 + Lb2 hold.

図３２（ａ）では、図示を簡単にするために、電極４２及び４３ａはいずれも正方形としてある。典型的な数値を例示すると、Ｌ１＝Ｌ２＝５μｍ、Ｌｂ１＝Ｌｂ２＝２μｍ、Ｐ１＝Ｐ２＝１μｍ、Ｌｃ１＝Ｌｃ２＝３μｍである。この場合、四つの電極４３ａは、電極４２の各角に、その中心に対して対称的に配置されている。   In FIG. 32A, for simplicity of illustration, the electrodes 42 and 43a are both square. For example, L1 = L2 = 5 μm, Lb1 = Lb2 = 2 μm, P1 = P2 = 1 μm, and Lc1 = Lc2 = 3 μm. In this case, the four electrodes 43a are arranged symmetrically with respect to the center of each electrode 42 at each corner.

図３２（ｂ）に示すように、接着剤膜４４ａは、電極４３ａとは重ならない形状（パターン）を有していると共に、多数の接着剤要素４４ａａから構成されている。各接着剤要素４４ａａの平面形状は、二辺の長さをＬａ１、Ｌａ２（Ｘ方向の長さをＬａ１、Ｙ方向の長さをＬａ２）とするとする矩形である。各接着剤要素４４ａａの大きさとレイアウトは、それが配置される位置や、その周囲にどの程度の大きさの電極４３ａがいくつあるか、に応じて適宜調整される。これは、接着剤要素４４ａａの表面を軟化または流動化させた状態で層間ギャップをＧ１からＧ２に減少した時に、電極４２と４３ａの箇所を除いて、第１半導体回路層１ａと第２半導体回路層２の間の隙間全体が接着剤膜４４ａによって充填されるようにするためである。このように、接着剤要素４４ａａの大きさとレイアウトは、当該隙間の充填の必要性に応じて任意に設定される。   As shown in FIG. 32 (b), the adhesive film 44a has a shape (pattern) that does not overlap with the electrode 43a, and includes a large number of adhesive elements 44aa. The planar shape of each adhesive element 44aa is a rectangle in which the length of two sides is La1 and La2 (the length in the X direction is La1 and the length in the Y direction is La2). The size and layout of each adhesive element 44aa are appropriately adjusted according to the position where the adhesive element 44aa is disposed and how many electrodes 43a there are around. This is because the first semiconductor circuit layer 1a and the second semiconductor circuit except for the positions of the electrodes 42 and 43a when the interlayer gap is decreased from G1 to G2 while the surface of the adhesive element 44aa is softened or fluidized. This is because the entire gap between the layers 2 is filled with the adhesive film 44a. Thus, the size and layout of the adhesive element 44aa are arbitrarily set according to the necessity of filling the gap.

接着剤要素４４ａａとそれを囲む複数の電極４３ａとの間には、隙間ｄ１、ｄ２、ｄ３、ｄ４が設けられている。隣接する接着剤要素４４ａａの間の隙間は、Ｘ方向がｄ１１、Ｙ方向がｄ１２である。   Gaps d1, d2, d3, and d4 are provided between the adhesive element 44aa and the plurality of electrodes 43a surrounding it. The gap between adjacent adhesive elements 44aa is d11 in the X direction and d12 in the Y direction.

図３２（ｂ）では、図示を簡単にするために、接着剤要素４４ａａの平面形状は正方形としてある。典型的な数値を例示すると、ｄ１＝ｄ２＝ｄ３＝ｄ４＝２μｍ、ｄ１１＝ｄ１２＝１．５μｍである。   In FIG. 32 (b), in order to simplify the illustration, the planar shape of the adhesive element 44aa is a square. To illustrate typical numerical values, d1 = d2 = d3 = d4 = 2 μm and d11 = d12 = 1.5 μm.

接着剤要素４４ａａの平面形状は、ここでは矩形としているが、本発明はこれに限定されるわけではない。矩形以外の任意の形状とすることができる。また、ｄ１、ｄ２、ｄ３、ｄ４、ｄ１１及びｄ１２の値は、加圧および軟化または流動化による接着剤要素４４ａａの広がりの度合いを考慮して決定される。   The planar shape of the adhesive element 44aa is rectangular here, but the present invention is not limited to this. Any shape other than a rectangle can be used. The values of d1, d2, d3, d4, d11, and d12 are determined in consideration of the degree of spread of the adhesive element 44aa due to pressurization and softening or fluidization.

以上説明したように、本発明の第１実施形態に係る集積回路装置の製造方法では、三次元積層構造を構成する第１半導体回路層１ａの内部に、一端が当該半導体回路層１ａの裏面（基板１１の裏面）から露出せしめられた複数の導電性プラグ１５（すなわち埋込配線）を形成すると共に、各プラグ１５の露出した端面にマイクロバンプ電極４２を形成する。他方、三次元積層構造を構成する第２半導体回路層２の表面（多層配線構造３０の表面）の所定位置に、複数のマイクロバンプ電極４３ａを形成する。その後、第２半導体回路層２の表面に、導電性プラグ１５及び電極４２、４３ａとは重ならない形状を持つパターン化された電気的絶縁性の接着剤膜４４ａを形成してから、第１半導体回路層１ａの裏面と第２半導体回路層２の表面とを相互に対向させる。そして、両回路層１ａと２の距離を狭めることにより、接着剤膜４４ａを押し広げながら電極４２と電極４３ａとを相互に接触させ、第１半導体回路層１ａと第２半導体回路層２の間の層間ギャップをＧ１とする。そして、さらに加熱下で押圧力を加えることによって、層間ギャップがＧ２となるまで第１半導体回路層１ａと第２半導体回路層２の間の隙間を狭める。その結果、電極４３ａが変形せしめられて両回路層１ａと２が相互に機械的・電気的に接続される。この時、接着剤膜４４ａは、両回路層１ａと２の間に残存する隙間内で変形せしめられる（押し広げられる）と共に、電極４２と４３ａの機械的接続工程の終了時に当該隙間全体に充填せしめられる。そして、その接着剤膜４４ａによって、両回路層１ａ及び２は相互に接着される。   As described above, in the method of manufacturing an integrated circuit device according to the first embodiment of the present invention, one end is inside the first semiconductor circuit layer 1a constituting the three-dimensional laminated structure, and the back surface of the semiconductor circuit layer 1a ( A plurality of conductive plugs 15 (that is, embedded wirings) exposed from the back surface of the substrate 11 are formed, and micro bump electrodes 42 are formed on the exposed end surfaces of the plugs 15. On the other hand, a plurality of micro bump electrodes 43a are formed at predetermined positions on the surface of the second semiconductor circuit layer 2 constituting the three-dimensional stacked structure (the surface of the multilayer wiring structure 30). Thereafter, a patterned electrically insulating adhesive film 44a having a shape that does not overlap the conductive plug 15 and the electrodes 42 and 43a is formed on the surface of the second semiconductor circuit layer 2, and then the first semiconductor. The back surface of the circuit layer 1a and the surface of the second semiconductor circuit layer 2 are opposed to each other. Then, by narrowing the distance between the two circuit layers 1a and 2, the electrode 42 and the electrode 43a are brought into contact with each other while spreading the adhesive film 44a, so that the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is increased. Let G1 be the interlayer gap. Further, by applying a pressing force under heating, the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is narrowed until the interlayer gap becomes G2. As a result, the electrode 43a is deformed and the circuit layers 1a and 2 are mechanically and electrically connected to each other. At this time, the adhesive film 44a is deformed (spreaded) in the gap remaining between the circuit layers 1a and 2 and filled in the gap at the end of the mechanical connection process of the electrodes 42 and 43a. I'm damned. The circuit layers 1a and 2 are bonded to each other by the adhesive film 44a.

このため、第１半導体回路層１ａと第２半導体回路層２の間の層間ギャップが所定値Ｇ２にされた時に、両層１ａと２の間に残存する空間の総体積にほぼ等しくなるように接着剤膜４４ａの総量を調整することにより、両層１ａと２の間の隙間全体に電気的絶縁性の接着剤を確実に配置することが可能となり、しかも前記隙間よりはみ出た余分の接着剤を除去する必要がなくなる。この点は、第２半導体回路層２ａと第３半導体回路層の間や、他の半導体回路層の間の接続について同様である。   For this reason, when the interlayer gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is set to a predetermined value G2, it becomes substantially equal to the total volume of the space remaining between the layers 1a and 2. By adjusting the total amount of the adhesive film 44a, it becomes possible to securely dispose the electrically insulating adhesive in the entire gap between the two layers 1a and 2, and the extra adhesive protruding from the gap. Need not be removed. This is the same for the connection between the second semiconductor circuit layer 2a and the third semiconductor circuit layer or between other semiconductor circuit layers.

よって、三次元積層構造を構成する積層された任意の半導体回路層間の隙間に電気的絶縁性の接着剤を確実に配置することができると共に、前記隙間よりはみ出た余分の接着剤を除去するという後処理を省略することもできる。その結果、三次元積層構造を構成する積層された任意の半導体回路層間の積層方向の機械的接続及び電気的接続を、導電性プラグ１５（つまり埋込配線）と電極４２、４３ａを使用して容易にかつ高い信頼性をもって実現することができる。   Therefore, it is possible to reliably arrange an electrically insulating adhesive in a gap between any stacked semiconductor circuit layers constituting a three-dimensional laminated structure, and to remove excess adhesive protruding from the gap. Post-processing can be omitted. As a result, the mechanical connection and electrical connection in the stacking direction between the stacked arbitrary semiconductor circuit layers constituting the three-dimensional stacked structure can be performed using the conductive plug 15 (that is, the embedded wiring) and the electrodes 42 and 43a. It can be realized easily and with high reliability.

なお、上述した第１実施形態では、パターン化された接着剤膜４４ａを第２半導体回路層２の表面（多層配線構造３０の表面）に形成しているが、第１半導体回路層２の裏面（ＳｉＯ2膜４１の表面）に形成してもよい。また、接着剤膜４４ａは、島状の接着剤要素４４ａａに分割されていなくてもよく、後述の第３実施形態の接着剤膜４４ｃのように、連続的に形成されていてもよい。この場合でも、表面が軟化または流動化せしめられた接着剤膜４４ａと、第１半導体回路層１ａの裏面との間には、空隙４５が確実に形成されるから、回路層１ａ及び２の間の隙間中に残存する空気は空隙４５を通って外部に確実に排出されることができる。したがって、島状の接着剤要素４４ａａに分割された接着剤膜４４ａと同様の効果が得られる。 In the first embodiment described above, the patterned adhesive film 44a is formed on the surface of the second semiconductor circuit layer 2 (the surface of the multilayer wiring structure 30), but the back surface of the first semiconductor circuit layer 2 is formed. it may be formed on (the surface of the SiO 2 film 41). Further, the adhesive film 44a may not be divided into island-shaped adhesive elements 44aa, and may be formed continuously like an adhesive film 44c of a third embodiment described later. Even in this case, the gap 45 is surely formed between the adhesive film 44a whose surface is softened or fluidized and the back surface of the first semiconductor circuit layer 1a. The air remaining in the gap can be reliably discharged to the outside through the gap 45. Therefore, an effect similar to that of the adhesive film 44a divided into island-shaped adhesive elements 44aa can be obtained.

また、上述した第１実施形態では、支持基板４０の下に第１半導体回路層１ａと第２半導体回路層２ａを順に積層・固着した場合を示しているが、支持基板４０の向きを上下逆にして、支持基板４０の上に第１半導体回路層１ａと第２半導体回路層２ａを順に積層・固着してもよいことは言うまでもない。   In the first embodiment described above, the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2a are sequentially stacked and fixed under the support substrate 40, but the support substrate 40 is turned upside down. Thus, it goes without saying that the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2a may be laminated and fixed in order on the support substrate 40.

さらに、上述した第１実施形態では、図２（ｄ）に示す構造の第１半導体回路層１を形成してから、電極３７を用いて直ちに支持基板４０に接続し、その次に図５（ｊ）に示す構造の第２半導体回路層２を形成してから、電極４２と４３を用いて直ちに第１半導体回路層１に接続しているが、本実施形態の製造方法はこれに限定されない。例えば、次のようにしてもよい。すなわち、まず、図２（ｄ）に示す構造の第１半導体回路層１と図５（ｊ）に示す構造の第２半導体回路層２とを先に製造しておく。その後、第１半導体回路層１を支持基板４０に固着させてから第１半導体回路層１の裏面を加工し、図４（ｉ）に示す構造を持つ第１半導体回路層１ａを形成する。続いて、図５（ｊ）に示す構造の第２半導体回路層２を第１半導体回路層１ａに固着させてから第２半導体回路層２の裏面を加工し、図７（ｌ）に示す構造を持つ第２半導体回路層２ａを形成するのである。   Furthermore, in the first embodiment described above, after the first semiconductor circuit layer 1 having the structure shown in FIG. 2D is formed, the first substrate 37 is immediately connected to the support substrate 40 using the electrode 37, and then, FIG. The second semiconductor circuit layer 2 having the structure shown in j) is formed and then immediately connected to the first semiconductor circuit layer 1 using the electrodes 42 and 43. However, the manufacturing method of the present embodiment is not limited to this. . For example, it may be as follows. That is, first, the first semiconductor circuit layer 1 having the structure shown in FIG. 2D and the second semiconductor circuit layer 2 having the structure shown in FIG. Thereafter, the first semiconductor circuit layer 1 is fixed to the support substrate 40 and then the back surface of the first semiconductor circuit layer 1 is processed to form the first semiconductor circuit layer 1a having the structure shown in FIG. Subsequently, after the second semiconductor circuit layer 2 having the structure shown in FIG. 5J is fixed to the first semiconductor circuit layer 1a, the back surface of the second semiconductor circuit layer 2 is processed, and the structure shown in FIG. The second semiconductor circuit layer 2a having the above is formed.

上述した第１実施形態は、半導体ウェハーを積み重ねて三次元積層構造を持つ集積回路装置を製造する例であるが、これと同様の工程により、半導体ウェハーに代えて半導体チップを積み重ねて三次元積層構造を持つ集積回路装置を製造することも可能である。   The above-described first embodiment is an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers, but in the same process as this, three-dimensional stacking is performed by stacking semiconductor chips instead of the semiconductor wafer. It is also possible to manufacture an integrated circuit device having a structure.

さらに、上述した構成を持つウェハーサイズの三次元積層集積回路装置は、積層された複数のウェハーからなるウェハー積層体を分割せず、ウェハーサイズの三次元積層集積回路装置としてそのまま使用することもできるが、支持基板４０に対して直交する方向（積層方向）にダイシングを行うことによって複数の部分に分割し、ウェハーサイズより小さい三次元積層集積回路装置としても使用できることは言うまでもない。   Further, the wafer-size three-dimensional stacked integrated circuit device having the above-described configuration can be used as it is as a wafer-size three-dimensional stacked integrated circuit device without dividing a wafer stack composed of a plurality of stacked wafers. However, it goes without saying that it can be divided into a plurality of parts by dicing in a direction orthogonal to the support substrate 40 (stacking direction) and used as a three-dimensional stacked integrated circuit device smaller than the wafer size.

（第２実施形態）
図１１（ａ）〜図１３（ｃ）及び図１４（ａ）〜図１５（ｄ）は、本発明の第２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図である。この第２実施形態も、半導体ウェハーを積み重ねて三次元積層構造を持つ集積回路装置を製造する例である。 (Second Embodiment)
11 (a) to 13 (c) and FIGS. 14 (a) to 15 (d) show a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the second embodiment of the present invention for each process. It is a fragmentary sectional view shown. This second embodiment is also an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

第２実施形態の集積回路装置の製造方法は、三次元積層構造を構成する第１半導体回路層１ａの裏面（第２主面）と第２半導体回路層２の表面（第１主面）の双方に電気的絶縁性の接着剤膜４４ｂ１及び４４ｂ２をそれぞれ形成した点を除き、第１実施形態の集積回路装置の製造方法と同一である。接着剤膜４４ｂ１は、導電性プラグ１５及びマイクロバンプ電極４２とは重ならない形状を持ち、多数の島状の接着剤要素４４ｂｂ１から構成される。接着剤膜４４ｂ２は、マイクロバンプ電極４３ａとは重ならない形状を持ち、多数の島状の接着剤要素４４ｂｂ２から構成される。よって、以下では、第１実施形態と同一の工程についてはその概略のみを説明し、相違する工程について詳細に説明する。   The manufacturing method of the integrated circuit device according to the second embodiment includes a back surface (second main surface) of the first semiconductor circuit layer 1a and a front surface (first main surface) of the second semiconductor circuit layer 2 constituting a three-dimensional stacked structure. The method is the same as that of the integrated circuit device according to the first embodiment except that electrically insulating adhesive films 44b1 and 44b2 are formed on both sides. The adhesive film 44b1 has a shape that does not overlap with the conductive plug 15 and the microbump electrode 42, and includes a plurality of island-shaped adhesive elements 44bb1. The adhesive film 44b2 has a shape that does not overlap with the micro-bump electrode 43a, and includes a large number of island-shaped adhesive elements 44bb2. Therefore, below, only the outline is demonstrated about the process same as 1st Embodiment, and a different process is demonstrated in detail.

図１１（ａ）〜図１３（ｃ）は、第１実施形態における図５（ｊ）〜図７（ｌ）にそれぞれ対応する。また、図１４（ａ）〜図１５（ｄ）は、第１実施形態における図９（ａ）〜図１０（ｄ）にそれぞれ対応する。   FIGS. 11A to 13C correspond to FIGS. 5J to 7L in the first embodiment, respectively. FIGS. 14A to 15D correspond to FIGS. 9A to 10D in the first embodiment, respectively.

まず、第１実施形態と同一の工程により、図４（ｈ）に示す構成の第１半導体回路層１ａを形成する。その後、第１実施形態と同一の材料を用い且つ同一の方法で、図４（ｉ）に示すように、露出した各導電性プラグ１５の下端にそれぞれマイクロバンプ電極４２を形成する。   First, the first semiconductor circuit layer 1a having the configuration shown in FIG. 4H is formed by the same process as in the first embodiment. Thereafter, using the same material as in the first embodiment and by the same method, as shown in FIG. 4I, a microbump electrode 42 is formed at the lower end of each exposed conductive plug 15, respectively.

第１半導体回路層１ａの裏面を基準とした電極４２の高さＨｃは、例えば１μｍとされる。   The height Hc of the electrode 42 with respect to the back surface of the first semiconductor circuit layer 1a is, for example, 1 μm.

次に、第１実施形態における接着剤膜４４ａと同様にして、図１１（ａ）及び図１４（ａ）に示すように、第１半導体回路層１ａの裏面（第２主面）すなわちＳｉＯ2膜４１の露出面に、パターン化された電気的絶縁性の接着剤膜４４ｂ１を形成する。この接着剤膜４４ｂ１は、ポリイミド樹脂やＳＯＧ材料等の電気絶縁性の接着剤を室温でパターン化（硬化）することにより形成されたものであって、所定温度に加熱することによりその表面（露出面）を軟化または流動化することが可能である。（換言すれば、加熱軟化性または加熱流動性を有している。）
接着剤膜４４ｂ１は、バンプ状（島状）に形成された多数の接着剤要素４４ｂｂ１から構成されており、それら接着剤要素４４ｂｂ１は、図３２（ｂ）に示すようなレイアウトで、ＳｉＯ2膜４１の露出面に規則的に分布せしめられている。接着剤膜４４ｂ１は、電極４２のいずれとも重ならない形状を持ち、電極４２が形成された箇所とその近傍を除いて配置されている。したがって、接着剤膜４４ｂ１（すなわち、すべての接着剤要素４４ｂｂ１）は導電性プラグ１５とも重ならない。 Next, similarly to the adhesive film 44a in the first embodiment, as shown in FIGS. 11A and 14A, the back surface (second main surface) of the first semiconductor circuit layer 1a, that is, SiO 2 is used. On the exposed surface of the film 41, a patterned electrically insulating adhesive film 44b1 is formed. This adhesive film 44b1 is formed by patterning (curing) an electrically insulating adhesive such as polyimide resin or SOG material at room temperature, and its surface (exposed) is heated to a predetermined temperature. Surface) can be softened or fluidized. (In other words, it has heat softening property or heat fluidity.)
The adhesive film 44b1 is composed of a number of adhesive elements 44bb1 formed in a bump shape (island shape), they adhesives element 44bb1 is a layout as shown in FIG. 32 (b), SiO 2 film 41 are regularly distributed on the exposed surface. The adhesive film 44b1 has a shape that does not overlap any of the electrodes 42, and is disposed except for the portion where the electrode 42 is formed and the vicinity thereof. Therefore, the adhesive film 44b1 (that is, all the adhesive elements 44bb1) does not overlap the conductive plug 15.

図１４（ａ）に示すように、第１半導体回路層１ａの裏面を基準とした接着剤要素４４ｂｂ１の高さは、Ｈｄであり、例えば、３μｍに設定される。   As shown in FIG. 14A, the height of the adhesive element 44bb1 with respect to the back surface of the first semiconductor circuit layer 1a is Hd, and is set to 3 μm, for example.

他方、第１半導体回路層１と同一の方法により製造された第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の表面（平坦化されている）に、図１１（ａ）及び図１４（ａ）に示すように、複数のマイクロバンプ電極４３ａ（高さはＨｂ）が形成される。電極４３ａは、第１半導体回路層１ａの電極４２と同一の方法で形成される。ここでは、第１実施形態と同様に、第１半導体回路層１ａ（Ｓｉウェハー１１）の裏面に設けられた電極４２の各々について、４個の電極４３ａが対応している。換言すれば、１個の電極４２に対して４個の電極４３ａが接合せしめられるようになっている。また、電極４２と４３ａを接触させて加圧した時に、電極４３ａのみが選択的に潰れる（塑性変形する）ようにするため、第１実施形態と同様に、電極４３ａは電極４２よりも機械的強度が低い導電性材料から形成されている。   On the other hand, on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2 manufactured by the same method as the first semiconductor circuit layer 1, FIG. As shown in FIG. 14A, a plurality of micro bump electrodes 43a (height is Hb) are formed. The electrode 43a is formed by the same method as the electrode 42 of the first semiconductor circuit layer 1a. Here, as in the first embodiment, four electrodes 43a correspond to each of the electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (Si wafer 11). In other words, four electrodes 43 a are bonded to one electrode 42. Further, when the electrodes 42 and 43a are brought into contact with each other and pressed, only the electrode 43a is selectively crushed (plastically deformed), so that the electrode 43a is more mechanical than the electrode 42 as in the first embodiment. It is formed from a conductive material having low strength.

第２半導体回路層２の表面を基準とした電極４３ａの高さＨａは、例えば、２μｍに設定される。   The height Ha of the electrode 43a with respect to the surface of the second semiconductor circuit layer 2 is set to 2 μm, for example.

次に、第１実施形態における接着剤膜４４ａと同様にして、第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の表面に、図１１（ａ）及び図１４（ａ）に示すように、パターン化された電気的絶縁性の接着剤膜４４ｂ２が形成される。この接着剤膜４４ｂ２は、接着剤膜４４ｂ１と同じ電気絶縁性の接着剤を用いて形成されており、所定形状にパターン化（硬化）せしめられた後も粘性（接着性）を有しており、また、所定温度への加熱によりその表面を軟化または流動化させることが可能である。   Next, in the same manner as the adhesive film 44a in the first embodiment, on the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2, FIG. 11 (a) and FIG. 14 (a). As shown, a patterned electrically insulating adhesive film 44b2 is formed. This adhesive film 44b2 is formed using the same electrically insulating adhesive as the adhesive film 44b1, and has a viscosity (adhesiveness) after being patterned (cured) into a predetermined shape. In addition, the surface can be softened or fluidized by heating to a predetermined temperature.

接着剤膜４４ｂ２は、バンプ状（島状）に形成された多数の接着剤要素４４ｂｂ２から構成されており、それらの接着剤要素４４ｂｂ２は、図３２（ｂ）に示すようなレイアウトで、多層配線構造３０の表面に規則的に分布せしめられている。接着剤膜４４ｂ２は、電極４３ａと重ならない形状を持ち、電極４３ａが形成された箇所とその近傍を除いて配置されている。したがって、接着剤膜４４ｂ２（すなわち、すべての接着剤要素４４ｂｂ２）は電極４２（導電性プラグ１５）とも重ならない。   The adhesive film 44b2 is composed of a large number of adhesive elements 44bb2 formed in a bump shape (island shape). These adhesive elements 44bb2 have a layout as shown in FIG. It is distributed regularly on the surface of the structure 30. The adhesive film 44b2 has a shape that does not overlap with the electrode 43a, and is disposed except for a portion where the electrode 43a is formed and its vicinity. Therefore, the adhesive film 44b2 (that is, all the adhesive elements 44bb2) does not overlap with the electrode 42 (conductive plug 15).

第２半導体回路層２の表面を基準とした接着剤要素４４ｂｂ２の高さＨａは、例えば、３μｍに設定される。   The height Ha of the adhesive element 44bb2 with respect to the surface of the second semiconductor circuit layer 2 is set to 3 μm, for example.

接着剤膜４４ｂ１と４４ｂ２の全体積（硬化後の全体積）の和は、電極４２と４３ａを用いて第２半導体回路層２と第１半導体回路層１ａとを機械的・電気的に接続した際に、それら二つの回路層１ａと２の間に生じる隙間全体が接着剤膜４４ｂ１及び４４ｂ２によって充填され、且つその隙間から余分の接着剤膜４４ｂ１及び４４ｂ２がはみ出ないような値に設定される。これは、回路層１ａと２の接続後に、当該隙間からはみ出た余分な接着剤膜４４ｂ１及び４４ｂ２を除去する作業を避けることができるようにするためである。   The sum of the total volume of the adhesive films 44b1 and 44b2 (total volume after curing) is obtained by mechanically and electrically connecting the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a using the electrodes 42 and 43a. At this time, the entire gap formed between the two circuit layers 1a and 2 is filled with the adhesive films 44b1 and 44b2, and the value is set so that the extra adhesive films 44b1 and 44b2 do not protrude from the gap. . This is to avoid the operation of removing the excess adhesive films 44b1 and 44b2 protruding from the gap after the circuit layers 1a and 2 are connected.

接着剤膜４４ｂ１及び４４ｂ２は、電極４２と４３ａがある箇所とその近傍には存在しないため、また、島状の接着剤要素４４ｂｂ１の間と島状の接着剤要素４４ｂｂ２の間にはそれぞれ隙間が設けてあるため、図１４（ａ）に示すように、各接着剤要素４４ｂｂ１の高さＨｄ（これは接着剤膜４４ｂ１の厚さに等しい）は、電極４２の高さＨｃよりも大きく設定されており（Ｈｄ＞Ｈｃ）、且つ、各接着剤要素４４ｂｂ２の高さＨａは、電極４３ａの高さＨｂよりも大きく設定されている（Ｈａ＞Ｈｂ）。これは、第２半導体回路層２と第１半導体回路層１ａとを接続した際に、加圧によって各接着剤要素４４ｂｂ１と４４ｂｂ２が押し潰されて電極４２と電極４３ａの周囲や各接着剤要素４４ｂｂ１、４４ｂｂ２間の隙間にまでそれぞれ広がって、回路層１ａと２の間に残存する隙間全体に充填されるようにするためである。   Since the adhesive films 44b1 and 44b2 do not exist in the vicinity of the place where the electrodes 42 and 43a are present, there is a gap between the island-shaped adhesive element 44bb1 and the island-shaped adhesive element 44bb2, respectively. 14A, the height Hd of each adhesive element 44bb1 (which is equal to the thickness of the adhesive film 44b1) is set larger than the height Hc of the electrode 42. (Hd> Hc), and the height Ha of each adhesive element 44bb2 is set larger than the height Hb of the electrode 43a (Ha> Hb). This is because, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, the adhesive elements 44bb1 and 44bb2 are crushed by pressurization, and around the electrode 42 and the electrode 43a and each adhesive element. This is to fill the entire gap remaining between the circuit layers 1a and 2 by spreading to the gap between 44bb1 and 44bb2, respectively.

後述するが、第２半導体回路層２と第１半導体回路層１ａとを接続した際に、各電極４３ａも押し潰されて塑性変形しその周囲に広げられる。その結果、各電極４２に対応する４個の電極４３ａは相互に接続されて一体化される。   As will be described later, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, each electrode 43a is also crushed, plastically deformed, and spread around it. As a result, the four electrodes 43a corresponding to each electrode 42 are connected and integrated.

接着剤膜４４ｂ１と４４ｂ２が、それぞれ多数の接着剤要素４４ｂｂ１、４４ｂｂ２に分割されているのは、第２半導体回路層２と第１半導体回路層１ａとを接続する際に、両回路層２、１ａの間に存在する空気を外部に逃がしやすくするため（つまり脱ガスの容易化のため）である。すなわち、回路層２と１ａがほとんど接続された状態でも、両層２、１ａの間に存在する空気が隣接する接着剤要素４４ｂ１と４４ｂ２の間の隙間を通って外部に押し出されるようにするためである。なお、接着剤要素４４ｂｂ１の各々は、接着剤要素４４ｂｂ２と一対一対応となっている。   The adhesive films 44b1 and 44b2 are divided into a plurality of adhesive elements 44bb1 and 44bb2, respectively, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected to each other. This is to facilitate the escape of air existing between 1a to the outside (that is, to facilitate degassing). That is, even when the circuit layers 2 and 1a are almost connected, the air existing between the layers 2 and 1a is pushed out through the gap between the adjacent adhesive elements 44b1 and 44b2. It is. Each of the adhesive elements 44bb1 has a one-to-one correspondence with the adhesive element 44bb2.

ここでは、マイクロバンプ電極４２を形成してから接着剤膜４４ｂ１を形成し、マイクロバンプ電極４３ａを形成してから接着剤膜４４ｂ２を形成しているが、接着剤膜４４ｂ１を形成してからマイクロバンプ電極４２を形成してもよいし、接着剤膜４４ｂ２を形成してからマイクロバンプ電極４３ａを形成してもよい。   Here, the adhesive film 44b1 is formed after the microbump electrode 42 is formed, and the adhesive film 44b2 is formed after the microbump electrode 43a is formed. However, after the adhesive film 44b1 is formed, the microbump electrode 42a is formed. The bump electrode 42 may be formed, or the microbump electrode 43a may be formed after the adhesive film 44b2 is formed.

続いて、図１１（ａ）及び図１４（ａ）に示すように、支持基板４０を介して固定された第１半導体回路層１ａの裏面に、下方から第２半導体回路層２の表面を対向させる。（逆に、第２半導体回路層２を固定しておき、上方から支持基板４０に固定された第１半導体回路層１ａを対向させてもよい。）その後、回路層２と１ａの間に押圧力を加えて回路層２と１ａを相互に近接させると、各接着剤要素４４ｂｂ１の高さ（接着剤膜４４ａの厚さ）Ｈｄは、電極４２の高さＨｃよりも大きく（Ｈｄ＞Ｈｃ）、且つ、各接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きい（Ｈａ＞Ｈｂ）ので、最初に、図１４（ｂ）に示すように、第２半導体回路層２の接着剤膜４４ｂ２（接着剤要素４４ｂｂ２）の先端（頂部）が第１半導体回路層１ａの接着剤膜４４ｂ１（接着剤要素４４ｂｂ１）の先端（頂部）に接触せしめられる。   Subsequently, as shown in FIGS. 11A and 14A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1a fixed via the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1a fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1a. When pressure is applied to bring the circuit layers 2 and 1a close to each other, the height of each adhesive element 44bb1 (the thickness of the adhesive film 44a) Hd is larger than the height Hc of the electrode 42 (Hd> Hc). Further, since the height of each adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is larger than the height Hb of the electrode 43a (Ha> Hb), first, as shown in FIG. Further, the tip (top) of the adhesive film 44b2 (adhesive element 44bb2) of the second semiconductor circuit layer 2 is brought into contact with the tip (top) of the adhesive film 44b1 (adhesive element 44bb1) of the first semiconductor circuit layer 1a. It is done.

その後、回路層２と１ａの間に押圧力を加えて両者間の距離を狭めることにより、図１２（ｂ）及び図１５（ｃ）に示すように、第２半導体回路層２の各電極４３ａを対応する第１半導体回路層１ａの電極４２に接触させる。この時の第１半導体回路層１ａの裏面と第２半導体回路層２の表面との距離、すなわち層間ギャップをＧ１とすると、層間ギャップＧ１は電極４２の厚さと電極４３ａの厚さの和に等しい、すなわちＧ１＝Ｈｃ＋Ｈｂである。この時、接着剤膜４４ｂ１及び４４ｂ２はいずれも押し潰されて変形し、回路層１と２の間の隙間のほぼ全体に押し広げられるが、接着剤膜４４ｂ１及び４４ｂ２は島状の接着剤要素４４ｂｂ１及び４４ｂｂ２にそれぞれ分割されているので、接着剤膜４４ｂ１及び４４ｂ２ａは当該隙間中にほぼ均一に広がる。また、変形せしめられた接着剤膜４４ｂ１と接着剤膜４４ｂ２との間（と隣接する接着剤要素４４ｂｂ１及び４４ｂｂ２の間）には、空隙４５が形成されやすいことから、当該隙間中に残存する空気が空隙４５を通って外部に確実に排出されることができ、最終的に一体化・硬化せしめられた接着剤膜４４ｂ１ｂ２中に気泡が生じる恐れをなくすことができる。   Thereafter, a pressing force is applied between the circuit layers 2 and 1a to reduce the distance between the two, and as shown in FIGS. 12B and 15C, each electrode 43a of the second semiconductor circuit layer 2 is obtained. Is brought into contact with the electrode 42 of the corresponding first semiconductor circuit layer 1a. When the distance between the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2 at this time, that is, the interlayer gap is G1, the interlayer gap G1 is equal to the sum of the thickness of the electrode 42 and the thickness of the electrode 43a. That is, G1 = Hc + Hb. At this time, the adhesive films 44b1 and 44b2 are both crushed and deformed, and are spread over almost the entire gap between the circuit layers 1 and 2, but the adhesive films 44b1 and 44b2 are island-shaped adhesive elements. Since it is divided into 44bb1 and 44bb2, respectively, the adhesive films 44b1 and 44b2a spread almost uniformly in the gap. Further, since a gap 45 is easily formed between the deformed adhesive film 44b1 and the adhesive film 44b2 (and between the adjacent adhesive elements 44bb1 and 44bb2), the air remaining in the gap Can be reliably discharged to the outside through the gap 45, and the possibility of bubbles being generated in the finally integrated and cured adhesive film 44b1b2 can be eliminated.

上述した第１半導体回路層１ａと第２半導体回路層２とを対向させてから電極４２と４３ａを相互接触させる工程は、第１実施形態と同様に、室温で行う。第１半導体回路層１ａと第２半導体回路層２との距離Ｇ１の値は、例えば２μｍ〜１０μｍの範囲で適宜決定されるが、典型的には４μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、２μｍ以下とすることも可能である。この場合、距離Ｇ１の値は、例えば０．１μｍ〜２μｍの範囲で適宜決定される。この点も第１実施形態と同様である。   The step of bringing the electrodes 42 and 43a into contact with each other after the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature, as in the first embodiment. The value of the distance G1 between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, but is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example. This is also the same as in the first embodiment.

その後、互いに接触せしめられた電極４３ａと電極４２を、以下のようにして相互に接続させる。   Thereafter, the electrodes 43a and 42 brought into contact with each other are connected to each other as follows.

すなわち、図１２（ｂ）及び図１５（ｃ）の状態にある第２半導体回路層２と第１半導体回路層１ａを室温から所定温度まで加熱する。その温度は、加圧変形状態にある接着剤膜４４ｂ１及び４４ｂ２の表面（露出面）がわずかに軟化するか、それらの表面がわずかに流動状態になる温度に設定する。その温度は、接着剤膜４４ｂ１及び４４ｂ２に使用する接着剤の種類によって異なるが、電極４２と電極４３ａとが「圧接」する温度を考慮しながら、例えば１００〜４００℃の範囲内で任意に設定される。このとき、設定する加熱温度によっては、電極４２及び電極４３ａの少なくとも一方が部分的に溶融状態となり、その表面が湾曲することがある。   That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a in the states of FIGS. 12B and 15C are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surfaces (exposed surfaces) of the adhesive films 44b1 and 44b2 in the pressure-deformed state are slightly softened or the surfaces are slightly fluidized. The temperature varies depending on the type of adhesive used for the adhesive films 44b1 and 44b2, but is arbitrarily set within a range of, for example, 100 to 400 ° C. in consideration of the temperature at which the electrode 42 and the electrode 43a are “press-contacted”. Is done. At this time, depending on the heating temperature to be set, at least one of the electrode 42 and the electrode 43a may be partially melted and the surface thereof may be curved.

続いて、押圧力を印加することにより、第１半導体回路層１ａに対して下方から第２半導体回路層２をさらに近づけ、あるいは第２半導体回路層２に対して上方から第１半導体回路層１ａを下降させることにより、図１３（ｃ）及び図１５（ｄ）に示すように、回路層１ａと２の間の隙間を狭めることにより、回路層１ａと２の間の層間ギャップをＧ１からそれより小さいＧ２（Ｇ２＜Ｇ１）とする。この時、第２半導体回路層２の電極４３ａと第１半導体回路層１ａの電極４２の間には、圧縮力が作用する。その結果、電極４２よりも機械的強度が低い電極４３ａのみが選択的に押し潰されて、電極４２と電極４３とが「圧接」によって相互に接合せしめられると共に、接着剤要素４４ｂｂ１及び４４ｂｂ２がさらに押し広げられて相互に連結・一体化される。このとき、１個の電極４２に対応する４個の電極４３ａが潰されて一体的になり、その結果、電極４２と電極４３ａとが一対一対応になる。こうして、相互に圧接された電極４３ａと電極４２の箇所を除いて、回路層２と１ａの間の隙間の全体が接着剤膜４４ａによって充填され、余分の接着剤膜４４ｂ１または４４ｂ２が当該隙間からはみ出ることもない。この時の状態は図１３（ｃ）及び図１５（ｄ）に示すようになる。   Subsequently, by applying a pressing force, the second semiconductor circuit layer 2 is made closer to the first semiconductor circuit layer 1a from below, or the first semiconductor circuit layer 1a is viewed from above with respect to the second semiconductor circuit layer 2. As shown in FIG. 13 (c) and FIG. 15 (d), the gap between the circuit layers 1a and 2 is reduced from G1 by narrowing the gap between the circuit layers 1a and 2 as shown in FIGS. A smaller G2 (G2 <G1) is assumed. At this time, a compressive force acts between the electrode 43a of the second semiconductor circuit layer 2 and the electrode 42 of the first semiconductor circuit layer 1a. As a result, only the electrode 43a having a mechanical strength lower than that of the electrode 42 is selectively crushed so that the electrode 42 and the electrode 43 are joined to each other by “pressure contact”, and the adhesive elements 44bb1 and 44bb2 are further provided. They are spread and connected and integrated with each other. At this time, the four electrodes 43a corresponding to one electrode 42 are crushed and integrated, and as a result, the electrodes 42 and the electrodes 43a have a one-to-one correspondence. In this way, the entire gap between the circuit layers 2 and 1a is filled with the adhesive film 44a except for the electrode 43a and the electrode 42 that are in pressure contact with each other, and the extra adhesive film 44b1 or 44b2 is removed from the gap. It does not protrude. The state at this time is as shown in FIGS. 13 (c) and 15 (d).

加熱時に電極４２及び電極４３ａの少なくとも一方が部分的に溶融状態となった場合は、電極４２と電極４３ａの接合は、溶融した電極４２、４３ａの「再凝固」により行われるか、「圧接」と「再凝固」が混合した形で行われる。この点は第１実施形態と同様である。   When at least one of the electrode 42 and the electrode 43a is partially melted during heating, the electrode 42 and the electrode 43a are joined by “re-solidification” of the melted electrodes 42 and 43a or “pressure welding”. And “re-solidification” are performed in a mixed form. This is the same as in the first embodiment.

この加熱圧接工程では、層間ギャップがＧ１からＧ２に減少せしめられる際に、回路層１ａと２の間の隙間に存在する空気（大気）が確実に除去されること、そして、回路層１ａと回路層２が相互に接着されることが重要である。この第２実施形態では、接着剤膜４４ｂ１及び４４ｂ２がそれぞれ多数の接着剤要素４４ｂｂ１及び４４ｂｂ２に分割されているので、当該隙間に存在する空気は、接着剤膜４４ｂ１及び４４ｂ２（これらはいずれも加熱によって表面が軟化または流動化している）との間の空隙４５と、隣接する接着剤要素４４ｂｂ１と４４ｂｂ２の間に残存する微小空間とを通って、外部に確実に排出されることができる。また、接着剤膜４４ｂｂ１の表面と接着剤膜４４ｂｂ２の表面がいずれも軟化または流動化しているので、層間ギャップがＧ２になった時に、接着剤膜４４ｂｂ１と接着剤膜４４ｂｂ２が接着されやすく、その結果、回路層１ａと２が確実に相互接着されることができる。   In this heating and pressure welding process, when the interlayer gap is reduced from G1 to G2, air (atmosphere) existing in the gap between the circuit layers 1a and 2 is surely removed, and the circuit layer 1a and the circuit It is important that the layers 2 are glued together. In this second embodiment, the adhesive films 44b1 and 44b2 are divided into a large number of adhesive elements 44bb1 and 44bb2, respectively, so that the air present in the gaps becomes the adhesive films 44b1 and 44b2 (both are heated). The surface is softened or fluidized) and the minute space remaining between the adjacent adhesive elements 44bb1 and 44bb2 can be reliably discharged to the outside. In addition, since the surface of the adhesive film 44bb1 and the surface of the adhesive film 44bb2 are both softened or fluidized, when the interlayer gap becomes G2, the adhesive film 44bb1 and the adhesive film 44bb2 are easily bonded. As a result, the circuit layers 1a and 2 can be securely bonded to each other.

層間ギャップＧ２の値は、例えば１μｍ〜９μｍの範囲で適宜決定されるが、典型的には３μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、１μｍ以下とすることも可能である。この場合、距離Ｇ２の値は、例えば０．０５μｍ〜１μｍの範囲で適宜決定される。   The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

第２半導体回路層２は、以上のようにして、電極４２と電極４３ａを用いて第１半導体回路層１ａの裏面側に固着（つまり機械的に接続）せしめられると共に、両回路層１ａ及び２の間の電気的接続も同時に行われる。また、それと同時に、両回路層１ａ及び２は、互いに接続された電極４３ａと電極４２の箇所を除いて回路層１ａと２の間の隙間全体に充填された接着剤膜４４ｂ１及び４４ｂ２によって、相互に接着される。   As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1a using the electrode 42 and the electrode 43a, and both the circuit layers 1a and 2 are connected. The electrical connection between is also made simultaneously. At the same time, both circuit layers 1a and 2 are mutually connected by adhesive films 44b1 and 44b2 filled in the entire gap between the circuit layers 1a and 2 except for the portions of the electrodes 43a and 42 connected to each other. Glued to.

以上のようにして電極４２と電極４３ａの機械的・電気的接続と接着剤膜４４ｂ１及び４４ｂ２の接着が終わると、相互に接合された回路層１と２ａは室温まで自然冷却される。そこで、加熱、紫外線照射、薬剤添加等によって一体化された接着剤膜４４ｂ１及び４４ｂ２を最終的に硬化させる。処理が容易であることから、加熱により硬化させるのが好ましい。加熱温度は、接着剤膜４４ｂ１及び４４ｂ２として使用した接着剤の性質に応じて、例えば１２０〜５００℃℃の範囲内で適宜設定される。こうして、二つの半導体回路層１ａと２の間の機械的接続と電気的接続が完了する。   When the mechanical / electrical connection between the electrode 42 and the electrode 43a and the bonding of the adhesive films 44b1 and 44b2 are finished as described above, the circuit layers 1 and 2a bonded to each other are naturally cooled to room temperature. Therefore, the adhesive films 44b1 and 44b2 integrated by heating, ultraviolet irradiation, chemical addition, etc. are finally cured. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive films 44b1 and 44b2. Thus, the mechanical connection and the electrical connection between the two semiconductor circuit layers 1a and 2 are completed.

その後の工程は、第１実施形態の場合と同じであるから、その説明は省略する。   Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

以上説明したように、本発明の第２実施形態に係る集積回路装置の製造方法は、第１半導体回路層１ａの裏面と第２半導体回路層２の表面の双方に電気的絶縁性の接着剤膜４４ｂ１及び４４ｂ２をそれぞれ形成した点を除いて、上述した第１実施形態に係る集積回路装置の製造方法と同じであるから、第１実施形態において得られるものと同一の効果が得られることは明らかである。ただ、第２実施形態では、二つの接着剤膜４４ｂ１及び４４ｂ２を使用しているので、第１実施形態におけるよりも第２半導体回路層２と第１半導体回路層１ａの接着力が増すという利点がある。   As described above, the method for manufacturing an integrated circuit device according to the second embodiment of the present invention has an electrically insulating adhesive on both the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2. Since the manufacturing method of the integrated circuit device according to the first embodiment is the same as that of the first embodiment except that the films 44b1 and 44b2 are formed, the same effect as that obtained in the first embodiment can be obtained. it is obvious. However, in the second embodiment, since the two adhesive films 44b1 and 44b2 are used, the adhesive force between the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a is increased as compared with the first embodiment. There is.

（第３実施形態）
図１６（ａ）〜図１８（ｃ）及び図１９（ａ）〜図２０（ｄ）は、本発明の第３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図である。この第３実施形態も、半導体ウェハーを積み重ねて三次元積層構造を持つ集積回路装置を製造する例である。 (Third embodiment)
FIGS. 16A to 18C and FIGS. 19A to 20D show a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the third embodiment of the present invention for each process. It is a fragmentary sectional view shown. This third embodiment is also an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

第３実施形態の集積回路装置の製造方法は、三次元積層構造を構成する第１半導体回路層１ａの裏面（第２主面）と第２半導体回路層２の表面（第１主面）の双方に電気的絶縁性の接着剤膜４４ｃ及び４４ｂ２をそれぞれ形成した点を除き、第１実施形態の集積回路装置の製造方法と同一である。接着剤膜４４ｃは、導電性プラグ１５及びマイクロバンプ電極４２とは重ならない形状を持つが、連続的に形成されており、多数の接着剤要素には分割されていない点で第２実施形態とは異なる。接着剤膜４４ｃと各電極４２との間には、接続時に電極４３ａが押し潰されることによって生じる体積増加を吸収するための領域として、空隙が形成されている。接着剤膜４４ｂ２は、第２実施形態と同様に、マイクロバンプ電極４３ａとは重ならない形状を持ち、多数の接着剤要素４４ｂｂ２から構成される。よって、以下では、第１実施形態と同一の工程についてはその概略のみを説明し、相違する工程について詳細に説明する。   The method for manufacturing an integrated circuit device according to the third embodiment includes a back surface (second main surface) of the first semiconductor circuit layer 1a and a front surface (first main surface) of the second semiconductor circuit layer 2 constituting a three-dimensional stacked structure. The manufacturing method of the integrated circuit device of the first embodiment is the same as that of the first embodiment, except that electrically insulating adhesive films 44c and 44b2 are formed on both sides. The adhesive film 44c has a shape that does not overlap with the conductive plug 15 and the microbump electrode 42, but is formed continuously and is not divided into a large number of adhesive elements as in the second embodiment. Is different. A gap is formed between the adhesive film 44c and each electrode 42 as a region for absorbing a volume increase caused by the electrode 43a being crushed during connection. Similar to the second embodiment, the adhesive film 44b2 has a shape that does not overlap with the microbump electrode 43a, and includes a large number of adhesive elements 44bb2. Therefore, below, only the outline is demonstrated about the process same as 1st Embodiment, and a different process is demonstrated in detail.

図１６（ａ）〜図１８（ｃ）は、第１実施形態における図５（ｊ）〜図７（ｌ）にそれぞれ対応する。また、図１９（ａ）〜図２０（ｄ）は、第１実施形態における図９（ａ）〜図１０（ｄ）にそれぞれ対応する。   FIGS. 16A to 18C correspond to FIGS. 5J to 7L in the first embodiment, respectively. FIGS. 19A to 20D correspond to FIGS. 9A to 10D in the first embodiment, respectively.

まず、第１実施形態と同一の工程により、図４（ｈ）に示す構成の第１半導体回路層１ａを形成する。その後、第１実施形態と同一の材料を用い且つ同一の方法で、図４（ｉ）に示すように、露出した各導電性プラグ１５の下端にそれぞれマイクロバンプ電極４２を形成する。   First, the first semiconductor circuit layer 1a having the configuration shown in FIG. 4H is formed by the same process as in the first embodiment. Thereafter, using the same material as in the first embodiment and by the same method, as shown in FIG. 4I, a microbump electrode 42 is formed at the lower end of each exposed conductive plug 15, respectively.

第１半導体回路層１ａの裏面を基準とした電極４２の高さＨｃは、例えば２．５μｍとされる。   The height Hc of the electrode 42 with respect to the back surface of the first semiconductor circuit layer 1a is, for example, 2.5 μm.

次に、第１実施形態における接着剤膜４４ａ及び第２実施形態における接着剤膜４４ｂ１と同様にして、図１６（ａ）及び図１９（ａ）に示すように、第１半導体回路層１ａの裏面（第２主面）すなわちＳｉＯ2膜４１の露出面に、パターン化された電気的絶縁性の接着剤膜４４ｃを形成する。この接着剤膜４４ｃは、ポリイミド樹脂やＳＯＧ材料等の電気絶縁性の接着剤を室温でパターン化（硬化）することにより形成されたものであって、所定温度に加熱することによりその表面（露出面）を軟化または流動化することが可能である。 Next, in the same manner as the adhesive film 44a in the first embodiment and the adhesive film 44b1 in the second embodiment, as shown in FIGS. 16A and 19A, the first semiconductor circuit layer 1a is formed. A patterned electrically insulating adhesive film 44 c is formed on the back surface (second main surface), that is, the exposed surface of the SiO 2 film 41. The adhesive film 44c is formed by patterning (curing) an electrically insulating adhesive such as polyimide resin or SOG material at room temperature, and its surface (exposed) is heated to a predetermined temperature. Surface) can be softened or fluidized.

接着剤膜４４ｃは、電極４２（そして導電性プラグ１５）とは重ならない形状を持つが、接着剤要素に分割されておらず、電極４２のある箇所とその近傍を除いてＳｉＯ2膜４１の露出面の全体を覆っている。したがって、接着剤膜４４ｃは導電性プラグ１５とも重ならない。 The adhesive film 44 c has a shape that does not overlap with the electrode 42 (and the conductive plug 15), but is not divided into adhesive elements, and the SiO 2 film 41 except for a portion where the electrode 42 is present and its vicinity. Covers the entire exposed surface. Therefore, the adhesive film 44 c does not overlap with the conductive plug 15.

図１９（ａ）に示すように、第１半導体回路層１ａの裏面を基準とした接着剤膜４４ｃの高さは、Ｈｄであり、例えば、２μｍに設定される。   As shown in FIG. 19A, the height of the adhesive film 44c with reference to the back surface of the first semiconductor circuit layer 1a is Hd, and is set to 2 μm, for example.

他方、第１半導体回路層１と同一の方法により製造された第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の表面（平坦化されている）に、図１６（ａ）及び図１９（ａ）に示すように、複数のマイクロバンプ電極４３ａ（高さはＨｂ）が形成される。電極４３ａは、第１半導体回路層１ａの電極４２と同一の方法で形成される。ここでは、第１実施形態と同様に、第１半導体回路層１ａ（Ｓｉウェハー１１）の裏面に設けられた電極４２の各々について、４個の電極４３ａが対応している。換言すれば、１個の電極４２に対して４個の電極４３ａが接合せしめられるようになっている。また、電極４２と４３ａを接触させて加圧した時に、電極４３ａのみが選択的に潰れる（塑性変形する）ようにするため、第１実施形態と同様に、電極４３ａは電極４２よりも機械的強度が低い導電性材料から形成されている。   On the other hand, on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2 manufactured by the same method as the first semiconductor circuit layer 1, FIG. As shown in FIG. 19A, a plurality of micro bump electrodes 43a (height is Hb) are formed. The electrode 43a is formed by the same method as the electrode 42 of the first semiconductor circuit layer 1a. Here, as in the first embodiment, four electrodes 43a correspond to each of the electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (Si wafer 11). In other words, four electrodes 43 a are bonded to one electrode 42. Further, when the electrodes 42 and 43a are brought into contact with each other and pressed, only the electrode 43a is selectively crushed (plastically deformed), so that the electrode 43a is more mechanical than the electrode 42 as in the first embodiment. It is formed from a conductive material having low strength.

第２半導体回路層２の表面を基準とした電極４３ａの高さＨｂは、例えば、２μｍに設定される。   The height Hb of the electrode 43a with respect to the surface of the second semiconductor circuit layer 2 is set to 2 μm, for example.

次に、第１実施形態における接着剤膜４４ａと同様にして、第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の表面に、図１６（ａ）及び図１９（ａ）に示すように、パターン化された電気的絶縁性の接着剤膜４４ｂ２が形成される。この接着剤膜４４ｂ２は、接着剤膜４４ｂ１と同じ電気絶縁性の接着剤を用いて形成されており、所定形状にパターン化（硬化）せしめられた後も粘性（接着性）を有しており、また、所定温度への加熱によりその表面を軟化または流動化させることが可能である。   Next, in the same manner as the adhesive film 44a in the first embodiment, on the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2, FIG. 16 (a) and FIG. 19 (a). As shown, a patterned electrically insulating adhesive film 44b2 is formed. This adhesive film 44b2 is formed using the same electrically insulating adhesive as the adhesive film 44b1, and has a viscosity (adhesiveness) after being patterned (cured) into a predetermined shape. In addition, the surface can be softened or fluidized by heating to a predetermined temperature.

接着剤膜４４ｂ２は、バンプ状（島状）に形成された多数の接着剤要素４４ｂｂ２から構成されており、それらの接着剤要素４４ｂｂ２は、図３２（ｂ）に示すようなレイアウトで、多層配線構造３０の表面に規則的に分布せしめられている。接着剤膜４４ｂ２は、電極４３ａと重ならない形状を持ち、電極４３ａが形成された箇所とその近傍を除いて配置されている。したがって、接着剤膜４４ｂ２（すなわち、すべての接着剤要素４４ｂｂ２）は電極４２（導電性プラグ１５）とも重ならない。   The adhesive film 44b2 is composed of a large number of adhesive elements 44bb2 formed in a bump shape (island shape). These adhesive elements 44bb2 have a layout as shown in FIG. It is distributed regularly on the surface of the structure 30. The adhesive film 44b2 has a shape that does not overlap with the electrode 43a, and is disposed except for a portion where the electrode 43a is formed and its vicinity. Therefore, the adhesive film 44b2 (that is, all the adhesive elements 44bb2) does not overlap with the electrode 42 (conductive plug 15).

第２半導体回路層２の表面を基準とした接着剤要素４４ｂｂ２の高さＨａは、例えば、３μｍに設定される。   The height Ha of the adhesive element 44bb2 with respect to the surface of the second semiconductor circuit layer 2 is set to 3 μm, for example.

接着剤膜４４ｃと４４ｂ２の全体積（硬化後の全体積）の和は、電極４２と４３ａを用いて第２半導体回路層２と第１半導体回路層１ａとを機械的・電気的に接続した際に、それら二つの回路層１ａと２の間に生じる隙間全体が接着剤膜４４ｃ及び４４ｂ２によって充填され、且つその隙間から余分の接着剤膜４４ｃ及び４４ｂ２がはみ出ないような値に設定されている。これは、回路層１ａと２の固着後に、当該隙間からはみ出た余分な接着剤膜４４ｃ及び４４ｂ２を除去する作業を避けることができるようにするためである。   The sum of the total volume (total volume after curing) of the adhesive films 44c and 44b2 is obtained by mechanically and electrically connecting the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a using the electrodes 42 and 43a. At this time, the entire gap formed between the two circuit layers 1a and 2 is filled with the adhesive films 44c and 44b2, and the value is set so that the excess adhesive films 44c and 44b2 do not protrude from the gap. Yes. This is to avoid the operation of removing the excess adhesive films 44c and 44b2 protruding from the gap after the circuit layers 1a and 2 are fixed.

図１９（ａ）に示すように、接着剤膜４４ｃの厚さＨｄは、電極４２の高さＨｃよりも小さくされているが（Ｈｄ＜Ｈｃ）、接着剤膜４４ｂ２の各接着剤要素４４ｂｂ２の高さＨａ（これは接着剤膜４４ｂ２の厚さに等しい）は、電極４３ａの高さＨｂよりも大きくされている（Ｈａ＞Ｈｂ）。このため、第２半導体回路層２と第１半導体回路層１ａとを接続した際に、加圧によって各接着剤要素４４ｂｂ２が押し潰されて電極４２と電極４３ａの周囲や各接着剤要素４４ｂｂ２間の隙間にまでそれぞれ広がって、回路層１ａと２の間に残存する隙間全体に充填されやすいようになっている。   As shown in FIG. 19A, the thickness Hd of the adhesive film 44c is smaller than the height Hc of the electrode 42 (Hd <Hc), but each adhesive element 44bb2 of the adhesive film 44b2 has a thickness Hd. The height Ha (which is equal to the thickness of the adhesive film 44b2) is larger than the height Hb of the electrode 43a (Ha> Hb). For this reason, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, each adhesive element 44bb2 is crushed by pressurization, and the periphery of the electrode 42 and the electrode 43a and between each adhesive element 44bb2. Each of the gaps between the circuit layers 1a and 2 is easily filled.

後述するが、第２半導体回路層２と第１半導体回路層１ａとを接続した際に、各電極４３ａも押し潰されて塑性変形しその周囲に広げられる。その結果、各電極４２に対応する４個の電極４３ａは相互に接続されて一体化される。   As will be described later, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, each electrode 43a is also crushed, plastically deformed, and spread around it. As a result, the four electrodes 43a corresponding to each electrode 42 are connected and integrated.

接着剤膜４４ｂ２が多数の接着剤要素４４ｂｂ２に分割されているのは、第２半導体回路層２と第１半導体回路層１ａとを接続する際に、両回路層２、１ａの間に存在する空気を外部に逃がしやすくするため（つまり脱ガスの容易化のため）である。すなわち、回路層２と１ａがほとんど接続された状態でも、両層２、１ａの間に存在する空気が隣接する接着剤要素４４ｂｂ２の間の隙間を通って外部に押し出されるようにするためである。   The adhesive film 44b2 is divided into a plurality of adhesive elements 44bb2 when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected to each other between the circuit layers 2 and 1a. This is to facilitate the escape of air to the outside (that is, to facilitate degassing). That is, even when the circuit layers 2 and 1a are almost connected, the air existing between the layers 2 and 1a is pushed out through the gap between the adjacent adhesive elements 44bb2. .

ここでは、マイクロバンプ電極４２を形成してから接着剤膜４４ｃを形成し、マイクロバンプ電極４３ａを形成してから接着剤膜４４ｂ２を形成しているが、接着剤膜４４ｃを形成してからマイクロバンプ電極４２を形成してもよいし、接着剤膜４４ｂ２を形成してからマイクロバンプ電極４３ａを形成してもよい。   Here, the adhesive film 44c is formed after the microbump electrode 42 is formed, and the adhesive film 44b2 is formed after the microbump electrode 43a is formed. However, after the adhesive film 44c is formed, the microbump electrode 42a is formed. The bump electrode 42 may be formed, or the microbump electrode 43a may be formed after the adhesive film 44b2 is formed.

続いて、図１６（ａ）及び図１９（ａ）に示すように、支持基板４０を介して固定された第１半導体回路層１ａの裏面に、下方から第２半導体回路層２の表面を対向させる。（逆に、第２半導体回路層２を固定しておき、上方から支持基板４０に固定された第１半導体回路層１ａを対向させてもよい。）その後、回路層２と１ａの間に押圧力を加えて回路層２と１ａを相互に近接させると、各接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きく（Ｈａ＞Ｈｂ）、接着剤膜４４ｃの厚さＨｄは、電極４２の高さＨｃよりも小さく（Ｈｄ＜Ｈｃ）、且つ、Ｈａ＋Ｈｄ＞Ｈｂ＋Ｈｃであるから、最初に、図１９（ｂ）に示すように、第２半導体回路層２の接着剤膜４４ｂ２（接着剤要素４４ｂｂ２）の先端（頂部）が第１半導体回路層１ａの接着剤膜４４ｃの表面に接触せしめられる。   Subsequently, as shown in FIGS. 16A and 19A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1a fixed via the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1a fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1a. When pressure is applied to bring the circuit layers 2 and 1a close to each other, the height of each adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is larger than the height Hb of the electrode 43a (Ha> Hb). Since the thickness Hd of the adhesive film 44c is smaller than the height Hc of the electrode 42 (Hd <Hc) and Ha + Hd> Hb + Hc, first, as shown in FIG. The tip (top) of the adhesive film 44b2 (adhesive element 44bb2) of the semiconductor circuit layer 2 is brought into contact with the surface of the adhesive film 44c of the first semiconductor circuit layer 1a.

その後、回路層２と１ａの間に押圧力を加えて両者間の距離を狭めることにより、図１６（ｂ）及び図２０（ｃ）に示すように、第２半導体回路層２の各電極４３ａを対応する第１半導体回路層１ａの電極４２に接触させる。この時の第１半導体回路層１ａの裏面と第２半導体回路層２の表面との距離、すなわち層間ギャップをＧ１とすると、層間ギャップＧ１は電極４２の厚さと電極４３ａの厚さの和に等しい、すなわちＧ１＝Ｈｃ＋Ｈｂである。この時、接着剤膜４４ｃ及び４４ｂ２はいずれも押し潰されて変形し、回路層１と２の間の隙間のほぼ全体に押し広げられるが、接着剤膜４４ｂ２は島状の接着剤要素４４ｂｂ２に分割されているので、接着剤膜４４ｂ２は当該隙間中にほぼ均一に広がる。また、変形せしめられた接着剤膜４４ｃと接着剤膜４４ｂ２との間（と隣接する接着剤要素４４ｂｂ２の間）には、空隙４５が形成されやすいことから、当該隙間中に残存する空気が空隙４５を通って外部に確実に排出されることができ、最終的に一体化・硬化せしめられた接着剤膜４４ｂ２ｃ中に気泡が生じる恐れをなくすことができる。   Thereafter, a pressing force is applied between the circuit layers 2 and 1a to reduce the distance between the two, and as shown in FIGS. 16B and 20C, each electrode 43a of the second semiconductor circuit layer 2 is obtained. Is brought into contact with the electrode 42 of the corresponding first semiconductor circuit layer 1a. When the distance between the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2 at this time, that is, the interlayer gap is G1, the interlayer gap G1 is equal to the sum of the thickness of the electrode 42 and the thickness of the electrode 43a. That is, G1 = Hc + Hb. At this time, the adhesive films 44c and 44b2 are both crushed and deformed, and are spread over almost the entire gap between the circuit layers 1 and 2, but the adhesive film 44b2 is formed on the island-shaped adhesive element 44bb2. Since it is divided, the adhesive film 44b2 spreads almost uniformly in the gap. Further, since the gap 45 is easily formed between the deformed adhesive film 44c and the adhesive film 44b2 (and between the adjacent adhesive elements 44bb2), the air remaining in the gap is void. It can be reliably discharged to the outside through 45, and the risk of bubbles being generated in the finally integrated and cured adhesive film 44b2c can be eliminated.

上述した第１半導体回路層１ａと第２半導体回路層２とを対向させてから電極４２と４３ａを相互接触させる工程は、第１実施形態と同様に、室温で行う。第１半導体回路層１ａと第２半導体回路層２との距離Ｇ１の値は、例えば２μｍ〜１０μｍの範囲で適宜決定されるが、典型的には４μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、２μｍ以下とすることも可能である。この場合、距離Ｇ１の値は、例えば０．１μｍ〜２μｍの範囲で適宜決定される。この点も第１実施形態と同様である。   The step of bringing the electrodes 42 and 43a into contact with each other after the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature, as in the first embodiment. The value of the distance G1 between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, but is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example. This is also the same as in the first embodiment.

その後、互いに接触せしめられた電極４３ａと電極４２を、以下のようにして相互に接合させる。   Thereafter, the electrode 43a and the electrode 42 brought into contact with each other are bonded to each other as follows.

すなわち、図１７（ｂ）及び図２０（ｃ）の状態にある第２半導体回路層２と第１半導体回路層１ａを室温から所定温度まで加熱する。その温度は、加圧変形状態にある接着剤膜４４ｃ及び４４ｂ２の表面（露出面）がわずかに軟化するか、それらの表面がわずかに流動状態になる温度に設定する。その温度は、接着剤膜４４ｃ及び４４ｂ２に使用する接着剤の種類によって異なるが、電極４２と電極４３ａとが「圧接」する温度を考慮しながら、例えば１００〜４００℃の範囲内で任意に設定される。このとき、設定する加熱温度によっては、電極４２及び電極４３ａの少なくとも一方が部分的に溶融状態となり、その表面が湾曲することがある。   That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a in the states of FIGS. 17B and 20C are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surfaces (exposed surfaces) of the adhesive films 44c and 44b2 in the pressure-deformed state are slightly softened or the surfaces are slightly fluidized. The temperature varies depending on the type of adhesive used for the adhesive films 44 c and 44 b 2, but is arbitrarily set within a range of, for example, 100 to 400 ° C. in consideration of the temperature at which the electrode 42 and the electrode 43 a “pressure contact”. Is done. At this time, depending on the heating temperature to be set, at least one of the electrode 42 and the electrode 43a may be partially melted and the surface thereof may be curved.

続いて、第１実施形態と同様にして、図１８（ｃ）及び図２０（ｄ）に示すように、回路層１ａと２の間の隙間を狭めることにより、回路層１ａと２の間の層間ギャップをＧ１からそれより小さいＧ２（Ｇ２＜Ｇ１）とする。この時、第１半導体回路層１ａの電極４２よりも機械的強度が低い第２半導体回路層２の電極４３ａのみが選択的に押し潰され、電極４２と電極４３とが「圧接」によって相互に接合せしめられると共に、接着剤要素４４ｂｂ２がさらに押し広げられて相互に連結・一体化され、さらに接着剤膜４４ｃとも連結・一体化される。このとき、１個の電極４２に対応する４個の電極４３ａが潰されて一体的になり、その結果、電極４２と電極４３ａとが一対一対応になる。こうして、相互に圧接された電極４３ａと電極４２の箇所を除いて、回路層２と１ａの間の隙間の全体が接着剤膜４４ｂ２ｃによって充填され、余分の接着剤膜４４ｂ１または４４ｂ２が当該隙間からはみ出ることもない。この時の状態は図１８（ｃ）及び図２０（ｃ）に示すようになる。   Subsequently, as in the first embodiment, as shown in FIGS. 18C and 20D, the gap between the circuit layers 1a and 2 is reduced by narrowing the gap between the circuit layers 1a and 2. The interlayer gap is set to G2 smaller than G1 (G2 <G1). At this time, only the electrode 43a of the second semiconductor circuit layer 2 whose mechanical strength is lower than that of the electrode 42 of the first semiconductor circuit layer 1a is selectively crushed, and the electrode 42 and the electrode 43 are mutually pressed by “pressure contact”. At the same time, the adhesive element 44bb2 is further spread and connected to and integrated with each other, and further connected to and integrated with the adhesive film 44c. At this time, the four electrodes 43a corresponding to one electrode 42 are crushed and integrated, and as a result, the electrodes 42 and the electrodes 43a have a one-to-one correspondence. Thus, the entire gap between the circuit layers 2 and 1a is filled with the adhesive film 44b2c except for the portions of the electrode 43a and the electrode 42 that are in pressure contact with each other, and the extra adhesive film 44b1 or 44b2 is removed from the gap. It does not protrude. The state at this time is as shown in FIG. 18 (c) and FIG. 20 (c).

加熱時に電極４２及び電極４３ａの少なくとも一方が部分的に溶融状態となった場合は、電極４２と電極４３ａの接合は、溶融した電極４２、４３ａの「再凝固」により行われるか、「圧接」と「再凝固」が混合した形で行われる。この点は第１実施形態と同様である。   When at least one of the electrode 42 and the electrode 43a is partially melted during heating, the electrode 42 and the electrode 43a are joined by “re-solidification” of the melted electrodes 42 and 43a or “pressure welding”. And “re-solidification” are performed in a mixed form. This is the same as in the first embodiment.

この加熱圧接工程では、層間ギャップがＧ１からＧ２に減少せしめられる際に、接着剤膜４４ｂ２が多数の接着剤要素４４ｂｂ２に分割されているので、回路層１ａと２の間の隙間に存在する空気は、接着剤膜４４ｃ及び４４ｂ２（これらはいずれも加熱によって表面が軟化または流動化している）の間の空隙４５と、隣接する接着剤要素４４ｂｂ２の間に残存する微小空間とを通って、外部に確実に排出されることができる。また、接着剤膜４４ｃの表面と接着剤膜４４ｂｂ２の表面がいずれも軟化または流動化しているので、層間ギャップがＧ２になった時に、接着剤膜４４ｃと接着剤膜４４ｂｂ２が接着されやすく、その結果、回路層１ａと２が確実に相互接着されることができる。   In this heating and pressing process, when the interlayer gap is reduced from G1 to G2, the adhesive film 44b2 is divided into a large number of adhesive elements 44bb2, so that air existing in the gap between the circuit layers 1a and 2 is present. Passes through the gap 45 between the adhesive films 44c and 44b2 (both of which are softened or fluidized by heating) and the minute space remaining between the adjacent adhesive elements 44bb2, Can be reliably discharged. In addition, since both the surface of the adhesive film 44c and the surface of the adhesive film 44bb2 are softened or fluidized, when the interlayer gap becomes G2, the adhesive film 44c and the adhesive film 44bb2 are easily bonded. As a result, the circuit layers 1a and 2 can be securely bonded to each other.

層間ギャップＧ２の値は、例えば１μｍ〜９μｍの範囲で適宜決定されるが、典型的には３μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、１μｍ以下とすることも可能である。この場合、距離Ｇ２の値は、例えば０．０５μｍ〜１μｍの範囲で適宜決定される。   The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

第２半導体回路層２は、以上のようにして、電極４２と電極４３ａを用いて第１半導体回路層１ａの裏面側に固着（つまり機械的に接続）せしめられると共に、両回路層１ａ及び２の間の電気的接続も同時に行われる。また、それと同時に、両回路層１ａ及び２は、互いに圧接せしめられた電極４３ａと電極４２の箇所を除いて回路層１ａと２の間の隙間全体に充填された接着剤膜４４ｃ及び４４ｂ２によって、相互に接着される。   As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1a using the electrode 42 and the electrode 43a, and both the circuit layers 1a and 2 are connected. The electrical connection between is also made simultaneously. At the same time, the circuit layers 1a and 2 are bonded to each other by the adhesive films 44c and 44b2 filled in the entire gap between the circuit layers 1a and 2 except for the portions of the electrodes 43a and 42 that are pressed against each other. Bonded to each other.

以上のようにして電極４２と電極４３ａの機械的・電気的接続と接着剤膜４４ｃ及び４４ｂ２の接着が終わると、相互に接合された回路層１と２ａは室温まで自然冷却される。そこで、加熱、紫外線照射、薬剤添加等によって一体化された接着剤膜４４ｂ１及び４４ｂ２を最終的に硬化させる。処理が容易であることから、加熱により硬化させるのが好ましい。加熱温度は、接着剤膜４４ｂ１及び４４ｂ２として使用した接着剤の性質に応じて、例えば１２０〜５００℃の範囲内で適宜設定される。こうして、二つの半導体回路層１ａと２の間の機械的接続と電気的接続が完了する。   When the mechanical and electrical connection between the electrode 42 and the electrode 43a and the bonding of the adhesive films 44c and 44b2 are completed as described above, the circuit layers 1 and 2a bonded to each other are naturally cooled to room temperature. Therefore, the adhesive films 44b1 and 44b2 integrated by heating, ultraviolet irradiation, chemical addition, etc. are finally cured. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive films 44b1 and 44b2. Thus, the mechanical connection and the electrical connection between the two semiconductor circuit layers 1a and 2 are completed.

その後の工程は、第１実施形態の場合と同じであるから、その説明は省略する。   Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

以上説明したように、本発明の第３実施形態に係る集積回路装置の製造方法は、第１半導体回路層１ａの裏面と第２半導体回路層２の表面の双方に電気的絶縁性の接着剤膜４４ｃ及び４４ｂ２をそれぞれ形成した点を除いて、上述した第１実施形態に係る集積回路装置の製造方法と同じであるから、第１実施形態において得られるものと同一の効果が得られることは明らかである。ただ、第３実施形態では、二つの接着剤膜４４ｃ及び４４ｂ２を使用しているので、第２実施形態と同様に、第１実施形態におけるよりも第２半導体回路層２と第１半導体回路層１ａの接着力が増すという利点がある。   As described above, the manufacturing method of the integrated circuit device according to the third embodiment of the present invention is an electrically insulating adhesive on both the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2. Since the manufacturing method of the integrated circuit device according to the first embodiment is the same as that of the first embodiment except that the films 44c and 44b2 are formed, the same effect as that obtained in the first embodiment can be obtained. it is obvious. However, in the third embodiment, since the two adhesive films 44c and 44b2 are used, as in the second embodiment, the second semiconductor circuit layer 2 and the first semiconductor circuit layer than in the first embodiment are used. There is an advantage that the adhesive force of 1a is increased.

第３実施形態では、接着剤膜４４ｂ２は接着剤要素に分割されているが、接着剤膜４４ｃは接着剤要素に分割されていないので、回路層１と２ａの間の隙間４５にある空気の排出されやすさは、それだけ第２実施形態よりも劣る。しかし、接着剤膜４４ｃを接着剤要素に分割する必要がないため、接着剤膜４４ｃの形成工程はそれだけ容易である。   In the third embodiment, the adhesive film 44b2 is divided into adhesive elements, but since the adhesive film 44c is not divided into adhesive elements, the air in the gap 45 between the circuit layers 1 and 2a Ease of discharging is inferior to that of the second embodiment. However, since it is not necessary to divide the adhesive film 44c into adhesive elements, the process of forming the adhesive film 44c is that much easier.

（第４実施形態）
図２１（ａ）〜図２３（ｃ）及び図２４（ａ）〜図２５（ｃ）は、本発明の第４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図である。この第４実施形態も、半導体ウェハーを積み重ねて三次元積層構造を持つ集積回路装置を製造する例である。 (Fourth embodiment)
21 (a) to 23 (c) and FIGS. 24 (a) to 25 (c) show a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fourth embodiment of the present invention for each step. It is a fragmentary sectional view shown. The fourth embodiment is also an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

第４実施形態の集積回路装置の製造方法は、三次元積層構造を構成する第１半導体回路層１ａの裏面（第２主面）と第２半導体回路層２の表面（第１主面）の双方に電気的絶縁性の接着剤膜４４ｃ１及び４４ｃ２をそれぞれ形成した点を除き、第１実施形態の集積回路装置の製造方法と同一である。接着剤膜４４ｃ１は、導電性プラグ１５及びマイクロバンプ電極４２とは重ならない形状を持つが、連続的に形成されており、多数の接着剤要素には分割されていない。接着剤膜４４ｃ２も同様に、マイクロバンプ電極４３ａとは重ならない形状を持つが、連続的に形成されており、多数の接着剤要素には分割されていない。よって、以下では、第１実施形態と同一の工程についてはその概略のみを説明し、相違する工程について詳細に説明する。   The manufacturing method of the integrated circuit device of 4th Embodiment is the back surface (2nd main surface) of the 1st semiconductor circuit layer 1a and the surface (1st main surface) of the 2nd semiconductor circuit layer 2 which comprise a three-dimensional laminated structure. The method is the same as the method of manufacturing the integrated circuit device of the first embodiment except that electrically insulating adhesive films 44c1 and 44c2 are formed on both sides. The adhesive film 44c1 has a shape that does not overlap the conductive plug 15 and the microbump electrode 42, but is formed continuously and is not divided into a large number of adhesive elements. Similarly, the adhesive film 44c2 has a shape that does not overlap the microbump electrode 43a, but is formed continuously and is not divided into a large number of adhesive elements. Therefore, below, only the outline is demonstrated about the process same as 1st Embodiment, and a different process is demonstrated in detail.

図２１（ａ）〜図２３（ｃ）は、第１実施形態における図５（ｊ）〜図７（ｌ）にそれぞれ対応する。また、図２４（ａ）〜図２５（ｃ）は、第１実施形態における図９（ａ）〜図１０（ｃ）にそれぞれ対応する。   FIG. 21A to FIG. 23C correspond to FIG. 5J to FIG. 7L in the first embodiment, respectively. FIGS. 24A to 25C correspond to FIGS. 9A to 10C in the first embodiment, respectively.

まず、第１実施形態と同一の工程により、図４（ｈ）に示す構成の第１半導体回路層１ａを形成する。その後、第１実施形態と同一の材料を用い且つ同一の方法で、図４（ｉ）に示すように、露出した各導電性プラグ１５の下端にそれぞれマイクロバンプ電極４２を形成する。   First, the first semiconductor circuit layer 1a having the configuration shown in FIG. 4H is formed by the same process as in the first embodiment. Thereafter, using the same material as in the first embodiment and by the same method, as shown in FIG. 4I, a microbump electrode 42 is formed at the lower end of each exposed conductive plug 15, respectively.

第１半導体回路層１ａの裏面を基準とした電極４２の高さＨｃは、例えば２．５μｍとされる。   The height Hc of the electrode 42 with respect to the back surface of the first semiconductor circuit layer 1a is, for example, 2.5 μm.

次に、第１実施形態における接着剤膜４４ａ及び第２実施形態における接着剤膜４４ｂ１と同様にして、図２１（ａ）及び図２４（ａ）に示すように、第１半導体回路層１ａの裏面（第２主面）すなわちＳｉＯ2膜４１の露出面に、パターン化されていない電気的絶縁性の接着剤膜４４ｃ１を形成する。この接着剤膜４４ｃ１は、ポリイミド樹脂やＳＯＧ材料等の電気絶縁性の接着剤を室温でパターン化（硬化）することにより形成されたものであって、所定温度に加熱することによりその表面（露出面）を軟化または流動化することが可能である。 Next, similarly to the adhesive film 44a in the first embodiment and the adhesive film 44b1 in the second embodiment, as shown in FIGS. 21A and 24A, the first semiconductor circuit layer 1a is formed. An unpatterned electrically insulating adhesive film 44c1 is formed on the back surface (second main surface), that is, the exposed surface of the SiO 2 film 41. The adhesive film 44c1 is formed by patterning (curing) an electrically insulating adhesive such as polyimide resin or SOG material at room temperature, and its surface (exposed) is heated to a predetermined temperature. Surface) can be softened or fluidized.

接着剤膜４４ｃ１は、電極４２（そして導電性プラグ１５）とは重ならない形状を持つが、接着剤要素に分割されておらず、電極４２のある箇所とその近傍を除いてＳｉＯ2膜４１の露出面の全体を覆っている。したがって、接着剤膜４４ｃ１は導電性プラグ１５とも重ならない。 The adhesive film 44 c 1 has a shape that does not overlap the electrode 42 (and the conductive plug 15), but is not divided into adhesive elements, and the SiO 2 film 41 except for a portion where the electrode 42 is present and its vicinity. Covers the entire exposed surface. Therefore, the adhesive film 44 c 1 does not overlap with the conductive plug 15.

図２４（ａ）に示すように、第１半導体回路層１ａの裏面を基準とした接着剤要素４４ｃ１の高さは、Ｈｄであり、例えば、２μｍに設定される。   As shown in FIG. 24A, the height of the adhesive element 44c1 with respect to the back surface of the first semiconductor circuit layer 1a is Hd, and is set to 2 μm, for example.

他方、第１半導体回路層１と同一の方法により製造された第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の表面（平坦化されている）に、図２１（ａ）及び図２４（ａ）に示すように、複数のマイクロバンプ電極４３ａ（高さはＨｂ）が形成される。電極４３ａは、第１半導体回路層１ａの電極４２と同一の方法で形成される。ここでは、第１実施形態と同様に、第１半導体回路層１ａ（Ｓｉウェハー１１）の裏面に設けられた電極４２の各々について、４個の電極４３ａが対応している。換言すれば、１個の電極４２に対して４個の電極４３ａが接合せしめられるようになっている。また、電極４２と４３ａを接触させて加圧した時に、電極４３ａのみが選択的に潰れる（塑性変形する）ようにするため、第１実施形態と同様に、電極４３ａは電極４２よりも機械的強度が低い導電性材料から形成されている。   On the other hand, on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2 manufactured by the same method as the first semiconductor circuit layer 1, FIG. As shown in FIG. 24A, a plurality of micro bump electrodes 43a (height is Hb) are formed. The electrode 43a is formed by the same method as the electrode 42 of the first semiconductor circuit layer 1a. Here, as in the first embodiment, four electrodes 43a correspond to each of the electrodes 42 provided on the back surface of the first semiconductor circuit layer 1a (Si wafer 11). In other words, four electrodes 43 a are bonded to one electrode 42. Further, when the electrodes 42 and 43a are brought into contact with each other and pressed, only the electrode 43a is selectively crushed (plastically deformed), so that the electrode 43a is more mechanical than the electrode 42 as in the first embodiment. It is formed from a conductive material having low strength.

第２半導体回路層２の表面を基準とした電極４３ａの高さＨｂは、例えば、２．５μｍに設定される。   The height Hb of the electrode 43a with respect to the surface of the second semiconductor circuit layer 2 is set to 2.5 μm, for example.

次に、第１実施形態における接着剤膜４４ａと同様にして、第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の表面に、図２１（ａ）及び図２４（ａ）に示すように、パターン化された電気的絶縁性の接着剤膜４４ｃ２が形成される。この接着剤膜４４ｃ２は、接着剤膜４４ｃ１と同じ電気絶縁性の接着剤を用いて形成されており、所定形状に硬化せしめられた後も粘性（接着性）を有しており、また、所定温度への加熱によりその表面を軟化または流動化させることが可能である。   Next, in the same manner as the adhesive film 44a in the first embodiment, on the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2, FIG. 21 (a) and FIG. 24 (a). As shown, a patterned electrically insulating adhesive film 44c2 is formed. The adhesive film 44c2 is formed using the same electrically insulating adhesive as the adhesive film 44c1, and has a viscosity (adhesiveness) after being cured into a predetermined shape. The surface can be softened or fluidized by heating to temperature.

接着剤膜４４ｃ２も、接着剤膜４４ｃ１と同様に、電極４３ａとは重ならない形状を持つが、接着剤要素に分割されておらず、電極４３ａのある箇所とその近傍を除いて多層配線構造３０の表面の全体を覆っている。   Similarly to the adhesive film 44c1, the adhesive film 44c2 has a shape that does not overlap the electrode 43a, but is not divided into adhesive elements, and the multilayer wiring structure 30 except for a portion where the electrode 43a is located and its vicinity. Covers the entire surface of the.

第２半導体回路層２の表面を基準とした接着剤膜４４ｃ２の厚さＨａは、例えば、２μｍに設定される。   A thickness Ha of the adhesive film 44c2 with respect to the surface of the second semiconductor circuit layer 2 is set to 2 μm, for example.

接着剤膜４４ｃ１と４４ｃ２の全体積（硬化後の全体積）の和は、電極４２と４３ａを用いて第２半導体回路層２と第１半導体回路層１ａとを機械的・電気的に接続した際に、それら二つの回路層１ａと２の間に生じる隙間全体が接着剤膜４４ｃ１及び４４ｃ２によって充填され、且つその隙間から余分の接着剤膜４４ｃ１及び４４ｃ２がはみ出ないような値に設定されている。これは、回路層１ａと２の接続後に、当該隙間からはみ出た余分な接着剤膜４４ｃ１及び４４ｃ２を除去する作業を避けることができるようにするためである。   The sum of the total volume (total volume after curing) of the adhesive films 44c1 and 44c2 is obtained by mechanically and electrically connecting the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a using the electrodes 42 and 43a. At this time, the entire gap formed between the two circuit layers 1a and 2 is filled with the adhesive films 44c1 and 44c2, and the adhesive film 44c1 and 44c2 are set so as not to protrude from the gap. Yes. This is to avoid the operation of removing the excess adhesive films 44c1 and 44c2 protruding from the gap after the circuit layers 1a and 2 are connected.

接着剤膜４４ｃ１及び４４ｃ２は、電極４２と４３ａがある箇所とその近傍には存在しないため、図２４（ａ）に示すように、接着剤膜４４ｃ１の厚さＨｄは、電極４２の高さＨｃよりも小さく設定され（Ｈｄ＜Ｈｃ）、且つ、接着剤膜４４ｃ２の厚さＨａは、電極４３ａの高さＨｂよりも小さく設定されている（Ｈａ＜Ｈｂ）。これは、第２半導体回路層２と第１半導体回路層１ａとを接続した際に、加圧によって接着剤膜４４ｃ１と４４ｃ２がそれぞれ押し潰されて電極４２と電極４３ａの周囲にまで広がって、回路層１ａと２の間に残存する隙間全体に充填されるようにするためである。   Since the adhesive films 44c1 and 44c2 do not exist in the vicinity of the positions where the electrodes 42 and 43a are present, the thickness Hd of the adhesive film 44c1 is equal to the height Hc of the electrode 42 as shown in FIG. Is set smaller (Hd <Hc), and the thickness Ha of the adhesive film 44c2 is set smaller than the height Hb of the electrode 43a (Ha <Hb). This is because when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, the adhesive films 44c1 and 44c2 are crushed by the pressure and spread around the electrodes 42 and 43a, This is because the entire gap remaining between the circuit layers 1a and 2 is filled.

後述するが、第２半導体回路層２と第１半導体回路層１ａとを接続した際に、各電極４３ａも押し潰されて塑性変形しその周囲に広げられる。その結果、各電極４２に対応する４個の電極４３ａは相互に接続されて一体化される。   As will be described later, when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a are connected, each electrode 43a is also crushed, plastically deformed, and spread around it. As a result, the four electrodes 43a corresponding to each electrode 42 are connected and integrated.

ここでは、マイクロバンプ電極４２を形成してから接着剤膜４４ｃ１を形成し、マイクロバンプ電極４３ａを形成してから接着剤膜４４ｃ２を形成しているが、接着剤膜４４ｃ１を形成してからマイクロバンプ電極４２を形成してもよいし、接着剤膜４４ｃ２を形成してからマイクロバンプ電極４３ａを形成してもよい。   Here, the adhesive film 44c1 is formed after the microbump electrode 42 is formed, and the adhesive film 44c2 is formed after the microbump electrode 43a is formed. However, the microbump electrode 42a is formed after the adhesive film 44c1 is formed. The bump electrode 42 may be formed, or the microbump electrode 43a may be formed after the adhesive film 44c2 is formed.

続いて、図２１（ａ）及び図２４（ａ）に示すように、支持基板４０を介して固定された第１半導体回路層１ａの裏面に、下方から第２半導体回路層２の表面を対向させる。（逆に、第２半導体回路層２を固定しておき、上方から支持基板４０に固定された第１半導体回路層１ａを対向させてもよい。）その後、回路層２と１ａの間に押圧力を加えて回路層２と１ａを相互に近接させると、接着剤膜４４ｃ１の厚さＨｄは電極４２の高さＨｃよりも小さく設定され（Ｈｄ＜Ｈｃ）、接着剤膜４４ｃ２の厚さＨａは電極４３ａの高さＨｂよりも小さく設定されている（Ｈａ＜Ｈｂ）ので、最初に、図２２（ｂ）及び図２４（ｂ）に示すように、第２半導体回路層２の電極４２の先端（頂部）が第１半導体回路層１ａの電極４３ａの先端（頂部）に接触せしめられる。この時の回路層１と２の間の層間ギャップはＧ１である（Ｇ１＝Ｈｃ＋Ｈｂ）。   Subsequently, as shown in FIGS. 21A and 24A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1a fixed via the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1a fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1a. When the circuit layers 2 and 1a are brought close to each other by applying pressure, the thickness Hd of the adhesive film 44c1 is set to be smaller than the height Hc of the electrode 42 (Hd <Hc), and the thickness Ha of the adhesive film 44c2 is set. Is set to be smaller than the height Hb of the electrode 43a (Ha <Hb). First, as shown in FIGS. 22B and 24B, the electrode 42 of the second semiconductor circuit layer 2 The tip (top) is brought into contact with the tip (top) of the electrode 43a of the first semiconductor circuit layer 1a. The interlayer gap between the circuit layers 1 and 2 at this time is G1 (G1 = Hc + Hb).

この時、接着剤膜４４ｃ１及び４４ｃ２は接合・一体化せず、接着剤膜４４ｃ１及び４４ｃ２の対向面の間に隙間４５が形成される。このため、空気はその隙間４５を通って容易に外部に排出されることができる。   At this time, the adhesive films 44c1 and 44c2 are not joined and integrated, and a gap 45 is formed between the opposing surfaces of the adhesive films 44c1 and 44c2. For this reason, air can be easily discharged outside through the gap 45.

上述した第１半導体回路層１ａと第２半導体回路層２とを対向させてから電極４２と４３ａを相互接触させる工程は、第１実施形態と同様に、室温で行う。第１半導体回路層１ａと第２半導体回路層２との距離Ｇ１の値は、例えば２μｍ〜１０μｍの範囲で適宜決定されるが、典型的には４μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、２μｍ以下とすることも可能である。この場合、距離Ｇ１の値は、例えば０．１μｍ〜２μｍの範囲で適宜決定される。この点も第１実施形態と同様である。   The step of bringing the electrodes 42 and 43a into contact with each other after the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature, as in the first embodiment. The value of the distance G1 between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, but is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example. This is also the same as in the first embodiment.

その後、互いに接触せしめられた電極４３ａと電極４２を、以下のようにして相互に接合させる。   Thereafter, the electrode 43a and the electrode 42 brought into contact with each other are bonded to each other as follows.

すなわち、図２２（ｂ）及び図２４（ｂ）の状態にある第２半導体回路層２と第１半導体回路層１ａを室温から所定温度まで加熱する。その温度は、接着剤膜４４ｃ１及び４４ｃ２の表面（露出面）がわずかに軟化するか、それらの表面がわずかに流動状態になる温度に設定する。その温度は、接着剤膜４４ｃ１及び４４ｃ２に使用する接着剤の種類によって異なるが、電極４２と電極４３ａとが「圧接」する温度を考慮しながら、例えば１００〜４００℃の範囲内で任意に設定される。このとき、設定する加熱温度によっては、電極４２及び電極４３ａの少なくとも一方が部分的に溶融状態となり、その表面が湾曲することがある。   That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1a in the states of FIGS. 22B and 24B are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surfaces (exposed surfaces) of the adhesive films 44c1 and 44c2 are slightly softened or the surfaces thereof are slightly fluidized. The temperature differs depending on the type of adhesive used for the adhesive films 44c1 and 44c2, but is arbitrarily set within a range of, for example, 100 to 400 ° C. in consideration of the temperature at which the electrode 42 and the electrode 43a are “pressed”. Is done. At this time, depending on the heating temperature to be set, at least one of the electrode 42 and the electrode 43a may be partially melted and the surface thereof may be curved.

続いて、押圧力を印加することにより、第１実施形態と同様にして、図２３（ｃ）及び図２５（ｃ）に示すように、回路層１ａと２の間の隙間を狭めることにより、回路層１ａと２の間の層間ギャップをＧ１からそれより小さいＧ２（Ｇ２＜Ｇ１）とする。この時、第２半導体回路層２の電極４３ａと第１半導体回路層１ａの電極４２の間には、圧縮力が作用する。その結果、電極４２よりも機械的強度が低い電極４３ａのみが選択的に押し潰されて、電極４２と電極４３とが「圧接」によって相互に接合せしめられると共に、接着剤膜４４ｃ１及び４４ｃ２が相互に接触し、押し広げられながら相互に連結・一体化される。このとき、１個の電極４２に対応する４個の電極４３ａが潰されて一体的になり、その結果、電極４２と電極４３ａとが一対一対応になる。こうして、相互に圧接された電極４３ａと電極４２の箇所を除いて、回路層２と１ａの間の隙間の全体が接着剤膜４４ｃ１ｃ２によって充填され、余分の接着剤膜４４ｃ１または４４ｃ２が当該隙間からはみ出ることもない。る。この時の状態は図２３（ｃ）及び図２５（ｃ）に示すようになる。   Subsequently, by applying a pressing force, as in the first embodiment, as shown in FIGS. 23 (c) and 25 (c), by narrowing the gap between the circuit layers 1a and 2, The interlayer gap between the circuit layers 1a and 2 is G2 and smaller G2 (G2 <G1). At this time, a compressive force acts between the electrode 43a of the second semiconductor circuit layer 2 and the electrode 42 of the first semiconductor circuit layer 1a. As a result, only the electrode 43a having a mechanical strength lower than that of the electrode 42 is selectively crushed so that the electrode 42 and the electrode 43 are joined to each other by “pressure contact”, and the adhesive films 44c1 and 44c2 are mutually connected. It is connected and integrated with each other while being pushed and spread. At this time, the four electrodes 43a corresponding to one electrode 42 are crushed and integrated, and as a result, the electrodes 42 and the electrodes 43a have a one-to-one correspondence. In this way, the entire gap between the circuit layers 2 and 1a is filled with the adhesive film 44c1c2 except for the portions of the electrodes 43a and 42 that are in pressure contact with each other, and the extra adhesive film 44c1 or 44c2 is removed from the gap. It does not protrude. The The state at this time is as shown in FIG. 23 (c) and FIG. 25 (c).

加熱時に電極４２及び電極４３ａの少なくとも一方が部分的に溶融状態となった場合は、電極４２と電極４３ａの接合は、溶融した電極４２、４３ａの「再凝固」により行われるか、「圧接」と「再凝固」が混合した形で行われる。この点は第１実施形態と同様である。   When at least one of the electrode 42 and the electrode 43a is partially melted during heating, the electrode 42 and the electrode 43a are joined by “re-solidification” of the melted electrodes 42 and 43a or “pressure welding”. And “re-solidification” are performed in a mixed form. This is the same as in the first embodiment.

この第４実施形態では、接着剤膜４４ｃ１及び４４ｃ２の双方が接着剤要素に分割されていないので、この加熱圧接工程では、接着剤膜４４ｃ１及び４４ｃ２の対向面の間に存在する空気は、層間ギャップがＧ２に狭められる前に隙間４５を通って外部に排出される。接着剤膜４４ｃ１の表面と接着剤膜４４ｃ２の表面がいずれも軟化または流動化しているので、層間ギャップがＧ２になった時に、接着剤膜４４ｃ１と接着剤膜４４ｃ２が接着されやすく、その結果、回路層１ａと２が確実に相互接着されることができる。この点は、第１実施形態と同様である。   In the fourth embodiment, since both of the adhesive films 44c1 and 44c2 are not divided into adhesive elements, the air existing between the opposing surfaces of the adhesive films 44c1 and 44c2 is not heated between Before the gap is narrowed to G2, it is discharged to the outside through the gap 45. Since both the surface of the adhesive film 44c1 and the surface of the adhesive film 44c2 are softened or fluidized, the adhesive film 44c1 and the adhesive film 44c2 are easily bonded when the interlayer gap becomes G2, and as a result, The circuit layers 1a and 2 can be securely bonded to each other. This is the same as in the first embodiment.

層間ギャップＧ２の値は、例えば１μｍ〜９μｍの範囲で適宜決定されるが、典型的には３μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、１μｍ以下とすることも可能である。この場合、距離Ｇ２の値は、例えば０．０５μｍ〜１μｍの範囲で適宜決定される。   The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

第２半導体回路層２は、以上のようにして、電極４２と電極４３ａを用いて第１半導体回路層１ａの裏面側に固着（つまり機械的に接続）せしめられると共に、両回路層１ａ及び２の間の電気的接続も同時に行われる。また、それと同時に、両回路層１ａ及び２は、互いに接続された電極４３ａと電極４２の箇所を除いて回路層１ａと２の間の隙間全体に充填された接着剤膜４４ｂ１及び４４ｂ２によって、相互に接着される。   As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1a using the electrode 42 and the electrode 43a, and both the circuit layers 1a and 2 are connected. The electrical connection between is also made simultaneously. At the same time, both circuit layers 1a and 2 are mutually connected by adhesive films 44b1 and 44b2 filled in the entire gap between the circuit layers 1a and 2 except for the portions of the electrodes 43a and 42 connected to each other. Glued to.

以上のようにして電極４２と電極４３ａの機械的・電気的接続と接着剤膜４４ｃ１及び４４ｃ２の接着が終わると、相互に接合された回路層１と２ａは室温まで自然冷却される。そこで、加熱、紫外線照射、薬剤添加等によって一体化された接着剤膜４４ｃ１及び４４ｃ２を最終的に硬化させる。処理が容易であることから、加熱により硬化させるのが好ましい。加熱温度は、接着剤膜４４ｃ１及び４４ｃとして使用した接着剤の性質に応じて、例えば１２０〜５００℃の範囲内で適宜設定される。こうして、二つの半導体回路層１ａと２の間の機械的接続と電気的接続が完了する。   When the mechanical / electrical connection between the electrode 42 and the electrode 43a and the bonding of the adhesive films 44c1 and 44c2 are completed as described above, the circuit layers 1 and 2a bonded to each other are naturally cooled to room temperature. Therefore, the adhesive films 44c1 and 44c2 integrated by heating, ultraviolet irradiation, chemical addition, etc. are finally cured. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive films 44c1 and 44c. Thus, the mechanical connection and the electrical connection between the two semiconductor circuit layers 1a and 2 are completed.

その後の工程は、第１実施形態の場合と同じであるから、その説明は省略する。   Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

以上説明したように、本発明の第４実施形態に係る集積回路装置の製造方法は、第１半導体回路層１ａの裏面と第２半導体回路層２の表面の双方に電気的絶縁性の接着剤膜４４ｃ１及び４４ｃ２をそれぞれ形成した点を除いて、上述した第１実施形態に係る集積回路装置の製造方法と同じであるから、第１実施形態において得られるものと同一の効果が得られることは明らかである。ただ、第４実施形態では、二つの接着剤膜４４ｃ１及び４４ｃ２を使用しているので、第２実施形態と同様に、第１実施形態におけるよりも第２半導体回路層２と第１半導体回路層１ａの接着力が増すという利点がある。   As described above, the method for manufacturing an integrated circuit device according to the fourth embodiment of the present invention has an electrically insulating adhesive on both the back surface of the first semiconductor circuit layer 1a and the surface of the second semiconductor circuit layer 2. Except for forming the films 44c1 and 44c2, respectively, it is the same as the manufacturing method of the integrated circuit device according to the first embodiment described above, and therefore the same effect as that obtained in the first embodiment can be obtained. it is obvious. However, in the fourth embodiment, since the two adhesive films 44c1 and 44c2 are used, as in the second embodiment, the second semiconductor circuit layer 2 and the first semiconductor circuit layer than in the first embodiment are used. There is an advantage that the adhesive force of 1a is increased.

第４実施形態では、接着剤膜４４ｃ１及び４４ｃ２の双方が接着剤要素に分割されていないので、回路層１と２ａの間の隙間４５にある空気の排出されやすさは、それだけ第２実施形態よりも劣る。しかし、接着剤膜４４ｃ１及び４４ｃ２を接着剤要素に分割する必要がないため、接着剤膜４４ｃ１及び４４ｃ２の形成工程はそれだけ容易である。   In the fourth embodiment, since both of the adhesive films 44c1 and 44c2 are not divided into adhesive elements, the air in the gap 45 between the circuit layers 1 and 2a is easily discharged as much as the second embodiment. Inferior to. However, since it is not necessary to divide the adhesive films 44c1 and 44c2 into adhesive elements, the process of forming the adhesive films 44c1 and 44c2 is much easier.

（第５実施形態）
図２６（ａ）〜図２９（ｅ）及び図３０（ａ）〜図３１（ｄ）は、本発明の第５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図である。この第５実施形態も、半導体ウェハーを積み重ねて三次元積層構造を持つ集積回路装置を製造する例である。 (Fifth embodiment)
26 (a) to 29 (e) and FIGS. 30 (a) to 31 (d) show a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention for each step. It is a fragmentary sectional view shown. The fifth embodiment is also an example of manufacturing an integrated circuit device having a three-dimensional stacked structure by stacking semiconductor wafers.

第５実施形態の集積回路装置の製造方法は、三次元積層構造を構成する第１半導体回路層１ａの裏面（第２主面）にはマイクロバンプ電極を形成せず、導電性プラグ１５の端を直接、第２半導体回路層２の表面（第１主面）のマイクロバンプ電極４３ａに接触させるようにした点を除き、第１実施形態の集積回路装置の製造方法と同一である。よって、以下では、第１実施形態と同一の工程についてはその概略のみを説明し、相違する工程について詳細に説明する。   In the manufacturing method of the integrated circuit device of the fifth embodiment, the microbump electrode is not formed on the back surface (second main surface) of the first semiconductor circuit layer 1a constituting the three-dimensional stacked structure, and the end of the conductive plug 15 is formed. Is directly in contact with the micro bump electrode 43a on the surface (first main surface) of the second semiconductor circuit layer 2, and is the same as the manufacturing method of the integrated circuit device of the first embodiment. Therefore, below, only the outline is demonstrated about the process same as 1st Embodiment, and a different process is demonstrated in detail.

まず、第１実施形態と同一の工程により、図３（ｆ）に示す構成の第１半導体回路層１ａを形成する。その後、第１実施形態と同様にして、基板１１の裏面と露出したＳｉＯ2膜１４の上にＳｉＯ2膜４１を形成し、図３（ｇ）に示す構成を得る。こうして得た構成を再度、図２６（ａ）に示している。この後の工程は、第１実施形態とは異なる。 First, the first semiconductor circuit layer 1a having the configuration shown in FIG. 3F is formed by the same process as in the first embodiment. Thereafter, similarly to the first embodiment, the SiO 2 film 41 is formed on the back surface of the substrate 11 and the exposed SiO 2 film 14 to obtain the configuration shown in FIG. The configuration thus obtained is again shown in FIG. The subsequent steps are different from those in the first embodiment.

すなわち、図３（ｇ）及び図２６（ａ）に示す構成において、公知のエッチング方法により、導電性プラグ１５の端部を覆う部分のＳｉＯ2膜４１を選択的に除去し、導電性プラグ１５の端部１５ａを露出させる。その結果、図２６（ｂ）に示すように、導電性プラグ１５の端部１５ａがＳｉＯ2膜４１から突出する。残存したＳｉＯ2膜４１は、半導体基板１１の裏面の導電性プラグ１５以外の部分を覆っている。以下、このような構造を持つ第１半導体回路層を１ｂとする。第１実施形態とは異なり、第１半導体回路層１ｂの裏面全体は平坦になっていない。また、露出した各導電性プラグ１５の下端に、マイクロバンプ電極４２は形成されない。 That is, in the configuration shown in FIGS. 3G and 26A, the portion of the SiO 2 film 41 covering the end of the conductive plug 15 is selectively removed by a known etching method, and the conductive plug 15 is removed. The edge part 15a of this is exposed. As a result, the end 15a of the conductive plug 15 protrudes from the SiO 2 film 41 as shown in FIG. The remaining SiO 2 film 41 covers portions other than the conductive plug 15 on the back surface of the semiconductor substrate 11. Hereinafter, the first semiconductor circuit layer having such a structure is referred to as 1b. Unlike the first embodiment, the entire back surface of the first semiconductor circuit layer 1b is not flat. Further, the micro bump electrode 42 is not formed at the lower end of each exposed conductive plug 15.

図３０（ａ）に示すように、各導電性プラグ１５の突出部分の第１半導体回路層１ｂの裏面（ＳｉＯ2膜４１の表面）を基準とした高さは、Ｈｅであり、例えば１μｍとされる。 As shown in FIG. 30A, the height of the protruding portion of each conductive plug 15 with respect to the back surface of the first semiconductor circuit layer 1b (the surface of the SiO 2 film 41) is He, for example, 1 μm. Is done.

次に、第１半導体回路層１ｂの裏面に、以下のようにして、第２半導体回路層２を固着させる。ここでは、第２半導体回路層２は、第１半導体回路層１とほぼ同一の構成を有しており、また第１半導体回路層１と同一の方法で製造されると仮定し、対応する要素には第１半導体回路層１の場合と同一符号を付してその説明を省略する。なお、必要に応じて、第２半導体回路層２を第１半導体回路層１とは異なる構成としてもよいことは言うまでもない。   Next, the second semiconductor circuit layer 2 is fixed to the back surface of the first semiconductor circuit layer 1b as follows. Here, it is assumed that the second semiconductor circuit layer 2 has substantially the same configuration as that of the first semiconductor circuit layer 1 and is manufactured by the same method as that of the first semiconductor circuit layer 1. Are denoted by the same reference numerals as those of the first semiconductor circuit layer 1 and description thereof is omitted. Needless to say, the second semiconductor circuit layer 2 may be configured differently from the first semiconductor circuit layer 1 as necessary.

第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の表面（平坦化されている）には、図２７（ｃ）及び図３０（ａ）に示すように、複数のマイクロバンプ電極４３ａが形成される。これらの電極４３ａは、第１実施形態における第１半導体回路層１ｂのマイクロバンプ電極４２と同一の方法で形成される。ここでは、第１半導体回路層１ｂ（Ｓｉウェハー１１）に設けられた導電性プラグ１５の各々について、４個の電極４３ａが対応している。換言すれば、１個の導電性プラグ１５に対して４個の電極４３ａが接合せしめられるようになっている。   As shown in FIGS. 27 (c) and 30 (a), a plurality of micro bump electrodes are formed on the surface (flattened) of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2. 43a is formed. These electrodes 43a are formed by the same method as the micro bump electrodes 42 of the first semiconductor circuit layer 1b in the first embodiment. Here, four electrodes 43a correspond to each of the conductive plugs 15 provided on the first semiconductor circuit layer 1b (Si wafer 11). In other words, four electrodes 43 a are bonded to one conductive plug 15.

また、導電性プラグ１５と電極４３ａを互いに加圧接触させた時に、電極４３ａのみが選択的に潰れる（塑性変形する）ようにするため、電極４３ａは導電性プラグ１５よりも硬度が十分低い導電性材料から形成されている。例えば、第１実施形態と同様に、電極４２をタングステン（Ｗ）により形成した場合、電極４３ａはインジウム（Ｉｎ）と金（Ａｕ）の積層体（Ｉｎ／Ａｕ）により形成するのが好ましい。また、電極４２を銅（Ｃｕ）により形成した場合は、電極４３ａは錫（Ｓｎ）と銀（Ａｇ）の積層体（Ｓｎ／Ａｇ）により形成するのが好ましい。   Further, when the conductive plug 15 and the electrode 43a are brought into pressure contact with each other, only the electrode 43a is selectively crushed (plastically deformed), so that the electrode 43a has a conductivity sufficiently lower than that of the conductive plug 15. It is formed from a functional material. For example, as in the first embodiment, when the electrode 42 is formed of tungsten (W), the electrode 43a is preferably formed of a laminate (In / Au) of indium (In) and gold (Au). Moreover, when the electrode 42 is formed of copper (Cu), the electrode 43a is preferably formed of a laminate (Sn / Ag) of tin (Sn) and silver (Ag).

次に、第２半導体回路層２の多層配線構造３０（すなわち絶縁材料３１）の表面に、図２７（ｃ）及び図３０（ａ）に示すように、パターン化された電気的絶縁性の接着剤膜４４ａが第１実施形態と同じ方法で形成される。この接着剤膜４４ａは、第１実施形態で用いられたものと同じであって、バンプ状（島状）に形成された多数の接着剤要素４４ａａ（高さはＨａ）から構成されており、それら接着剤要素４４ａａは多層配線構造３０の表面に規則的に分布せしめられている。接着剤膜４４ａは、電極４３ａのいずれとも重ならない形状を持ち、電極４３ａが形成された箇所とその近傍を除いて配置されている。したがって、接着剤膜４４ａ（すなわち、すべての接着剤要素４４ａａ）は、第１半導体回路層１ｂの導電性プラグ１５とも重ならない。   Next, as shown in FIGS. 27 (c) and 30 (a), a patterned electrically insulating adhesive is adhered to the surface of the multilayer wiring structure 30 (that is, the insulating material 31) of the second semiconductor circuit layer 2. The agent film 44a is formed by the same method as in the first embodiment. This adhesive film 44a is the same as that used in the first embodiment, and is composed of a number of adhesive elements 44aa (height Ha) formed in a bump shape (island shape). These adhesive elements 44aa are regularly distributed on the surface of the multilayer wiring structure 30. The adhesive film 44a has a shape that does not overlap any of the electrodes 43a, and is disposed except for the portion where the electrode 43a is formed and the vicinity thereof. Accordingly, the adhesive film 44a (that is, all the adhesive elements 44aa) does not overlap with the conductive plug 15 of the first semiconductor circuit layer 1b.

図３０（ａ）に示すように、第２半導体回路層２の表面を基準とした接着剤要素４４ａａの高さは、Ｈａであり、例えば、４μｍに設定される。   As shown in FIG. 30A, the height of the adhesive element 44aa on the basis of the surface of the second semiconductor circuit layer 2 is Ha, and is set to 4 μm, for example.

接着剤膜４４ａの全体積（硬化後の全体積）は、導電性プラグ１５と電極４３ａを用いて第２半導体回路層２と第１半導体回路層１ｂとを接続した際に、それら二つの回路層１ｂと２の間に生じる隙間全体が接着剤膜４４ａによって充填され、且つその隙間から余分の接着剤膜４４ａがはみ出ないような値に設定される。接着剤膜４４ａは、導電性プラグ１５と電極４３ａがある箇所とその近傍には存在しないので、図３０（ａ）に示すように、各接着剤要素４４ａａの高さＨａ（これは接着剤膜４４ａの厚さに等しい）は、電極４３ａの高さＨｂよりも大きくされており（Ｈａ＞Ｈｂ）、第２半導体回路層２と第１半導体回路層１ｂとを接合した際に各接着剤要素４４ａａが押しつぶされて導電性プラグ１５と電極４３ａがある箇所の周囲まで広がり、回路層１ｂと２の間に生じる隙間全体に充填されやすいようになっている。   The total volume of the adhesive film 44a (the total volume after curing) is determined when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1b are connected using the conductive plug 15 and the electrode 43a. The entire gap formed between the layers 1b and 2 is filled with the adhesive film 44a, and the value is set so that the excess adhesive film 44a does not protrude from the gap. Since the adhesive film 44a does not exist in the vicinity of the conductive plug 15 and the electrode 43a and in the vicinity thereof, as shown in FIG. 30A, the height Ha of each adhesive element 44aa (this is the adhesive film 44a is equal to the height Hb of the electrode 43a (Ha> Hb), and each adhesive element is bonded to the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1b. 44aa is crushed and spreads around the place where the conductive plug 15 and the electrode 43a are present, so that the entire gap formed between the circuit layers 1b and 2 can be easily filled.

第２半導体回路層２の表面を基準とした電極４３ａの高さＨｂの典型例は、例えば、２μｍである。   A typical example of the height Hb of the electrode 43a with respect to the surface of the second semiconductor circuit layer 2 is 2 μm, for example.

接着剤膜４４ａが多数の接着剤要素４４ａａに分けられているのは、第２半導体回路層２と第１半導体回路層１ｂとを接合する際に、両回路層２、１ｂの間に存在する空気を外部に逃がしやすくするため（つまり脱ガスの容易化のため）である。すなわち、回路層２と１ｂがほとんど接続された状態でも、両層２、１ｂの間に存在する空気が隣接する接着剤要素４４ａａの間の隙間を通って外部に押し出されるようにするためである。   The adhesive film 44a is divided into a large number of adhesive elements 44aa when the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1b are bonded to each other between the circuit layers 2 and 1b. This is to facilitate the escape of air to the outside (that is, to facilitate degassing). That is, even when the circuit layers 2 and 1b are almost connected, the air existing between the layers 2 and 1b is pushed out through the gap between the adjacent adhesive elements 44aa. .

ここでは、マイクロバンプ電極４３ａを形成してから接着剤膜４４ａを形成しているが、接着剤膜４４ａを形成してからマイクロバンプ電極４３ａを形成してもよい。   Here, the adhesive film 44a is formed after the microbump electrode 43a is formed, but the microbump electrode 43a may be formed after the adhesive film 44a is formed.

続いて、図２７（ａ）及び図３０（ａ）に示すように、支持基板４０を介して固定された第１半導体回路層１ｂの裏面に、下方から第２半導体回路層２の表面を対向させる。（逆に、第２半導体回路層２を固定しておき、上方から支持基板４０に固定された第１半導体回路層１ｂを対向させてもよい。）その後、回路層２と１ｂの間に押圧力を加えて回路層２と１ｂを相互に近接させると、各接着剤要素４４ａａの高さ（接着剤膜４４ａの厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きく（Ｈａ＞Ｈｂ）、且つ導電性プラグ１５の突出高さＨｅと電極４３ａの高さＨｂの和より大きい（Ｈａ＞Ｈｂ＋Ｈｅ）ため、最初に、図３０（ｂ）に示すように、第２半導体回路層２の接着剤膜４４ａ（接着剤要素４４ａａ）の先端（頂部）が第１半導体回路層１ｂの裏面に接触せしめられる。   Subsequently, as shown in FIGS. 27A and 30A, the surface of the second semiconductor circuit layer 2 is opposed to the back surface of the first semiconductor circuit layer 1b fixed through the support substrate 40 from below. Let (Conversely, the second semiconductor circuit layer 2 may be fixed and the first semiconductor circuit layer 1b fixed to the support substrate 40 may be opposed from above.) Thereafter, the second semiconductor circuit layer 2 is pushed between the circuit layers 2 and 1b. When pressure is applied to bring the circuit layers 2 and 1b close to each other, the height of each adhesive element 44aa (the thickness of the adhesive film 44a) Ha is larger than the height Hb of the electrode 43a (Ha> Hb). And larger than the sum of the protruding height He of the conductive plug 15 and the height Hb of the electrode 43a (Ha> Hb + He), first, as shown in FIG. 30B, the second semiconductor circuit layer 2 is bonded. The tip (top) of the agent film 44a (adhesive element 44aa) is brought into contact with the back surface of the first semiconductor circuit layer 1b.

その後、回路層２と１ｂの間に押圧力を加えて両者間の距離を狭めることにより、図２８（ｄ）及び図３１（ｃ）に示すように、第２半導体回路層２の各電極４３ａを対応する第１半導体回路層１ｂの電極４２に接触させる。この時の第１半導体回路層１ｂの裏面と第２半導体回路層２の表面との距離すなわち層間ギャップＧ１は、導電性プラグ１５の突出高さと電極４３ａの高さの和に等しい、すなわちＧ１＝Ｈｅ＋Ｈｂである。この時、接着剤膜４４ａは押し潰されて変形し、回路層１ｂと２の間の隙間のほぼ全体に押し広げられるが、接着剤膜４４ａは島状の接着剤要素４４ａａに分割されているので、接着剤膜４４ａは当該隙間中にほぼ均一に広がる。また、第１半導体回路層１ｂの裏面と変形せしめられた接着剤膜４４ａとの間（と隣接する接着剤要素４４ａａの間）には、空隙４５が形成されやすいことから、当該隙間中に残存する空気が空隙４５を通って外部に確実に排出されることができ、最終的に一体化・硬化せしめられた接着剤膜４４ａ中に気泡が生じる恐れをなくすことができる。   Thereafter, a pressing force is applied between the circuit layers 2 and 1b to reduce the distance between the two, and as shown in FIGS. 28D and 31C, each electrode 43a of the second semiconductor circuit layer 2 is obtained. Is brought into contact with the electrode 42 of the corresponding first semiconductor circuit layer 1b. At this time, the distance between the back surface of the first semiconductor circuit layer 1b and the surface of the second semiconductor circuit layer 2, that is, the interlayer gap G1, is equal to the sum of the protruding height of the conductive plug 15 and the height of the electrode 43a, that is, G1 = He + Hb. At this time, the adhesive film 44a is crushed and deformed to be spread over almost the entire gap between the circuit layers 1b and 2, but the adhesive film 44a is divided into island-shaped adhesive elements 44aa. Therefore, the adhesive film 44a spreads almost uniformly in the gap. Further, since a gap 45 is easily formed between the back surface of the first semiconductor circuit layer 1b and the deformed adhesive film 44a (and between the adjacent adhesive elements 44aa), it remains in the gap. The air to be discharged can be surely discharged to the outside through the gap 45, and the risk of bubbles being generated in the finally integrated and cured adhesive film 44a can be eliminated.

上述した第１半導体回路層１ｂと第２半導体回路層２とを対向させてから導電性プラグ１５と電極４３ａとを相互接触させる工程は、第１実施形態と同様に、室温で行う。第１半導体回路層１ｂと第２半導体回路層２との距離Ｇ１の値は、例えば２μｍ〜１０μｍの範囲で適宜決定されるが、典型的には４μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、２μｍ以下とすることも可能である。この場合、距離Ｇ１の値は、例えば０．１μｍ〜２μｍの範囲で適宜決定される。この点も第１実施形態と同様である。   The step of making the conductive plug 15 and the electrode 43a contact each other after the first semiconductor circuit layer 1b and the second semiconductor circuit layer 2 are opposed to each other is performed at room temperature, as in the first embodiment. The value of the distance G1 between the first semiconductor circuit layer 1b and the second semiconductor circuit layer 2 is appropriately determined within a range of 2 μm to 10 μm, for example, and is typically 4 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 2 μm or less. In this case, the value of the distance G1 is appropriately determined within a range of 0.1 μm to 2 μm, for example. This is also the same as in the first embodiment.

その後、互いに接触せしめられた電極４３ａと電極４２を、以下のようにして相互に接続させる。   Thereafter, the electrodes 43a and 42 brought into contact with each other are connected to each other as follows.

すなわち、図２８（ｄ）及び図３０（ｂ）の状態にある第２半導体回路層２と第１半導体回路層１ｂを室温から所定温度まで加熱する。その温度は、加圧変形状態にある接着剤膜４４ａの表面（露出面）がわずかに軟化するか、その表面がわずかに流動状態になる温度に設定する。その温度は、接着剤膜４４ａに使用する接着剤の種類によって異なるが、導電性プラグ１５と電極４３ａとが「圧接」する温度を考慮しながら、例えば１００〜４００℃の範囲内で任意に設定される。このとき、設定する加熱温度によっては、電極４３ａが部分的に溶融状態となり、その表面が湾曲することがある。   That is, the second semiconductor circuit layer 2 and the first semiconductor circuit layer 1b in the states of FIG. 28D and FIG. 30B are heated from room temperature to a predetermined temperature. The temperature is set to a temperature at which the surface (exposed surface) of the adhesive film 44a in a pressure-deformed state is slightly softened or the surface is slightly fluidized. The temperature varies depending on the type of adhesive used for the adhesive film 44a, but is arbitrarily set within a range of, for example, 100 to 400 ° C. in consideration of the temperature at which the conductive plug 15 and the electrode 43a are “press-contacted”. Is done. At this time, depending on the heating temperature to be set, the electrode 43a may be partially melted and the surface may be curved.

続いて、押圧力を印加することにより、第１半導体回路層１ｂに対して下方から第２半導体回路層２をさらに近づけ、あるいは第２半導体回路層２に対して上方から第１半導体回路層１ｂを下降させることにより、図２９（ｅ）及び図３１（ｄ）に示すように、回路層１ｂと２の間の隙間を狭める。換言すれば、回路層１ｂと２の間の層間ギャップをＧ１からそれより小さいＧ２（Ｇ２＜Ｇ１）とする。この時、第２半導体回路層２の電極４３ａと第１半導体回路層１ｂの導電性プラグ１５の間には、圧縮力が作用する。その結果、導電性プラグ１５よりも機械的強度が低い電極４３ａのみが選択的に押し潰されて、導電性プラグ１５と電極４３とが「圧接」によって相互に接合せしめられると共に、接着剤要素４４ａａがさらに押し広げられて相互に連結・一体化される。このとき、１個の導電性プラグ１５に対応する４個の電極４３ａが潰されて一体的になり、その結果、導電性プラグ１５と電極４３ａとが一対一対応になる。こうして、相互に圧接された電極４３ａと導電性プラグ１５の箇所を除いて、回路層２と１ｂの間の隙間の全体が接着剤膜４４ａによって充填され、余分の接着剤膜４４ｂ１または４４ｂ２が当該隙間からはみ出ることもない。この時の状態は図２９（ｅ）及び図３１（ｄ）に示すようになる。   Subsequently, by applying a pressing force, the second semiconductor circuit layer 2 is brought closer to the first semiconductor circuit layer 1b from below, or the first semiconductor circuit layer 1b is viewed from above with respect to the second semiconductor circuit layer 2. As shown in FIGS. 29 (e) and 31 (d), the gap between the circuit layers 1b and 2 is narrowed. In other words, the interlayer gap between the circuit layers 1b and 2 is set to G2 smaller than G1 (G2 <G1). At this time, a compressive force acts between the electrode 43a of the second semiconductor circuit layer 2 and the conductive plug 15 of the first semiconductor circuit layer 1b. As a result, only the electrode 43a having a mechanical strength lower than that of the conductive plug 15 is selectively crushed so that the conductive plug 15 and the electrode 43 are joined to each other by “pressure contact” and the adhesive element 44aa. Are further expanded and connected and integrated with each other. At this time, the four electrodes 43a corresponding to one conductive plug 15 are crushed and integrated, and as a result, the conductive plug 15 and the electrode 43a have a one-to-one correspondence. In this way, the entire gap between the circuit layers 2 and 1b is filled with the adhesive film 44a except for the electrode 43a and the conductive plug 15 that are in pressure contact with each other, and the extra adhesive film 44b1 or 44b2 is filled with the adhesive film 44a. It does not protrude from the gap. The state at this time is as shown in FIGS. 29 (e) and 31 (d).

この加熱圧接工程では、層間ギャップがＧ１からＧ２に減少せしめられる際に、回路層１ａと２の間の隙間に存在する空気（大気）は、第１半導体回路層１ｂの裏面と接着剤膜４４ａ（これらはいずれも加熱によって表面が軟化または流動化している）との間の空隙４５と、隣接する接着剤要素４４ａａの間に残存する微小空間とを通って、外部に確実に排出されることができる。また、接着剤膜４４ａの表面が軟化または流動化しているので、層間ギャップがＧ２になった時に、第１半導体回路層１ｂの裏面と接着剤膜４４ａが接着されやすく、その結果、回路層１ｂと２が確実に相互接着されることができる。   In this heating and pressure welding process, when the interlayer gap is reduced from G1 to G2, the air (atmosphere) existing in the gap between the circuit layers 1a and 2 is removed from the back surface of the first semiconductor circuit layer 1b and the adhesive film 44a. (All of which are softened or fluidized by heating) and the minute space remaining between the adjacent adhesive elements 44aa and reliably discharged to the outside. Can do. Further, since the surface of the adhesive film 44a is softened or fluidized, when the interlayer gap becomes G2, the back surface of the first semiconductor circuit layer 1b and the adhesive film 44a are easily bonded, and as a result, the circuit layer 1b. And 2 can be securely bonded to each other.

加熱時に電極４３ａが部分的に溶融状態となった場合は、導電性プラグ１５と電極４３ａの接合は、溶融した電極４３ａの「再凝固」により行われるか、「圧接」と「再凝固」が混合した形で行われる。この点は第１実施形態と同様である。   When the electrode 43a is partially melted during heating, the conductive plug 15 and the electrode 43a are joined by “re-solidification” of the molten electrode 43a, or “pressure welding” and “re-solidification” are performed. It is done in a mixed form. This is the same as in the first embodiment.

層間ギャップＧ２の値は、例えば１μｍ〜９μｍの範囲で適宜決定されるが、典型的には３μｍである。しかし、電極４２と４３ａの高さＨｃとＨｂをいっそう小さくすることにより、１μｍ以下とすることも可能である。この場合、距離Ｇ２の値は、例えば０．０５μｍ〜１μｍの範囲で適宜決定される。   The value of the interlayer gap G2 is appropriately determined within a range of 1 μm to 9 μm, for example, but is typically 3 μm. However, the heights Hc and Hb of the electrodes 42 and 43a can be further reduced to 1 μm or less. In this case, the value of the distance G2 is appropriately determined in the range of 0.05 μm to 1 μm, for example.

第２半導体回路層２は、以上のようにして、導電性プラグ１５と電極４３ａを用いて第１半導体回路層１ｂの裏面側に固着（つまり機械的に接続）せしめられると共に、両回路層１ｂ及び２の間の電気的接続も同時に行われる。また、それと同時に、両回路層１ｂ及び２は、互いに接続された導電性プラグ１５及び電極４３ａの箇所を除いて回路層１ｂと２の間の隙間全体に充填された接着剤膜４４ａによって、相互に接着される。   As described above, the second semiconductor circuit layer 2 is fixed (that is, mechanically connected) to the back surface side of the first semiconductor circuit layer 1b using the conductive plug 15 and the electrode 43a, and both the circuit layers 1b. And the electrical connection between the two. At the same time, both circuit layers 1b and 2 are mutually connected by an adhesive film 44a filled in the entire gap between the circuit layers 1b and 2 except for the conductive plug 15 and the electrode 43a connected to each other. Glued to.

以上のようにして導電性プラグ１５と電極４３ａの機械的・電気的接続と接着剤膜４４ａの接着が終わると、相互に接合された回路層１ｂと２は室温まで自然冷却される。そこで、加熱、紫外線照射、薬剤添加等によって一体化された接着剤膜４４ａを最終的に硬化させる。処理が容易であることから、加熱により硬化させるのが好ましい。加熱温度は、接着剤膜４４ａとして使用した接着剤の性質に応じて、例えば１２０〜５００℃の範囲内で適宜設定される。こうして、二つの半導体回路層１ｂと２の間の機械的接続と電気的接続が完了する。   When the mechanical and electrical connection between the conductive plug 15 and the electrode 43a and the bonding of the adhesive film 44a are completed as described above, the circuit layers 1b and 2 bonded to each other are naturally cooled to room temperature. Therefore, the integrated adhesive film 44a is finally cured by heating, ultraviolet irradiation, chemical addition, or the like. Since treatment is easy, it is preferable to cure by heating. The heating temperature is appropriately set within a range of 120 to 500 ° C., for example, depending on the properties of the adhesive used as the adhesive film 44a. Thus, the mechanical connection and electrical connection between the two semiconductor circuit layers 1b and 2 are completed.

その後の工程は、第１実施形態の場合と同じであるから、その説明は省略する。   Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

以上説明したように、本発明の第５実施形態に係る集積回路装置の製造方法は、第１半導体回路層１ｂと第２半導体回路層２の接合を導電性プラグ１５（電極４２は使用しない）と電極４３ａを用いて行う点を除いて、上述した第１実施形態に係る集積回路装置の製造方法と同じであるから、第１実施形態において得られるものと同一の効果が得られることは明らかである。また、第５実施形態では、電極４２を形成する工程が不要なので、第１実施形態におけるよりも工程が少し簡単になる、という利点がある。   As described above, in the method of manufacturing an integrated circuit device according to the fifth embodiment of the present invention, the conductive plug 15 (the electrode 42 is not used) is used to join the first semiconductor circuit layer 1b and the second semiconductor circuit layer 2. And the electrode 43a are the same as the method for manufacturing the integrated circuit device according to the first embodiment described above, and it is clear that the same effect as that obtained in the first embodiment can be obtained. It is. Further, in the fifth embodiment, since the process of forming the electrode 42 is unnecessary, there is an advantage that the process is a little simpler than in the first embodiment.

（第６実施形態）
図３３は、本発明の第６実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第６実施形態は、上述した第１実施形態の変形例１に相当する。 (Sixth embodiment)
FIG. 33 is a partial enlarged cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional laminated structure according to the sixth embodiment of the present invention. The sixth embodiment corresponds to Modification 1 of the first embodiment described above.

上記第１実施形態では、図９（ａ）に示すように、島状の接着剤要素４４ａａの高さ（接着剤膜４４ａの厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きく設定され（Ｈａ＞Ｈｂ）、且つ電極４２の高さＨｃと電極４３ａの高さＨｂの和よりも大きく設定されている（Ｈａ＞Ｈｂ＋Ｈｃ）。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、接着剤膜４４ａが第１半導体回路層１ａに先に接触して変形せしめられ、その後で電極４２と４３ａが相互に接触する。しかし、本発明はこのような関係に限定されるわけではない。   In the first embodiment, as shown in FIG. 9A, the height of the island-shaped adhesive element 44aa (the thickness of the adhesive film 44a) Ha is set larger than the height Hb of the electrode 43a. (Ha> Hb) and larger than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a (Ha> Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive film 44a is first brought into contact with the first semiconductor circuit layer 1a and deformed, and then the electrodes 42 and 43a are mutually connected. To touch. However, the present invention is not limited to such a relationship.

ここで述べる第６実施形態に係る集積回路装置の製造方法では、図３３（ａ）に示すように、島状の接着剤要素４４ａａの高さ（接着剤膜４４ａの厚さ）Ｈａが、電極４３ａの高さＨｂよりも大きく設定されている（Ｈａ＞Ｈｂ）点は、上記第１実施形態と同じであるが、電極４２の高さＨｃと電極４３ａの高さＨｂの和よりも小さく設定されている（Ｈａ＜Ｈｂ＋Ｈｃ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、図３３（ｂ）に示すように、まず電極４２と４３ａが相互に接触し、その後に、加圧による電極４３ａの変形に伴って、接着剤膜４４ａが第１半導体回路層１ａに接触して変形せしめられる。それ以外の点は上記第１実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the sixth embodiment described here, as shown in FIG. 33A, the height of the island-shaped adhesive element 44aa (the thickness of the adhesive film 44a) Ha is the electrode. The point set larger than the height Hb of 43a (Ha> Hb) is the same as in the first embodiment, but is set smaller than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a. (Ha <Hb + Hc) is different. For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, as shown in FIG. 33 (b), the electrodes 42 and 43a are first brought into contact with each other, and then the electrode 43a by pressurization is applied. With the deformation, the adhesive film 44a comes into contact with the first semiconductor circuit layer 1a and is deformed. The other points are the same as in the first embodiment.

したがって、第６実施形態に係る集積回路装置の製造方法においても、上記第１実施形態と同様の効果が得られることは明らかである。   Therefore, it is obvious that the same effect as that of the first embodiment can be obtained in the method of manufacturing an integrated circuit device according to the sixth embodiment.

（第７実施形態）
図３４は、本発明の第７実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第７実施形態は、上述した第１実施形態の変形例２に相当する。 (Seventh embodiment)
FIG. 34 is a partial enlarged cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional laminated structure according to the seventh embodiment of the present invention. The seventh embodiment corresponds to Modification 2 of the first embodiment described above.

ここで述べる第７実施形態に係る集積回路装置の製造方法では、図３４（ａ）に示すように、島状の接着剤要素４４ａａの高さ（接着剤膜４４ａの厚さ）Ｈａが、電極４３ａの高さＨｂよりも小さく設定されている（Ｈａ＜Ｈｂ）点で、上記第１実施形態とは異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、図３４（ｂ）に示すように、まず電極４２と４３ａが相互に接触し、その後に、加圧による電極４３ａの変形に伴って、接着剤膜４４ａが第１半導体回路層１ａに接触して変形せしめられる。また、電極４３ａの変形量が、第６実施形態よりも大きくなる。それ以外の点は上記第１実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the seventh embodiment described here, as shown in FIG. 34A, the height of the island-like adhesive element 44aa (the thickness of the adhesive film 44a) Ha is the electrode. It differs from the said 1st Embodiment by the point set smaller than the height Hb of 43a (Ha <Hb). For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, as shown in FIG. 34 (b), the electrodes 42 and 43a are first brought into contact with each other, and thereafter, the electrode 43a by pressure is applied. With the deformation, the adhesive film 44a comes into contact with the first semiconductor circuit layer 1a and is deformed. Further, the deformation amount of the electrode 43a is larger than that in the sixth embodiment. The other points are the same as in the first embodiment.

第７実施形態では、第１半導体回路層１ａと第２半導体回路層２の間の隙間に接着剤膜４４ａが充填されるようにするため、電極４３ａの変形量を大きくする必要がある。そこで、電極４３ａと共に電極４２も塑性変形するように構成するのが好ましい。   In the seventh embodiment, it is necessary to increase the amount of deformation of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive film 44a. Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

第７実施形態に係る集積回路装置の製造方法においても、上記第１実施形態と同様の効果が得られることは明らかである。   It is clear that the same effect as that of the first embodiment can be obtained in the method of manufacturing an integrated circuit device according to the seventh embodiment.

（第８実施形態）
図３５は、本発明の第８実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第８実施形態は、上述した第１実施形態の変形例３に相当する。 (Eighth embodiment)
FIG. 35 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the eighth embodiment of the present invention. The eighth embodiment corresponds to Modification 3 of the first embodiment described above.

ここで述べる第８実施形態に係る集積回路装置の製造方法では、図３５（ａ）に示すように、島状の接着剤要素４４ａａの高さ（接着剤膜４４ａの厚さ）Ｈａが、電極４３ａの高さＨｂよりも大きく設定されている（Ｈａ＞Ｈｂ）点は、上記第１実施形態と同じであるが、電極４２の高さＨｃと電極４３ａの高さＨｂの和にほぼ等しく設定されている（Ｈａ≒Ｈｂ＋Ｈｃ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、電極４２と４３ａが相互に接触するのとほぼ同時に、接着剤膜４４ａが第１半導体回路層１ａの裏面に接触する。それ以外の点は上記第１実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the eighth embodiment described here, as shown in FIG. 35A, the height of the island-shaped adhesive element 44aa (the thickness of the adhesive film 44a) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as in the first embodiment, but is set substantially equal to the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a. (Ha≈Hb + Hc) is different. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive film 44a contacts the back surface of the first semiconductor circuit layer 1a almost simultaneously with the electrodes 42 and 43a contacting each other. To do. The other points are the same as in the first embodiment.

したがって、第８実施形態に係る集積回路装置の製造方法においても、上記第１実施形態と同様の効果が得られることは明らかである。   Therefore, it is obvious that the same effect as that of the first embodiment can be obtained in the method of manufacturing an integrated circuit device according to the eighth embodiment.

（第９実施形態）
図３６は、本発明の第９実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第９実施形態は、上述した第２実施形態の変形例１に相当する。 (Ninth embodiment)
FIG. 36 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the ninth embodiment of the present invention. The ninth embodiment corresponds to Modification 1 of the second embodiment described above.

上記第２実施形態では、図１４（ａ）に示すように、島状の接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きく設定され（Ｈａ＞Ｈｂ）、島状の接着剤要素４４ｂｂ１の高さ（接着剤膜４４ｂ１の厚さ）Ｈｄは、電極４２の高さＨｃよりも大きく設定されている（Ｈｃ＜Ｈｄ）。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、先に接着剤膜４４ｂ１及び４４ｂ２が相互に接触して変形せしめられ、その後で電極４２と４３ａが相互に接触する。しかし、本発明はこのような関係に限定されるわけではない。   In the second embodiment, as shown in FIG. 14A, the height (the thickness of the adhesive film 44b2) Ha of the island-shaped adhesive element 44bb2 is set larger than the height Hb of the electrode 43a. (Ha> Hb), the height (the thickness of the adhesive film 44b1) Hd of the island-shaped adhesive element 44bb1 is set to be larger than the height Hc of the electrode 42 (Hc <Hd). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are first brought into contact with each other and deformed, and then the electrodes 42 and 43a are brought into contact with each other. . However, the present invention is not limited to such a relationship.

ここで述べる第９実施形態に係る集積回路装置の製造方法では、図３６（ａ）に示すように、島状の接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａが、電極４３ａの高さＨｂよりも大きく設定されている（Ｈａ＞Ｈｂ）点は、上記第２実施形態と同じであるが、島状の接着剤要素４４ｂｂ１の高さ（接着剤膜４４ｂ１の厚さ）Ｈｄが、電極４２の高さＨｃよりも小さく設定されており（Ｈｃ＞Ｈｄ）、且つ、接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａと接着剤要素４４ｂｂ１の高さ（接着剤膜４４ｂ１の厚さ）Ｈｄの和が、電極４２の高さＨｃと電極４３ａの高さＨｂの和よりも大きく設定されている（Ｈａ＋Ｈｄ＞Ｈｂ＋Ｈｃ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず接着剤膜４４ｂ１と４４ｂ２が相互に接触し、その後、電極４２と４３ａが相互に接触する。それ以外の点は上記第２実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the ninth embodiment described here, as shown in FIG. 36A, the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as that of the second embodiment, but the height of the island-shaped adhesive element 44bb1 (the thickness of the adhesive film 44b1). Hd is set smaller than the height Hc of the electrode 42 (Hc> Hd), and the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha and the height of the adhesive element 44bb1 ( The difference is that the sum of the thickness Hd of the adhesive film 44b1) is set to be larger than the sum of the height Hc of the electrode 42 and the height Hb of the electrode 43a (Ha + Hd> Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are first in contact with each other, and then the electrodes 42 and 43a are in contact with each other. The other points are the same as in the second embodiment.

したがって、第９実施形態に係る集積回路装置の製造方法においても、上記第２実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effect as that of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the ninth embodiment.

（第１０実施形態）
図３７は、本発明の第１０実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１０実施形態は、上述した第２実施形態の変形例２に相当する。 (10th Embodiment)
FIG. 37 is a partial enlarged cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to the tenth embodiment of the present invention. The tenth embodiment corresponds to the second modification of the second embodiment described above.

ここで述べる第９実施形態に係る集積回路装置の製造方法では、図３７（ａ）に示すように、島状の接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａが、電極４３ａの高さＨｂよりも大きく設定されている（Ｈａ＞Ｈｂ）点は、上記第２実施形態と同じであるが、島状の接着剤要素４４ｂｂ１の高さ（接着剤膜４４ｂ１の厚さ）Ｈｄが、電極４２の高さＨｃよりも小さく設定されており（Ｈｃ＞Ｈｄ）、且つ、接着剤要素４４ｂｂ２の高さＨａと接着剤要素４４ｂｂ１の高さＨｄの和が、電極４２の高さＨｃと電極４３ａの高さＨｂの和よりも小さく設定されている（Ｈａ＋Ｈｄ＜Ｈｂ＋Ｈｃ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず電極４２と４３ａが相互に接触し、その後、接着剤膜４４ｂ１と４４ｂ２が相互に接触する。それ以外の点は上記第２実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the ninth embodiment described here, as shown in FIG. 37A, the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as that of the second embodiment, but the height of the island-shaped adhesive element 44bb1 (the thickness of the adhesive film 44b1). Hd is set smaller than the height Hc of the electrode 42 (Hc> Hd), and the sum of the height Ha of the adhesive element 44bb2 and the height Hd of the adhesive element 44bb1 is the height of the electrode 42. The difference is that it is set smaller than the sum of Hc and the height Hb of the electrode 43a (Ha + Hd <Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the second embodiment.

したがって、第１０実施形態に係る集積回路装置の製造方法においても、上記第２実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effect as that of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the tenth embodiment.

第１０実施形態では、第１半導体回路層１ａと第２半導体回路層２の間の隙間に接着剤膜４４ｂ１及び４４ｂ２が充填されるようにするため、電極４３ａの変形量を大きくする必要がある。そこで、電極４３ａと共に電極４２も塑性変形するように構成するのが好ましい。   In the tenth embodiment, it is necessary to increase the amount of deformation of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive films 44b1 and 44b2. . Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

（第１１実施形態）
図３８は、本発明の第１１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１１実施形態は、上述した第２実施形態の変形例３に相当する。 (Eleventh embodiment)
FIG. 38 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the eleventh embodiment of the present invention. The eleventh embodiment corresponds to the third modification of the second embodiment described above.

ここで述べる第１１実施形態に係る集積回路装置の製造方法では、図３８（ａ）に示すように、島状の接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａが、電極４３ａの高さＨｂよりも小さく設定され（Ｈａ＜Ｈｂ）、島状の接着剤要素４４ｂｂ１の高さ（接着剤膜４４ｂ１の厚さ）Ｈｄが、電極４２の高さＨｃよりも小さく設定されている（Ｈｃ＞Ｈｄ）点が、第２実施形態とは異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず電極４２と４３ａが相互に接触し、その後、接着剤膜４４ｂ１と４４ｂ２が相互に接触する。それ以外の点は上記第２実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the eleventh embodiment described here, as shown in FIG. 38A, the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the electrode. 43a is set smaller than the height Hb (Ha <Hb), and the island-shaped adhesive element 44bb1 height (the thickness of the adhesive film 44b1) Hd is set smaller than the height Hc of the electrode 42. (Hc> Hd) is different from the second embodiment. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the second embodiment.

したがって、第１１実施形態に係る集積回路装置の製造方法においても、上記第２実施形態と同様の効果が得られることは明らかである。   Therefore, it is obvious that the same effects as those of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the eleventh embodiment.

（第１２実施形態）
図３９は、本発明の第１２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１２実施形態は、上述した第２実施形態の変形例４に相当する。 (Twelfth embodiment)
FIG. 39 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twelfth embodiment of the present invention. The twelfth embodiment corresponds to Modification 4 of the second embodiment described above.

ここで述べる第１２実施形態に係る集積回路装置の製造方法では、図３９（ａ）に示すように、島状の接着剤要素４４ｂｂ１の高さ（接着剤膜４４ｂ１の厚さ）Ｈｄが、電極４２の高さＨｃよりも大さく設定されている（Ｈｃ＜Ｈｄ）点は、第２実施形態と同じであるが、島状の接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａが、電極４３ａの高さＨｂよりも小さく設定され（Ｈａ＜Ｈｂ）、且つ、接着剤要素４４ｂｂ２の高さＨａと接着剤要素４４ｂｂ１の高さＨｄの和が、電極４２の高さＨｃと電極４３ａの高さＨｂの和よりも大きく設定されている（Ｈａ＋Ｈｄ＞Ｈｂ＋Ｈｃ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず接着剤膜４４ｂ１と４４ｂ２が相互に接触し、その後、電極４２と４３ａが相互に接触する。それ以外の点は上記第２実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the twelfth embodiment described here, as shown in FIG. 39A, the height of the island-like adhesive element 44bb1 (the thickness of the adhesive film 44b1) Hd is The point set larger than the height Hc of 42 (Hc <Hd) is the same as in the second embodiment, but the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2). Ha is set smaller than the height Hb of the electrode 43a (Ha <Hb), and the sum of the height Ha of the adhesive element 44bb2 and the height Hd of the adhesive element 44bb1 is equal to the height Hc of the electrode 42. The difference is that it is set larger than the sum of the heights Hb of the electrodes 43a (Ha + Hd> Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are first in contact with each other, and then the electrodes 42 and 43a are in contact with each other. The other points are the same as in the second embodiment.

したがって、第１２実施形態に係る集積回路装置の製造方法においても、上記第２実施形態と同様の効果が得られることは明らかである。   Therefore, it is obvious that the same effects as those of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the twelfth embodiment.

（第１３実施形態）
図４０は、本発明の第１３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１３実施形態は、上述した第２実施形態の変形例５に相当する。 (13th Embodiment)
FIG. 40 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the thirteenth embodiment of the present invention. The thirteenth embodiment corresponds to Modification 5 of the second embodiment described above.

ここで述べる第１３実施形態に係る集積回路装置の製造方法では、図４０（ａ）に示すように、島状の接着剤要素４４ｂｂ１の高さ（接着剤膜４４ｂ１の厚さ）Ｈｄが、電極４２の高さＨｃよりも大さく設定されている（Ｈｃ＜Ｈｄ）点は、第２実施形態と同じであるが、島状の接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａが、電極４３ａの高さＨｂよりも小さく設定されており（Ｈａ＜Ｈｂ）、且つ、接着剤要素４４ｂｂ２の高さＨａと接着剤要素４４ｂｂ１の高さＨｄの和が、電極４２の高さＨｃと電極４３ａの高さＨｂの和よりも小さく設定されている（Ｈａ＋Ｈｄ＜Ｈｂ＋Ｈｃ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず電極４２と４３ａが相互に接触し、その後、接着剤膜４４ｂ１と４４ｂ２が相互に接触する。それ以外の点は上記第２実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the thirteenth embodiment described here, as shown in FIG. 40A, the height of the island-like adhesive element 44bb1 (the thickness of the adhesive film 44b1) Hd is The point set larger than the height Hc of 42 (Hc <Hd) is the same as in the second embodiment, but the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2). Ha is set smaller than the height Hb of the electrode 43a (Ha <Hb), and the sum of the height Ha of the adhesive element 44bb2 and the height Hd of the adhesive element 44bb1 is the height of the electrode 42. The difference is that it is set smaller than the sum of Hc and the height Hb of the electrode 43a (Ha + Hd <Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the second embodiment.

したがって、第１３実施形態に係る集積回路装置の製造方法においても、上記第２実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effect as that of the second embodiment can be obtained in the method of manufacturing an integrated circuit device according to the thirteenth embodiment.

第１３実施形態では、第１半導体回路層１ａと第２半導体回路層２の間の隙間に接着剤膜４４ｂ１及び４４ｂ２が充填されるようにするため、電極４３ａの変形量を大きくする必要がある。そこで、電極４３ａと共に電極４２も塑性変形するように構成するのが好ましい。   In the thirteenth embodiment, it is necessary to increase the deformation amount of the electrode 43a so that the adhesive films 44b1 and 44b2 are filled in the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2. . Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

（第１４実施形態）
図４１は、本発明の第１４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１４実施形態は、上述した第２実施形態の変形例６に相当する。 (14th Embodiment)
FIG. 41 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fourteenth embodiment of the present invention. The fourteenth embodiment corresponds to Modification 6 of the second embodiment described above.

ここで述べる第１４実施形態に係る集積回路装置の製造方法では、図４１（ａ）に示すように、島状の接着剤要素４４ｂｂ１の高さ（接着剤膜４４ｂ１の厚さ）Ｈｄが、電極４２の高さＨｃよりも大さく設定されている（Ｈｃ＜Ｈｄ）点は、第２実施形態と同じであるが、島状の接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａが、電極４３ａの高さＨｂよりも小さく設定されており（Ｈａ＜Ｈｂ）、且つ、接着剤要素４４ｂｂ２の高さＨａと接着剤要素４４ｂｂ１の高さＨｄの和が、電極４２の高さＨｃと電極４３ａの高さＨｂの和とほぼ等しく設定されている（Ｈａ＋Ｈｄ≒Ｈｂ＋Ｈｃ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、電極４２と４３ａが相互に接触するのとほぼ同時に、接着剤膜４４ｂ１と４４ｂ２が相互に接触する。それ以外の点は上記第２実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the fourteenth embodiment described here, as shown in FIG. 41A, the height of the island-shaped adhesive element 44bb1 (the thickness of the adhesive film 44b1) Hd is The point set larger than the height Hc of 42 (Hc <Hd) is the same as in the second embodiment, but the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2). Ha is set smaller than the height Hb of the electrode 43a (Ha <Hb), and the sum of the height Ha of the adhesive element 44bb2 and the height Hd of the adhesive element 44bb1 is the height of the electrode 42. The difference is that it is set to be substantially equal to the sum of Hc and the height Hb of the electrode 43a (Ha + Hd≈Hb + Hc). For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are in contact with each other almost simultaneously with the electrodes 42 and 43a being in contact with each other. The other points are the same as in the second embodiment.

したがって、第１４実施形態に係る集積回路装置の製造方法においても、上記第２実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effects as those of the second embodiment can be obtained also in the integrated circuit device manufacturing method according to the fourteenth embodiment.

（第１５実施形態）
図４２は、本発明の第１５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１５実施形態は、上述した第３実施形態の変形例１に相当する。 (Fifteenth embodiment)
FIG. 42 is a partial enlarged cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fifteenth embodiment of the present invention. The fifteenth embodiment corresponds to the first modification of the third embodiment described above.

上記第３実施形態では、図１９（ａ）に示すように、島状の接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きく設定され（Ｈａ＞Ｈｂ）、連続的な接着剤膜４４ｃの厚さＨｄは、電極４２の高さＨｃよりも小さく設定され（Ｈｃ＞Ｈｄ）、さらに、接着剤要素４４ｂｂ２の高さＨａと接着剤膜４４ｃの厚さＨｄの和が、電極４３ａの高さＨｂと電極の高さＨＣの和よりも大きく設定されている（Ｈａ＋Ｈｄ＞Ｈｂ＋Ｈｃ）。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、先に接着剤膜４４ｃ及び４４ｂ２が相互に接触して変形せしめられ、その後で電極４２と４３ａが相互に接触する。しかし、本発明はこのような関係に限定されるわけではない。   In the third embodiment, as shown in FIG. 19A, the height of the island-shaped adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is set to be larger than the height Hb of the electrode 43a. (Ha> Hb), the thickness Hd of the continuous adhesive film 44c is set smaller than the height Hc of the electrode 42 (Hc> Hd), and the height Ha of the adhesive element 44bb2 and the adhesive film The sum of the thickness Hd of 44c is set larger than the sum of the height Hb of the electrode 43a and the height HC of the electrode (Ha + Hd> Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44c and 44b2 are first brought into contact with each other and deformed, and then the electrodes 42 and 43a are brought into contact with each other. . However, the present invention is not limited to such a relationship.

ここで述べる第１５実施形態に係る集積回路装置の製造方法では、図４２（ａ）に示すように、接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きく設定され（Ｈａ＞Ｈｂ）、連続的な接着剤膜４４ｃの厚さＨｄは、電極４２の高さＨｃよりも小さく設定されている（Ｈｃ＞Ｈｄ）点は、上記第３実施形態と同じであるが、接着剤要素４４ｂｂ２の高さＨａと接着剤膜４４ｃの厚さＨｄの和が、電極４３ａの高さＨｂと電極４２の高さＨｃの和よりも小さく設定されている（Ｈａ＋Ｈｄ＜Ｈｂ＋Ｈｃ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず電極４２と４３ａが相互に接触し、その後に接着剤膜４４ｂ１と４４ｂ２が相互に接触する。それ以外の点は上記第３実施形態と同じである。   In the method of manufacturing the integrated circuit device according to the fifteenth embodiment described here, as shown in FIG. 42A, the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the height of the electrode 43a. Is set to be larger than the height Hb (Ha> Hb), and the thickness Hd of the continuous adhesive film 44c is set to be smaller than the height Hc of the electrode 42 (Hc> Hd). Although the same as the embodiment, the sum of the height Ha of the adhesive element 44bb2 and the thickness Hd of the adhesive film 44c is set to be smaller than the sum of the height Hb of the electrode 43a and the height Hc of the electrode 42. (Ha + Hd <Hb + Hc). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the third embodiment.

したがって、第１５実施形態に係る集積回路装置の製造方法においても、上記第３実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effects as those of the third embodiment can be obtained also in the integrated circuit device manufacturing method according to the fifteenth embodiment.

第１５実施形態は、上述した第４実施形態の変形例１にも相当する。   The fifteenth embodiment corresponds to the first modification of the fourth embodiment described above.

第１５実施形態では、第１半導体回路層１ａと第２半導体回路層２の間の隙間に接着剤膜４４ｃ及び４４ｂ２が充填されるようにするため、電極４３ａの変形量を大きくする必要がある。そこで、電極４３ａと共に電極４２も塑性変形するように構成するのが好ましい。   In the fifteenth embodiment, it is necessary to increase the amount of deformation of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive films 44c and 44b2. . Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

（第１６実施形態）
図４３は、本発明の第１６実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１６実施形態は、上述した第３実施形態の変形例２に相当する。 (Sixteenth embodiment)
FIG. 43 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the sixteenth embodiment of the present invention. The sixteenth embodiment corresponds to the second modification of the third embodiment described above.

ここで述べる第１６実施形態に係る集積回路装置の製造方法では、図４３（ａ）に示すように、接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きく設定されている（Ｈａ＞Ｈｂ）点は、上記第３実施形態と同じであるが、連続的な接着剤膜４４ｃの厚さＨｄは、電極４２の高さＨｃよりも大きく設定されている（Ｈｃ＜Ｈｄ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず接着剤膜４４ｂ１と４４ｂ２が相互に接触し、その後に電極４２と４３ａが相互に接触する。それ以外の点は上記第３実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the sixteenth embodiment described here, as shown in FIG. 43A, the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is the height of the electrode 43a. The point set to be larger than the height Hb (Ha> Hb) is the same as in the third embodiment, but the thickness Hd of the continuous adhesive film 44c is larger than the height Hc of the electrode 42. The set point (Hc <Hd) is different. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are first in contact with each other, and then the electrodes 42 and 43a are in contact with each other. The other points are the same as in the third embodiment.

したがって、第１６実施形態に係る集積回路装置の製造方法においても、上記第３実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effects as those of the third embodiment can be obtained also in the integrated circuit device manufacturing method according to the sixteenth embodiment.

第１６実施形態は、上述した第４実施形態の変形例２にも相当する。   The sixteenth embodiment corresponds to the second modification of the fourth embodiment described above.

（第１７実施形態）
図４４は、本発明の第１７実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１７実施形態は、上述した第３実施形態の変形例３に相当する。 (17th Embodiment)
FIG. 44 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the seventeenth embodiment of the present invention. The seventeenth embodiment corresponds to the third modification of the third embodiment described above.

ここで述べる第１７実施形態に係る集積回路装置の製造方法では、図４４（ａ）に示すように、連続的な接着剤膜４４ｃの厚さＨｄが、電極４２の高さＨｃよりも小さく設定されている（Ｈｃ＞Ｈｄ）点は、上記第３実施形態と同じであるが、接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａが、電極４３ａの高さＨｂよりも小さく設定されている（Ｈａ＜Ｈｂ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず電極４２と４３ａが相互に接触し、その後に接着剤膜４４ｂ１と４４ｂ２が相互に接触する。それ以外の点は上記第３実施形態と同じである。   In the integrated circuit device manufacturing method according to the seventeenth embodiment described here, the thickness Hd of the continuous adhesive film 44c is set smaller than the height Hc of the electrode 42, as shown in FIG. (Hc> Hd) is the same as in the third embodiment, but the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is smaller than the height Hb of the electrode 43a. The set point (Ha <Hb) is different. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the electrodes 42 and 43a first contact each other, and then the adhesive films 44b1 and 44b2 contact each other. The other points are the same as in the third embodiment.

したがって、第１７実施形態に係る集積回路装置の製造方法においても、上記第３実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effect as that of the third embodiment can be obtained in the method of manufacturing an integrated circuit device according to the seventeenth embodiment.

第１７実施形態は、上述した第４実施形態の変形例３にも相当する。   The seventeenth embodiment also corresponds to the third modification of the fourth embodiment described above.

第１７実施形態では、第１半導体回路層１ａと第２半導体回路層２の間の隙間に接着剤膜４４ｃ及び４４ｂ２が充填されるようにするため、電極４３ａの変形量を大きくする必要がある。そこで、電極４３ａと共に電極４２も塑性変形するように構成するのが好ましい。   In the seventeenth embodiment, it is necessary to increase the deformation amount of the electrode 43a so that the adhesive films 44c and 44b2 are filled in the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2. . Therefore, it is preferable to configure the electrode 42 so as to be plastically deformed together with the electrode 43a.

（第１８実施形態）
図４５は、本発明の第１８実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１８実施形態は、上述した第３実施形態の変形例４に相当する。 (Eighteenth embodiment)
FIG. 45 is a partial enlarged cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the eighteenth embodiment of the present invention. The eighteenth embodiment corresponds to Modification 4 of the third embodiment described above.

ここで述べる第１８実施形態に係る集積回路装置の製造方法では、図４５（ａ）に示すように、連続的な接着剤膜４４ｃの厚さＨｄが、電極４２の高さＨｃよりも小さく設定されている（Ｈｃ＞Ｈｄ）点は、上記第３実施形態と同じであるが、接着剤要素４４ｂｂ２の高さ（接着剤膜４４ｂ２の厚さ）Ｈａが、電極４３ａの高さＨｂよりも大きく設定されており（Ｈａ＞Ｈｂ）、且つ、接着剤膜４４ｂ２の高さＨａと接着剤膜４４ｃの厚さＨｄの和が、電極４３ａの高さＨｂと電極４３ａの高さＨｃの和とほぼ同じに設定されている点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、電極４２と４３ａが相互に接触するのとほぼ同時に、接着剤膜４４ｂ１と４４ｂ２が相互に接触する。それ以外の点は上記第３実施形態と同じである。   In the integrated circuit device manufacturing method according to the eighteenth embodiment described here, the thickness Hd of the continuous adhesive film 44c is set smaller than the height Hc of the electrode 42, as shown in FIG. (Hc> Hd) is the same as in the third embodiment, but the height of the adhesive element 44bb2 (the thickness of the adhesive film 44b2) Ha is larger than the height Hb of the electrode 43a. Is set (Ha> Hb), and the sum of the height Ha of the adhesive film 44b2 and the thickness Hd of the adhesive film 44c is substantially equal to the sum of the height Hb of the electrode 43a and the height Hc of the electrode 43a. The difference is that they are set the same. For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive films 44b1 and 44b2 are in contact with each other almost simultaneously with the electrodes 42 and 43a being in contact with each other. The other points are the same as in the third embodiment.

したがって、第１８実施形態に係る集積回路装置の製造方法においても、上記第３実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effect as that of the third embodiment can be obtained in the method of manufacturing an integrated circuit device according to the eighteenth embodiment.

第１８実施形態は、上述した第４実施形態の変形例４にも相当する。   The eighteenth embodiment also corresponds to the fourth modification of the fourth embodiment described above.

（第１９実施形態）
図４６は、本発明の第１９実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第１９実施形態は、上述した第５実施形態の変形例１に相当する。 (Nineteenth embodiment)
FIG. 46 is a partially enlarged cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the nineteenth embodiment of the present invention. The nineteenth embodiment corresponds to Modification 1 of the fifth embodiment described above.

上記第５実施形態では、図３０（ａ）に示すように、島状の接着剤要素４４ａの高さ（接着剤膜４４ａの厚さ）Ｈａは、電極４３ａの高さＨｂよりも大きく設定され（Ｈａ＞Ｈｂ）、且つ、接着剤膜４４ａの厚さＨａは、導電性バンプ１５の突出高さＨｅと電極４３ａの高さＨｂの和よりも大きく設定されている（Ｈａ＞Ｈｂ＋Ｈｅ）。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、先に接着剤膜４４ａが第１半導体回路層１ｂの裏面に接触して変形せしめられ、その後で導電性バンプ１５と電極４３ａが相互に接触する。しかし、本発明はこのような関係に限定されるわけではない。   In the fifth embodiment, as shown in FIG. 30A, the height of the island-shaped adhesive element 44a (the thickness of the adhesive film 44a) Ha is set larger than the height Hb of the electrode 43a. (Ha> Hb), and the thickness Ha of the adhesive film 44a is set to be larger than the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a (Ha> Hb + He). For this reason, in the connecting step of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive film 44a is first deformed by contacting the back surface of the first semiconductor circuit layer 1b, and then the conductive bump 15 And the electrode 43a are in contact with each other. However, the present invention is not limited to such a relationship.

ここで述べる第１９実施形態に係る集積回路装置の製造方法では、図４６（ａ）に示すように、島状の接着剤要素４４ａの高さ（接着剤膜４４ａの厚さ）Ｈａが、電極４３ａの高さＨｂよりも大きく設定されている（Ｈａ＞Ｈｂ）点は、上記第５実施形態と同じであるが、導電性バンプ１５の突出高さＨｅと電極４３ａの高さＨｂの和よりも小さく設定されている（Ｈａ＜Ｈｂ＋Ｈｅ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず導電性バンプ１５と電極４３ａが相互に接触し、その後、接着剤膜４４ａが第１半導体回路層１ｂの裏面に接触する。それ以外の点は上記第５実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the nineteenth embodiment described here, as shown in FIG. 46A, the height of the island-like adhesive element 44a (the thickness of the adhesive film 44a) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as that of the fifth embodiment, but from the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a. Is different (Ha <Hb + He). For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, first, the conductive bump 15 and the electrode 43a are in contact with each other, and then the adhesive film 44a is the back surface of the first semiconductor circuit layer 1b. To touch. The other points are the same as in the fifth embodiment.

したがって、第１９実施形態に係る集積回路装置の製造方法においても、上記第５実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effect as that of the fifth embodiment can be obtained also in the manufacturing method of the integrated circuit device according to the nineteenth embodiment.

第１９実施形態では、第１半導体回路層１ａと第２半導体回路層２の間の隙間に接着剤膜４４ａが充填されるようにするため、電極４３ａの変形量を大きくする必要があるが、それには限界がある。そこで、接着剤膜４４ａの厚さＨａと、導電性バンプ１５の突出高さＨｅと電極４３ａの高さＨｂの和との差（Ｈａ−Ｈｂ−Ｈｅ）を、あまり大きくしないようにするのが好ましい。   In the nineteenth embodiment, it is necessary to increase the deformation amount of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive film 44a. It has its limits. Therefore, the difference (Ha−Hb−He) between the thickness Ha of the adhesive film 44a and the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a should not be so large. preferable.

（第２０実施形態）
図４７は、本発明の第２０実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第２０実施形態は、上述した第５実施形態の変形例２に相当する。 (20th embodiment)
FIG. 47 is a partially enlarged cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the twentieth embodiment of the present invention. The twentieth embodiment corresponds to the second modification of the fifth embodiment described above.

ここで述べる第２０実施形態に係る集積回路装置の製造方法では、図４７（ａ）に示すように、島状の接着剤要素４４ａの高さ（接着剤膜４４ａの厚さ）Ｈａが、電極４３ａの高さＨｂよりも小さく設定されている（Ｈａ＜Ｈｂ）点が、上記第５実施形態とは異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、まず導電性バンプ１５と電極４３ａが相互に接触し、その後、接着剤膜４４ａが第１半導体回路層１ｂの裏面に接触する。それ以外の点は上記第５実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the twentieth embodiment described here, as shown in FIG. 47A, the height of the island-shaped adhesive element 44a (the thickness of the adhesive film 44a) Ha is the electrode. The point which is set smaller than the height Hb of 43a (Ha <Hb) is different from the fifth embodiment. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, first, the conductive bump 15 and the electrode 43a are in contact with each other, and then the adhesive film 44a is the back surface of the first semiconductor circuit layer 1b. To touch. The other points are the same as in the fifth embodiment.

したがって、第２０実施形態に係る集積回路装置の製造方法においても、上記第５実施形態と同様の効果が得られることは明らかである。   Therefore, it is apparent that the same effect as that of the fifth embodiment can be obtained in the method of manufacturing an integrated circuit device according to the twentieth embodiment.

第２０実施形態では、第１半導体回路層１ａと第２半導体回路層２の間の隙間に接着剤膜４４ａが充填されるようにするため、電極４３ａの変形量を大きくする必要があるが、それには限界がある。そこで、接着剤膜４４ａの厚さＨａと、導電性バンプ１５の突出高さＨｅと電極４３ａの高さＨｂの和との差（Ｈａ−Ｈｂ−Ｈｅ）を、あまり大きくしないようにするのが好ましい。   In the twentieth embodiment, it is necessary to increase the deformation amount of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive film 44a. It has its limits. Therefore, the difference (Ha−Hb−He) between the thickness Ha of the adhesive film 44a and the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a should not be so large. preferable.

（第２１実施形態）
図４８は、本発明の第２１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。この第２０実施形態は、上述した第５実施形態の変形例３に相当する。 (21st Embodiment)
FIG. 48 is a partial enlarged cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the twenty-first embodiment of the present invention. The twentieth embodiment corresponds to the third modification of the fifth embodiment described above.

ここで述べる第２１実施形態に係る集積回路装置の製造方法では、図４８（ａ）に示すように、島状の接着剤要素４４ａの高さ（接着剤膜４４ａの厚さ）Ｈａが、電極４３ａの高さＨｂよりも大きく設定されている（Ｈａ＞Ｈｂ）点は、上記第５実施形態と同じであるが、導電性バンプ１５の突出高さＨｅと電極４３ａの高さＨｂの和とほぼ同じに設定されている（Ｈａ≒Ｈｂ＋Ｈｅ）点が異なる。このため、第１半導体回路層１ａと第２半導体回路層２の接続工程では、導電性バンプ１５と電極４３ａが相互に接触≒するのとほぼ同時に、接着剤膜４４ａが第１半導体回路層１ｂの裏面に接触する。それ以外の点は上記第５実施形態と同じである。   In the method of manufacturing an integrated circuit device according to the twenty-first embodiment described here, as shown in FIG. 48A, the height of the island-like adhesive element 44a (the thickness of the adhesive film 44a) Ha is the electrode. The point set to be larger than the height Hb of 43a (Ha> Hb) is the same as in the fifth embodiment, but the sum of the protruding height He of the conductive bump 15 and the height Hb of the electrode 43a is The points that are set substantially the same (Ha≈Hb + He) are different. For this reason, in the connection process of the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2, the adhesive film 44a is formed on the first semiconductor circuit layer 1b almost simultaneously with the contact between the conductive bump 15 and the electrode 43a. Touch the back of the. The other points are the same as in the fifth embodiment.

したがって、第２１実施形態に係る集積回路装置の製造方法においても、上記第５実施形態と同様の効果が得られることは明らかである。   Therefore, it is obvious that the same effect as that of the fifth embodiment can be obtained in the method of manufacturing an integrated circuit device according to the twenty-first embodiment.

第２１実施形態では、第１半導体回路層１ａと第２半導体回路層２の間の隙間に接着剤膜４４ａが充填されるようにするため、電極４３ａの変形量を大きくする必要がある。   In the twenty-first embodiment, it is necessary to increase the deformation amount of the electrode 43a in order to fill the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 with the adhesive film 44a.

（第２２実施形態）
図４９は、本発明の第２２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法において使用される電極のレイアウトと接着剤膜のパターンを示す、図３２（ｂ）と同様の図である。 (Twenty-second embodiment)
FIG. 49 is a view similar to FIG. 32B, showing an electrode layout and an adhesive film pattern used in the method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twenty-second embodiment of the present invention. It is.

図４９に示された矩形の四つの頂点にそれぞれ配置された四つの電極４３ａ（第２半導体回路層２の表面に設けられる）は、一組になっていて、図３２（ａ）に示したものと同様に、一つの電極４２または導電性バンプ１５の突出部（第１半導体回路層１ａまたは１ｂの裏面に設けられる）に対して一対一で接続される。   49. Four electrodes 43a (provided on the surface of the second semiconductor circuit layer 2) respectively disposed at the four vertices of the rectangle shown in FIG. 49 form a set, and are shown in FIG. 32 (a). Similarly to the above, one electrode 42 or the protruding portion of the conductive bump 15 (provided on the back surface of the first semiconductor circuit layer 1a or 1b) is connected on a one-to-one basis.

図３２（ｂ）では、接着剤膜４４ａは、規則的に配置された多数の島状の接着剤要素４４ａａに分割されており、電極４３ａの各組の周囲を取り囲んでいる。他方、図４９に示された接着剤膜４４ｄは、Ｘ方向及びＹ方向に連続的に形成されたものである。すなわち、接着剤膜４４ｄは、格子状パターンを持っていて、Ｘ方向に延在する複数の帯状部と、それらと直交するＹ方向に延在する複数の帯状部とから構成されている。この接着剤膜４４ｄは、上述した接着剤膜４４ｃ、４４ｃ１、４４ｃ２に相当するものである。   In FIG. 32 (b), the adhesive film 44a is divided into a number of regularly arranged island-like adhesive elements 44aa, and surrounds each set of electrodes 43a. On the other hand, the adhesive film 44d shown in FIG. 49 is continuously formed in the X direction and the Y direction. That is, the adhesive film 44d has a lattice pattern, and includes a plurality of strips extending in the X direction and a plurality of strips extending in the Y direction orthogonal to them. The adhesive film 44d corresponds to the above-described adhesive films 44c, 44c1, and 44c2.

第２２実施形態の製造方法では、図４９に示された格子状の接着剤膜４４ｄを使用するので、平面的には（つまり、接着剤膜４４ｄを含む平面内では）気体の逃げ道はない。しかし、第１半導体回路層１ａと第２半導体回路層２の間の隙間（電極４３ａの各組の周囲）に存在する気体は、両者の間に形成される空隙４５（図６（ｋ）を参照）を通って外部に排出されることができる。   In the manufacturing method of the twenty-second embodiment, since the lattice-like adhesive film 44d shown in FIG. 49 is used, there is no gas escape route in a plane (that is, in a plane including the adhesive film 44d). However, the gas existing in the gaps (around each set of electrodes 43a) between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 passes through the gaps 45 (FIG. 6 (k)) formed between them. See) can be discharged to the outside.

（第２３実施形態）
図５０は、本発明の第２３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法において使用される電極のレイアウトと接着剤膜のパターンを示す、図３２（ｂ）と同様の図である。 (23rd Embodiment)
FIG. 50 is a view similar to FIG. 32B, showing an electrode layout and an adhesive film pattern used in the method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twenty-third embodiment of the present invention. It is.

図５０に示された電極４３ａのレイアウトは、図４９の電極４３ａと同じである。図５０に示された接着剤膜４４ｅは、Ｘ方向にのみ連続的に形成されたものである。接着剤膜４４ｅは、ストライプ状パターンを持っていて、Ｘ方向に延在する複数の帯状部から構成されている。隣接する帯状部の間には、それぞれ、脱ガス用の通路となる空隙５１が存在する。   The layout of the electrode 43a shown in FIG. 50 is the same as that of the electrode 43a in FIG. The adhesive film 44e shown in FIG. 50 is formed continuously only in the X direction. The adhesive film 44e has a striped pattern and is composed of a plurality of strips extending in the X direction. Between adjacent strips, there are gaps 51 that serve as degassing passages.

第２３実施形態の製造方法では、図５０に示された格子状の接着剤膜４４ｅを使用するので、第１半導体回路層１ａと第２半導体回路層２の間の隙間（電極４３ａの各組の周囲）に存在する気体は、両者の間に形成される空隙４５（図６（ｋ）を参照）と、接着剤膜４４ｅの空隙５１とを通って外部に排出される。このため、第２２実施形態に比べて気体が排出されやすい利点がある。   In the manufacturing method of the twenty-third embodiment, since the lattice-like adhesive film 44e shown in FIG. 50 is used, the gaps between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 (each set of the electrodes 43a). The gas existing in the vicinity of the gas is discharged to the outside through the gap 45 (see FIG. 6 (k)) formed between them and the gap 51 of the adhesive film 44e. For this reason, there exists an advantage which is easy to discharge | emit gas compared with 22nd Embodiment.

（第２４実施形態）
図５１は、本発明の第２４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法において使用される電極のレイアウトと接着剤膜のパターンを示す、図３２（ｂ）と同様の図である。 (24th Embodiment)
FIG. 51 is a view similar to FIG. 32B, showing an electrode layout and an adhesive film pattern used in the method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twenty-fourth embodiment of the present invention. It is.

図５１に示された電極４３ａのレイアウトは、図４９の電極４３ａと同じである。図５１に示された接着剤膜４４ｆは、Ｙ方向に延在する帯状部に複数のスリット５２が形成されている点を除き、図４９の接着剤膜４４ｄと同じである。   The layout of the electrode 43a shown in FIG. 51 is the same as that of the electrode 43a in FIG. The adhesive film 44f shown in FIG. 51 is the same as the adhesive film 44d shown in FIG. 49 except that a plurality of slits 52 are formed in a belt-like portion extending in the Y direction.

第２４実施形態の製造方法では、図５１に示された格子状の接着剤膜４４ｆを使用するので、第１半導体回路層１ａと第２半導体回路層２の間の隙間（電極４３ａの各組の周囲）に存在する気体は、両者の間に形成される空隙４５と、接着剤膜４４ｆの空隙５１及びスリット５２とを通って外部に排出される。このため、第２２実施形態に比べて気体が排出されやすい利点がある。   In the manufacturing method of the twenty-fourth embodiment, since the lattice-like adhesive film 44f shown in FIG. 51 is used, the gap between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 (each set of the electrodes 43a). The gas existing in the vicinity of the gas is discharged to the outside through the gap 45 formed between them, the gap 51 of the adhesive film 44f, and the slit 52. For this reason, there exists an advantage which is easy to discharge | emit gas compared with 22nd Embodiment.

（第２５実施形態）
図５２は、本発明の第２５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法において使用される電極のレイアウトと接着剤膜のパターンを示す、図３２（ｂ）と同様の図である。 (25th Embodiment)
FIG. 52 is a view similar to FIG. 32B, showing an electrode layout and an adhesive film pattern used in the method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the twenty-fifth embodiment of the present invention. It is.

図５２に示された電極４３ａのレイアウトは、図４９の電極４３ａと同じである。図５２に示された接着剤膜４４ｇは、Ｙ方向に延在する帯状部とＸ方向に延在する帯状部にそれぞれ複数のスリット５２及び５３が形成されている点を除き、図４９の接着剤膜４４ｄと同じである。   The layout of the electrode 43a shown in FIG. 52 is the same as that of the electrode 43a in FIG. The adhesive film 44g shown in FIG. 52 is similar to the adhesive film shown in FIG. 49 except that a plurality of slits 52 and 53 are formed in the belt-like portion extending in the Y direction and the belt-like portion extending in the X direction. It is the same as the agent film 44d.

第２５実施形態の製造方法では、図５２に示された格子状の接着剤膜４４ｇを使用するので、第１半導体回路層１ａと第２半導体回路層２の間の隙間（電極４３ａの各組の周囲）に存在する気体は、両者の間に形成される空隙４５と、接着剤膜４４ｆの空隙５１並びにスリット５２及び５３とを通って外部に排出される。このため、第２２実施形態及び第２３実施形態に比べて気体が排出されやすい利点がある。   In the manufacturing method of the twenty-fifth embodiment, since the lattice-like adhesive film 44g shown in FIG. 52 is used, the gaps between the first semiconductor circuit layer 1a and the second semiconductor circuit layer 2 (each set of the electrodes 43a). The gas existing in the periphery) is discharged to the outside through the gap 45 formed therebetween, the gap 51 of the adhesive film 44f, and the slits 52 and 53. For this reason, there exists an advantage which gas is easy to be discharged | emitted compared with 22nd Embodiment and 23rd Embodiment.

（変形例）
上述した第１〜第２５実施形態は本発明を具体化した例を示すものであり、したがって本発明はこれらの実施形態に限定されるものではなく、本発明の趣旨を外れることなく種々の変形が可能であることは言うまでもない。例えば、上述した第１〜第２５実施形態では、隣接する半導体回路層のマイクロバンプ電極同士（あるいは導電性プラグとマイクロバンプ電極）を「加熱圧接」によって接合させているが、本発明はこれに限定されない。マイクロバンプ電極や導電性プラグの材質によっては、室温における圧接すなわち「室温圧接」が可能であるから、そのような場合には「室温圧接」を使用してもよいことは言うまでもない。また、マイクロバンプ電極同士（あるいは導電性プラグとマイクロバンプ電極）を適当な接合用金属（例えばハンダ合金）を介在させて相互に接合させてもよい。 (Modification)
The first to 25th embodiments described above show examples embodying the present invention. Therefore, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. It goes without saying that is possible. For example, in the first to 25th embodiments described above, the microbump electrodes of the adjacent semiconductor circuit layers (or the conductive plug and the microbump electrode) are joined together by “heating pressure welding”. It is not limited. Depending on the material of the micro-bump electrode and the conductive plug, pressure welding at room temperature, that is, “room temperature pressure welding” is possible. Needless to say, “room temperature pressure welding” may be used in such a case. Alternatively, the microbump electrodes (or the conductive plug and the microbump electrode) may be bonded to each other with an appropriate bonding metal (for example, a solder alloy) interposed therebetween.

また、上述した第１〜第２５実施形態では、主として第１半導体回路層を支持基板に固着する場合について説明しているが、本発明はこれに限定されない。例えば、本発明を第２半導体回路層に適用すれば、当該第２半導体回路層はそれに隣接する第１半導体回路層に固着されることになる。   In the first to 25th embodiments described above, the case where the first semiconductor circuit layer is mainly fixed to the support substrate has been described, but the present invention is not limited to this. For example, when the present invention is applied to the second semiconductor circuit layer, the second semiconductor circuit layer is fixed to the first semiconductor circuit layer adjacent thereto.

さらに、上述した第１〜第２５実施形態では、半導体回路層の各々を単一の半導体ウェハーにより形成する場合について述べているが、本発明はこれらに限定されない。例えば、半導体回路層の各々を複数の半導体チップにより形成してもよい。また、少なくとも一つの半導体回路層を単一の半導体ウェハーにより形成し、残りの半導体回路層の各々を複数の半導体チップにより形成してもよい。ある半導体回路層を複数の半導体チップにより形成する場合、それら半導体チップのすべてが電子回路を内蔵していなくてもよい。すなわち、いくつかの半導体チップは電子回路を内蔵していない（または電子回路を内蔵しているが使用されていない）「ダミーチップ」でもよい。また、ある半導体回路層を単一の半導体ウェハーにより形成する場合、その半導体ウェハーが、電子回路を内蔵していない（または電子回路を内蔵しているが使用されていない）「ダミー領域」を含んでいてもよい。   Furthermore, in the first to 25th embodiments described above, the case where each of the semiconductor circuit layers is formed by a single semiconductor wafer is described, but the present invention is not limited to these. For example, each of the semiconductor circuit layers may be formed by a plurality of semiconductor chips. Further, at least one semiconductor circuit layer may be formed by a single semiconductor wafer, and each of the remaining semiconductor circuit layers may be formed by a plurality of semiconductor chips. When a certain semiconductor circuit layer is formed of a plurality of semiconductor chips, all of the semiconductor chips do not have to incorporate an electronic circuit. That is, some semiconductor chips may be “dummy chips” that do not contain electronic circuits (or that contain electronic circuits but are not used). When a semiconductor circuit layer is formed of a single semiconductor wafer, the semiconductor wafer includes a “dummy region” that does not contain an electronic circuit (or that contains an electronic circuit but is not used). You may go out.

本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図である。It is a fragmentary sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure which concerns on 1st Embodiment of this invention for every process. 本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図１の続きである。FIG. 3 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each process, and is a continuation of FIG. 1. 本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図２の続きである。FIG. 3 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each process, and is a continuation of FIG. 2. 本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図３の続きである。FIG. 4 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG. 3. 本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図４の続きである。FIG. 5 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each process, and is a continuation of FIG. 4. 本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図５の続きである。FIG. 6 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG. 5. 本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図６の続きである。FIG. 7 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each process, and is a continuation of FIG. 6. 本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図７の続きである。FIG. 9 is a partial cross-sectional view showing the method for manufacturing the integrated circuit device having the three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG. 7. （ａ）、（ｂ）は、本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図５の工程と図６の工程の詳細をそれぞれ示す部分拡大断面図である。(A), (b) is the elements on larger scale which each show the detail of the process of FIG. 5 of the manufacturing method of the integrated circuit device with the three-dimensional laminated structure which concerns on 1st Embodiment of this invention, and the process of FIG. is there. 本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図７（ｌ）の工程の詳細を示す部分拡大断面図である。FIG. 8 is a partial enlarged cross-sectional view showing details of the step of FIG. 7L of the method for manufacturing the integrated circuit device having a three-dimensional laminated structure according to the first embodiment of the present invention. 本発明の第２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図５に対応するものである。FIG. 7 is a partial cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional laminated structure according to a second embodiment of the present invention for each step, and corresponds to FIG. 5. 本発明の第２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図１１の続きであり、図６に対応するものである。FIG. 12 is a partial cross-sectional view illustrating a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to a second embodiment of the present invention for each step, which is a continuation of FIG. 11 and corresponds to FIG. 6. 本発明の第２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図１２の続きであり、図７に対応するものである。FIG. 13 is a partial cross-sectional view illustrating a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to a second embodiment of the present invention for each step, which is a continuation of FIG. 12 and corresponds to FIG. （ａ）、（ｂ）は、本発明の第２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図１１と図１２の工程の詳細をそれぞれ示す部分拡大断面図である。(A), (b) is a partial expanded sectional view which shows the detail of the process of FIG. 11 and FIG. 12 of the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure which concerns on 2nd Embodiment of this invention, respectively. 本発明の第２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図１３の工程の詳細を示す部分拡大断面図である。FIG. 14 is a partial enlarged cross-sectional view showing details of the step of FIG. 13 in the method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to the second embodiment of the present invention. 本発明の第３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図５に対応するものである。FIG. 5 is a partial cross-sectional view showing a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to a third embodiment of the present invention for each step, and corresponds to FIG. 5. 本発明の第３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図１６の続きであり、図６に対応するものである。FIG. 17 is a partial cross-sectional view illustrating a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to a third embodiment of the present invention for each process, and is a continuation of FIG. 16 and corresponds to FIG. 本発明の第３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図１７の続きであり、図７に対応するものである。FIG. 18 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having a three-dimensional stacked structure according to the third embodiment of the present invention for each process, and is a continuation of FIG. 17 and corresponds to FIG. （ａ）、（ｂ）は、本発明の第３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図１６と図１７の工程の詳細をそれぞれ示す部分拡大断面図である。(A), (b) is a partial expanded sectional view which respectively shows the detail of the process of FIG. 16 and FIG. 17 of the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 3rd Embodiment of this invention. 本発明の第３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図１８の工程の詳細を示す部分拡大断面図である。FIG. 19 is a partial enlarged cross-sectional view illustrating details of the process of FIG. 18 of the method for manufacturing the integrated circuit device having a three-dimensional stacked structure according to the third embodiment of the present invention. 本発明の第４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図５に対応するものである。FIG. 9 is a partial cross-sectional view showing a method of manufacturing an integrated circuit device having a three-dimensional laminated structure according to a fourth embodiment of the present invention for each step, corresponding to FIG. 5. 本発明の第４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図２１の続きであり、図６に対応するものである。FIG. 22 is a partial cross-sectional view illustrating a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to a fourth embodiment of the present invention for each step, which is a continuation of FIG. 21 and corresponds to FIG. 6. 本発明の第４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図２２の続きであり、図７に対応するものである。FIG. 24 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fourth embodiment of the present invention for each step, which is a continuation of FIG. 22 and corresponds to FIG. 7; （ａ）、（ｂ）は、本発明の第４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図２１と図２２の工程の詳細をそれぞれ示す部分拡大断面図である。(A), (b) is a partial expanded sectional view which shows the detail of the process of FIG. 21 and FIG. 22 of the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 4th Embodiment of this invention, respectively. 本発明の第４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図２３の工程の詳細を示す部分拡大断面図である。FIG. 24 is a partial enlarged cross-sectional view showing details of the step of FIG. 23 in the method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fourth embodiment of the present invention. （ａ）、（ｂ）は、本発明の第５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図３（ｇ）と図４（ｈ）にそれぞれ対応するものである。FIGS. 3A and 4B are partial cross-sectional views showing a method of manufacturing an integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention for each step, and FIGS. ) Respectively. 本発明の第５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図２６の続きであり、図５に対応するものである。FIG. 27 is a partial cross-sectional view illustrating the method for manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention for each process, and is a continuation of FIG. 26 and corresponds to FIG. 5. 本発明の第５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図２７の続きであり、図６に対応するものである。FIG. 28 is a partial cross-sectional view illustrating a method for manufacturing an integrated circuit device having a three-dimensional stacked structure according to a fifth embodiment of the present invention for each step, which is a continuation of FIG. 27 and corresponds to FIG. 6. 本発明の第５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を工程毎に示す部分断面図で、図２８の続きであり、図７に対応するものである。FIG. 29 is a partial cross-sectional view showing the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention for each process, and is a continuation of FIG. 28 and corresponds to FIG. （ａ）、（ｂ）は、本発明の第５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図２７と図２８の工程の詳細をそれぞれ示す部分拡大断面図である。(A), (b) is a partial expanded sectional view which shows the detail of the process of FIG. 27 and FIG. 28 of the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 5th Embodiment of this invention, respectively. 本発明の第５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法の図２９の工程の詳細を示す部分拡大断面図である。FIG. 30 is a partial enlarged cross-sectional view showing details of the step of FIG. 29 in the method of manufacturing the integrated circuit device having a three-dimensional stacked structure according to the fifth embodiment of the present invention. （ａ）は、本発明の第１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される上下のマイクロバンプ電極の位置と大きさの関係を示す概略平面図、（ｂ）は同製造方法において第２半導体回路層の多層配線構造の表面に配置された、マイクロバンプ電極群と接着剤要素群のレイアウトの一例を示す概念図である。(A) is a schematic top view which shows the relationship between the position and magnitude | size of an upper and lower micro bump electrode used with the manufacturing method of the integrated circuit device which has the three-dimensional laminated structure which concerns on 1st Embodiment of this invention, (b) ) Is a conceptual diagram showing an example of a layout of a micro-bump electrode group and an adhesive element group disposed on the surface of the multilayer wiring structure of the second semiconductor circuit layer in the manufacturing method. 本発明の第６実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 6th Embodiment of this invention. 本発明の第７実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 7th Embodiment of this invention. 本発明の第８実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 8th Embodiment of this invention. 本発明の第９実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 9th Embodiment of this invention. 本発明の第１０実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 10th Embodiment of this invention. 本発明の第１１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 11th Embodiment of this invention. 本発明の第１２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 12th Embodiment of this invention. 本発明の第１３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 13th Embodiment of this invention. 本発明の第１４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 14th Embodiment of this invention. 本発明の第１５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 15th Embodiment of this invention. 本発明の第１６実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 16th Embodiment of this invention. 本発明の第１７実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 17th Embodiment of this invention. 本発明の第１８実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 18th Embodiment of this invention. 本発明の第１９実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 19th Embodiment of this invention. 本発明の第２０実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 20th Embodiment of this invention. 本発明の第２１実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す部分拡大断面図である。It is a partial expanded sectional view which shows the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 21st Embodiment of this invention. 本発明の第２２実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される電極のレイアウトと接着剤膜のパターンを示す部分拡大平面図である。It is the elements on larger scale which show the layout of the electrode used by the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 22nd Embodiment of this invention, and the pattern of an adhesive film. 本発明の第２３実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される電極のレイアウトと接着剤膜のパターンを示す部分拡大平面図である。It is a partial enlarged plan view which shows the layout of the electrode used by the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 23rd Embodiment of this invention, and the pattern of an adhesive film. 本発明の第２４実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される電極のレイアウトと接着剤膜のパターンを示す部分拡大平面図である。It is a partial enlarged plan view which shows the layout of the electrode used by the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 24th Embodiment of this invention, and the pattern of an adhesive film. 本発明の第２５実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される電極のレイアウトと接着剤膜のパターンを示す部分拡大平面図である。It is a partial enlarged plan view which shows the layout of the electrode used by the manufacturing method of the integrated circuit device which has a three-dimensional laminated structure concerning 25th Embodiment of this invention, and the pattern of an adhesive film.

符号の説明Explanation of symbols

１ 第１半導体回路層
１ａ、１ｂ薄くされた第１半導体回路層
２ 第２半導体回路層
２ａ 薄くされた第２半導体回路層
１１ 半導体基板
１２ 酸化シリコン（ＳｉＯ2）膜
１２ａ 窒化シリコン（Ｓｉ3Ｎ4）膜
１２ｂ ゲート絶縁膜
１３ トレンチ
１４ 酸化シリコン（ＳｉＯ2）膜
１５ 導電性プラグ
１５ａ 導電性プラグの端部
１６ ソース・ドレイン領域
１７ フォトレジスト膜
１８ ゲート電極
１９ 層間絶縁膜
２０ 金属配線膜
２１ 導電性材料
３０ 多層配線構造
３１ 絶縁材料
３２、３３、３４ 配線層
３５、３６ 導電体
３７ マイクロバンプ電極
３８ 導電体
３９ 接着剤
４０ 支持基板
４１ 酸化シリコン（ＳｉＯ2）膜
４２、４３ａ マイクロバンプ電極
４４ａ、４４ｂ１、４４ｂ２、４４ｃ、４４ｃ１、４４ｃ２ 接着剤膜
４４ｂ１ｂ２、４４ｂ２ｃ、４４ｃ１ｃ２ 一体化された接着剤膜
４４ｄ、４４ｅ、４４ｆ、４４ｇ 接着剤膜
４５ 第１半導体回路層と第２半導体回路層の間に形成される脱ガス用通路
５１ 脱ガス用空隙
５２、５３ 脱ガス用スリット
DESCRIPTION OF SYMBOLS 1 1st semiconductor circuit layer 1a, 1b Thinned first semiconductor circuit layer 2 Second semiconductor circuit layer 2a Thinned second semiconductor circuit layer 11 Semiconductor substrate 12 Silicon oxide (SiO 2 ) film 12a Silicon nitride (Si 3 N 4 ) Film 12b Gate insulating film 13 Trench 14 Silicon oxide (SiO 2 ) film 15 Conductive plug 15a End of conductive plug 16 Source / drain region 17 Photoresist film 18 Gate electrode 19 Interlayer insulating film 20 Metal wiring film 21 Conductive Conductive material 30 Multi-layer wiring structure 31 Insulating material 32, 33, 34 Wiring layer 35, 36 Conductor 37 Micro bump electrode 38 Conductor 39 Adhesive 40 Support substrate 41 Silicon oxide (SiO 2 ) film 42, 43a Micro bump electrode 44a, 44b1, 44b2, 44c, 44c1, 44c2 Adhesive film 44b b2, 44b2c, 44c1c2 Integrated adhesive film 44d, 44e, 44f, 44g Adhesive film 45 Degassing passage 51 formed between the first semiconductor circuit layer and the second semiconductor circuit layer 51 Degassing gap 52 53 Degassing slit

Claims (1)

複数の半導体回路層を支持基板上に積層してなる三次元積層構造を持つ集積回路装置の製造方法であって、
前記三次元積層構造を構成する一つの半導体回路層の内部に、一端が当該半導体回路層の裏面から露出せしめられた複数の埋込配線を形成する工程と、
前記半導体回路層の裏面、あるいは前記三次元積層構造を構成する他の半導体回路層の表面、またはそれらの双方に、複数のバンプ電極を形成する工程と、
前記半導体回路層の裏面、あるいは前記他の半導体回路層の表面、またはそれらの双方に、前記埋込配線の露出端および前記バンプ電極とは重ならない形状にパターン化された電気的絶縁性の接着剤膜を形成する工程と、
前記接着剤膜を間に介在させながら、前記半導体回路層の裏面と前記他の半導体回路層の表面とを相互に対向させる工程と、
相互に対向せしめられた前記半導体回路層の裏面と前記他の半導体回路層の表面を、それらの間の層間ギャップが第１所定値になるまで近接させる工程と、
前記層間ギャップを第２所定値まで狭めることにより、前記接着剤膜を前記半導体回路層の裏面と前記他の半導体回路層の表面との間に残存する隙間内で変形させながら、また、前記埋込配線の露出端および前記バンプ電極の少なくとも一方を変形させながら、前記埋込配線の前記露出端と前記バンプ電極とを相互に接合させ、もって前記半導体回路層の裏面と前記他の半導体回路層の表面とを相互接続する工程とを備え、
前記接着剤膜を形成する前記工程では、パターン化された前記接着剤膜の総量は、前記層間ギャップが前記第２所定値にまで狭められた時に前記半導体回路層の裏面と前記他の半導体回路層の表面との間に残存する前記隙間の総体積にほぼ等しくなるように調整され、
前記半導体回路層の裏面と前記他の半導体回路層の表面とを相互接続する前記工程では、前記埋込配線の一つに対応する複数の前記バンプ電極が変形して一体化されることで、前記埋込配線と前記バンプ電極とが一対一対応になり、
前記半導体回路層の裏面と前記他の半導体回路層の表面とを相互接続する前記工程の終了後には、前記隙間は前記接着剤膜によって充填せしめられると共に、前記半導体回路層の裏面と前記他の半導体回路層の表面は前記接着剤膜によって相互接着されることを特徴とする集積回路装置の製造方法。 A method of manufacturing an integrated circuit device having a three-dimensional stacked structure in which a plurality of semiconductor circuit layers are stacked on a support substrate,
Forming a plurality of embedded wirings, one end of which is exposed from the back surface of the semiconductor circuit layer, inside one semiconductor circuit layer constituting the three-dimensional stacked structure;
Forming a plurality of bump electrodes on the back surface of the semiconductor circuit layer, or on the surface of another semiconductor circuit layer constituting the three-dimensional stacked structure, or both of them;
Electrically insulating adhesion patterned in a shape that does not overlap the exposed end of the embedded wiring and the bump electrode on the back surface of the semiconductor circuit layer, the surface of the other semiconductor circuit layer, or both of them Forming the agent film;
Making the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer face each other while interposing the adhesive film therebetween,
Bringing the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer facing each other close to each other until an interlayer gap therebetween becomes a first predetermined value;
By narrowing the interlayer gap to a second predetermined value, the adhesive film is deformed in the gap remaining between the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer, and the filling is performed. The exposed end of the embedded wiring and the bump electrode are bonded to each other while deforming at least one of the exposed end of the embedded wiring and the bump electrode, so that the back surface of the semiconductor circuit layer and the other semiconductor circuit layer are joined together. And interconnecting the surface of the
In the step of forming the adhesive film, the total amount of the patterned adhesive film is such that the back surface of the semiconductor circuit layer and the other semiconductor circuit when the interlayer gap is narrowed to the second predetermined value. Adjusted to be approximately equal to the total volume of the gap remaining between the surface of the layer,
In the step of interconnecting the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer, a plurality of the bump electrodes corresponding to one of the embedded wirings are deformed and integrated, The embedded wiring and the bump electrode have a one-to-one correspondence,
After the step of interconnecting the back surface of the semiconductor circuit layer and the surface of the other semiconductor circuit layer, the gap is filled with the adhesive film, and the back surface of the semiconductor circuit layer and the other semiconductor circuit layer A method of manufacturing an integrated circuit device, wherein surfaces of semiconductor circuit layers are bonded to each other by the adhesive film.
JP2005259824A 2005-09-07 2005-09-07 Manufacturing method of integrated circuit device having three-dimensional laminated structure Expired - Fee Related JP5175003B2 (en)

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