JP2666565B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2666565B2 JP2666565B2 JP2340916A JP34091690A JP2666565B2 JP 2666565 B2 JP2666565 B2 JP 2666565B2 JP 2340916 A JP2340916 A JP 2340916A JP 34091690 A JP34091690 A JP 34091690A JP 2666565 B2 JP2666565 B2 JP 2666565B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- forming
- thermal oxidation
- region
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMOS型半導体装置の製造方法に関し、特にゲ
ート絶縁膜の形成法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS type semiconductor device, and more particularly to a method for forming a gate insulating film.
MOS型半導体装置は高集積化・高性能化・多機能化を
目指して開発が進められており、MOS型トランジスタ特
性に対する要求も多種多様となり、二種類のゲート酸化
膜厚を持ったMOS型トランジスタへの要求（公開昭62-25
6476）もその一例である。MOS type semiconductor devices are being developed with the aim of high integration, high performance, and multi-functionality, and the requirements for MOS type transistor characteristics are also diverse, and MOS type transistors with two types of gate oxide film thicknesses Request to the public (Publication 62-25
6476) is one example.
従来、二種類のゲート酸化膜厚をもったMOS型半導体
装置の製造方法は第２図に示す様になっていた。以下、
第２図を用いて従来例について説明を行なう。まず、第
２図（ａ）に示す様に一導電型半導体基板１上に素子分
離絶縁膜２を有する素子分離領域と第１の酸化膜３を有
する素子領域を形成する。続いて、第２図（ｂ）に示す
様にフォトレジスト４を用いて第１の酸化膜３を選択的
に例えば弗酸を用いてエッチング除去する。そして、第
２図（ｃ）に示す様にフォトレジスト４を除去して熱酸
化法により第２の酸化膜５を形成する。この時に第１の
酸化膜３は厚くなり３′となる。この後、第２図（ｄ）
に示す様に多結晶シリコンより成るゲート電極10を形成
し、続いて、第２図（ｅ）に示す様にソース及びドレイ
ンとなる拡散層11を形成し、層間絶縁膜12を形成し、コ
ンタクト孔を形成し配線電極13を形成し、保護膜として
カバー絶縁膜14を形成する。Conventionally, a method of manufacturing a MOS type semiconductor device having two types of gate oxide film thickness has been shown in FIG. Less than,
A conventional example will be described with reference to FIG. First, as shown in FIG. 2A, an element isolation region having an element isolation insulating film 2 and an element region having a first oxide film 3 are formed on a semiconductor substrate 1 of one conductivity type. Subsequently, as shown in FIG. 2B, the first oxide film 3 is selectively removed by etching using, for example, hydrofluoric acid using a photoresist 4. Then, as shown in FIG. 2C, the photoresist 4 is removed, and a second oxide film 5 is formed by a thermal oxidation method. At this time, the first oxide film 3 becomes thick and becomes 3 '. Thereafter, FIG. 2 (d)
As shown in FIG. 2, a gate electrode 10 made of polycrystalline silicon is formed. Subsequently, as shown in FIG. 2 (e), a diffusion layer 11 serving as a source and a drain is formed, an interlayer insulating film 12 is formed, and a contact is formed. A hole is formed, a wiring electrode 13 is formed, and a cover insulating film 14 is formed as a protective film.
この従来のMOS型半導体装置の製造方法では、第２の
酸化膜を熱酸化法により形成する時に、第１の酸化膜が
熱酸化に晒されて酸化され、膜厚が厚くなり以下の様な
問題が生じていた。In this conventional method for manufacturing a MOS type semiconductor device, when the second oxide film is formed by a thermal oxidation method, the first oxide film is exposed to thermal oxidation and oxidized, and the film thickness becomes thicker as follows. There was a problem.
第１の酸化膜厚は第２の酸化膜厚に左右され、膜厚
を独立に設定出来ない。即ち、第１の酸化膜厚は第２の
酸化膜形成後に所望の膜厚にならなければならないの
で、第２の酸化膜厚を考慮に入れて前もって形成する膜
厚を調整しておかなければならない。また、もし第２の
酸化膜厚を変える時には前もって形成する膜厚をも変え
なければ第１の酸化膜厚も変わってしまう。The first oxide film thickness depends on the second oxide film thickness, and cannot be set independently. That is, since the first oxide film thickness must be a desired film thickness after the formation of the second oxide film, the film thickness to be formed must be adjusted in advance in consideration of the second oxide film thickness. No. If the thickness of the second oxide film is changed, the thickness of the first oxide film also changes unless the thickness of the film formed in advance is changed.
第１の酸化膜は２度の酸化により形成される為、膜
厚のバラツキが１度の形成よりも増大してしまう。Since the first oxide film is formed by the two oxidations, the variation in the film thickness is larger than that of the first oxide film.
一導電型半導体基板上に素子領域及び素子分離領域を
形成する工程と、素子領域に熱酸化法によりゲート絶縁
膜となる第１の酸化膜を形成する工程と、窒素又はアン
モニア雰囲気中で熱処理を行ない全面を窒化した後に熱
酸化を行なう工程と、フォトエッチング技術により所定
の領域の窒化された第１の酸化膜を除去し、熱酸化法に
より窒化された第１の酸化膜をマスクとして所定の領域
にゲート絶縁膜となる第２の酸化膜を形成する工程と、
多結晶シリコン膜より成るゲート電極を形成する工程と
を有する事、若しくは、一導電型半導体基板上に素子領
域及び素子分離領域を形成する工程と、素子領域に熱酸
化法によりゲート絶縁膜となる第１の酸化膜を形成する
工程と、フォトエッチング技術により所定の素子領域の
第１の酸化膜の一部を除去し熱酸化法によりゲート絶縁
膜となる第２の酸化膜を形成する工程と、窒素又はアン
モニア雰囲気中で熱処理を行ない全面を窒化した後に熱
酸化を行なう工程と、フォトエッチング技術により所定
の領域の窒化された第１の酸化膜を除去し熱酸化法によ
り窒化された第１の酸化膜及び窒化された第２の酸化膜
をマスクとして所定の領域にゲート絶縁膜となる第３の
酸化膜を形成する工程と、多結晶シリコン膜より成るゲ
ート電極を形成する工程とを有する事、若しくは、一導
電型半導体基板上に素子領域及び素子分離領域を形成す
る工程と、素子領域にゲート絶縁膜となる第１の酸化膜
を形成する工程と、所定の領域に浮遊ゲート電極となる
第１の多結晶シリコン膜を形成する工程と、熱酸化法に
より第１の多結晶シリコン膜上に第２の酸化膜を形成
し、窒素又はアンモニア雰囲気中で熱処理を行ない全面
を窒化した後に熱酸化を行なう工程と、フォトエッチン
グ技術により所定の素子領域の窒化された第１の酸化膜
を除去し、熱酸化法により窒化された第２の酸化膜をマ
スクとして所定の領域にゲート絶縁膜となる第３の酸化
膜を形成する工程と、第２の多結晶シリコン膜より成る
ゲート電極を形成する工程とを有する事、若しくは、一
導電型半導体基板上に素子領域及び素子分離領域を形成
する工程と、素子領域に熱酸化法によりゲート絶縁膜と
なる第１の酸化膜を形成する工程と、所定の領域に前記
一導電型半導体基板と逆導電型の拡散層を形成する工程
と、フォトエッチング技術により拡散層上に第１の酸化
膜の一部を除去し熱酸化法によりゲート絶縁膜となる第
２の酸化膜を形成する工程と、窒素又はアンモニア雰囲
気中で熱処理を行ない全面を窒化した後に熱酸化を行な
う工程と、所定の領域に浮遊ゲート電極となる第１の多
結晶シリコン膜を形成する工程と熱酸化法により第１の
多結晶シリコン膜上に第３の酸化膜を形成し、窒素又は
アンモニア雰囲気中で熱処理を行ない全面を窒化した後
に熱酸化を行なう工程と、フォトエッチング技術により
所定の素子領域の窒化された第１の酸化膜を除去し、熱
酸化法により窒化された第３の酸化膜をマスクとして所
定の領域にゲート絶縁膜となる第３の酸化膜を形成する
工程と、第２の多結晶シリコン膜より成るゲート電極を
形成する工程とを有する。Forming a device region and a device isolation region on the one conductivity type semiconductor substrate, forming a first oxide film serving as a gate insulating film in the device region by a thermal oxidation method, and performing heat treatment in a nitrogen or ammonia atmosphere. Performing a thermal oxidation process after nitriding the entire surface, removing the nitrided first oxide film in a predetermined region by a photoetching technique, and using the first oxide film nitrided by the thermal oxidation method as a mask, Forming a second oxide film serving as a gate insulating film in the region;
Forming a gate electrode made of a polycrystalline silicon film, or forming an element region and an element isolation region on a semiconductor substrate of one conductivity type, and forming a gate insulating film in the element region by a thermal oxidation method. A step of forming a first oxide film, a step of removing a part of the first oxide film in a predetermined element region by a photo-etching technique, and forming a second oxide film to be a gate insulating film by a thermal oxidation method Heat-treating in a nitrogen or ammonia atmosphere to perform thermal oxidation after nitriding the entire surface; and removing the nitrided first oxide film in a predetermined region by a photo-etching technique and nitriding by a thermal oxidation method. Forming a third oxide film serving as a gate insulating film in a predetermined region using the oxide film and the nitrided second oxide film as masks, and forming a gate electrode made of a polycrystalline silicon film Or a step of forming an element region and an element isolation region on a semiconductor substrate of one conductivity type, a step of forming a first oxide film serving as a gate insulating film in the element region, Forming a first polycrystalline silicon film to be a floating gate electrode, forming a second oxide film on the first polycrystalline silicon film by a thermal oxidation method, and performing heat treatment in a nitrogen or ammonia atmosphere; Performing a thermal oxidation after nitriding, and removing a nitrided first oxide film in a predetermined element region by a photo-etching technique, and using a second oxide film nitrided by a thermal oxidation method as a mask in a predetermined region. Forming a third oxide film serving as a gate insulating film, and forming a gate electrode formed of a second polycrystalline silicon film, or forming an element region and a device on a one-conductivity type semiconductor substrate. A step of forming an isolation region, a step of forming a first oxide film serving as a gate insulating film in a device region by a thermal oxidation method, and forming a diffusion layer of the opposite conductivity type to the one conductivity type semiconductor substrate in a predetermined region Forming a second oxide film to be a gate insulating film by removing a part of the first oxide film on the diffusion layer by a photo-etching technique, and performing a heat treatment in a nitrogen or ammonia atmosphere. Performing a thermal oxidation after nitriding the entire surface, forming a first polycrystalline silicon film to be a floating gate electrode in a predetermined region, and forming a third polycrystalline silicon film on the first polycrystalline silicon film by a thermal oxidation method. Forming a silicon oxide film, performing a heat treatment in a nitrogen or ammonia atmosphere, nitriding the entire surface and then performing thermal oxidation, and removing the nitrided first oxide film in a predetermined element region by a photoetching technique. acid Forming a third oxide film serving as a gate insulating film in a predetermined region using the third oxide film nitrided by the chemical method as a mask, and forming a gate electrode made of a second polycrystalline silicon film. Having.
次に本発明について図面を参照して説明する。第１図
は本発明の一実施例の断面図である。まず、一導電型半
導体基板１上に素子分離絶縁膜２を有する素子分離領域
と第１の酸化膜３を有する素子領域とを形成する。第１
の酸化膜３としては、例えば800℃〜1150℃の熱酸化に
より100Å〜500Å程度の膜厚を形成する（第１図
（ａ））。続いて、窒素ガス雰囲気又はアンモニアガス
雰囲気で熱処理を行ない全面を窒化する。窒化の時の温
度は窒素ガス雰囲気の場合は1000℃〜1200℃，アンモニ
アガス雰囲気の場合は900℃〜1150℃で行なう。その後
に、膜質の均質化の為に熱酸化を例えば800℃〜1150℃
で行なう（第１図（ｂ））。そして、フォトレジスト４
を用いて選択的に、窒化された第１の酸化膜６を例えば
弗酸を用いて除去する（第１図（ｃ））。それから、第
２の酸化膜５を例えば800℃〜1150℃の熱酸化により100
Å〜500Å程度形成する。この時窒化された第１の酸化
膜６はほとんど酸化されず膜厚の増大は無い（第１図
（ｄ））。そして多結晶シリコン膜から成るゲート電極
10を形成し（第１図（ｅ））。ソース及びドレインとな
る拡散層11を形成し、層間絶縁膜12を形成し、コンタク
ト孔を形成して配線電極13を形成し、保護膜としてカバ
ー絶縁膜14を形成する（第１図（ｆ））。Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of one embodiment of the present invention. First, an element isolation region having an element isolation insulating film 2 and an element region having a first oxide film 3 are formed on a semiconductor substrate 1 of one conductivity type. First
The oxide film 3 is formed to a thickness of about 100 ° to 500 ° by, for example, thermal oxidation at 800 ° C. to 1150 ° C. (FIG. 1A). Subsequently, heat treatment is performed in a nitrogen gas atmosphere or an ammonia gas atmosphere to nitride the entire surface. Nitriding is performed at a temperature of 1000 ° C. to 1200 ° C. in a nitrogen gas atmosphere and 900 ° C. to 1150 ° C. in an ammonia gas atmosphere. After that, thermal oxidation is performed, for example, at 800 ° C to 1150 ° C to homogenize the film quality.
(FIG. 1 (b)). And photoresist 4
The nitrided first oxide film 6 is selectively removed using, for example, hydrofluoric acid (FIG. 1C). Then, the second oxide film 5 is subjected to thermal oxidation at, for example, 800 ° C. to 1150 ° C. for 100 seconds.
It forms about Å ~ 500Å. At this time, the nitrided first oxide film 6 is hardly oxidized and there is no increase in film thickness (FIG. 1 (d)). And a gate electrode made of a polycrystalline silicon film
10 is formed (FIG. 1 (e)). A diffusion layer 11 serving as a source and a drain is formed, an interlayer insulating film 12 is formed, a contact hole is formed, a wiring electrode 13 is formed, and a cover insulating film 14 is formed as a protective film (FIG. 1 (f)). ).
また、本発明の他の実施例の断面図を第３図に示す。
まず、一導電型半導体基板１上に素子分離絶縁膜２を有
する素子分離領域と第１の酸化膜３を有する素子領域を
形成し、第１の酸化膜３としては例えば800℃〜1150℃
の熱酸化により100Å〜400Å程度形成する（第３図
（ａ））。続いて、フォトレジスト４を用いて選択的に
第１の酸化膜３を例えば弗酸によりエッチング除去し
（第３図（ｂ））、フォトレジスタ４を除去した後に第
２の酸化膜５を例えば800℃〜1150℃の熱酸化により50
Å〜200Å程度形成する。この時には、第１の酸化膜３
も熱酸化に晒されるので膜厚が厚くなり３′となる（第
３図（ｃ））。こうして素子領域に厚くなった第１の酸
化膜３′と第２の酸化膜５の二種類の酸化膜を形成した
後に、窒素ガス雰囲気又はアンモニアガス雰囲気で熱処
理を行ない全面を窒化する。窒化の時の温度は窒素ガス
雰囲気の場合は1000℃〜1200℃、アンモニアガス雰囲気
の場合は900℃〜1150℃で行なう。その後に膜質の均質
化の為に熱酸化を例えば800℃〜1150℃で行なう（第３
図（ｄ））。そして、フォトレジスト８を用いて選択的
に、窒化された第１の酸化膜６を例えば弗酸を用いて除
去する（第３図（ｅ））。それから、第３の酸化膜９を
例えば800℃〜1150℃の熱酸化により100Å〜500Å程度
形成する。この時、窒化された第１の酸化膜６及び窒化
された第２の酸化膜７はほとんど酸化されず膜厚の増大
は無い（第３図（ｆ））。そして多結晶シリコン膜から
成るゲート電極10を形成し（第３図（ｇ））、ソース及
びドレインとなる拡散層11を形成し、層間絶縁膜12を形
成し、コンタクト孔を形成し配線電極13を形成し、保護
膜としてカバー絶縁膜14を形成する（第３図
（（ｈ））。FIG. 3 is a sectional view of another embodiment of the present invention.
First, an element isolation region having an element isolation insulating film 2 and an element region having a first oxide film 3 are formed on a semiconductor substrate 1 of one conductivity type, and the first oxide film 3 is formed, for example, at 800 ° C. to 1150 ° C.
Is formed by thermal oxidation of about 100 ° to 400 ° (FIG. 3 (a)). Subsequently, the first oxide film 3 is selectively removed by etching using, for example, hydrofluoric acid using a photoresist 4 (FIG. 3B), and after the photoresist 4 is removed, the second oxide film 5 is removed, for example. 50 by thermal oxidation between 800 ℃ and 1150 ℃
It forms about Å ~ 200Å. At this time, the first oxide film 3
Is also exposed to thermal oxidation, so that the film thickness is increased to 3 '(FIG. 3 (c)). After the two types of oxide films, ie, the first oxide film 3 'and the second oxide film 5, which are thickened in the element region, are formed, a heat treatment is performed in a nitrogen gas atmosphere or an ammonia gas atmosphere, and the entire surface is nitrided. The temperature for nitriding is 1000 to 1200 ° C. in a nitrogen gas atmosphere, and 900 to 1150 ° C. in an ammonia gas atmosphere. Thereafter, thermal oxidation is performed at, for example, 800 ° C. to 1150 ° C. in order to homogenize the film quality (No. 3).
Figure (d). Then, the nitrided first oxide film 6 is selectively removed using the photoresist 8 using, for example, hydrofluoric acid (FIG. 3E). Then, a third oxide film 9 is formed by thermal oxidation at, for example, 800 ° C. to 1150 ° C., for about 100 ° to 500 °. At this time, the nitrided first oxide film 6 and the nitrided second oxide film 7 are hardly oxidized and there is no increase in film thickness (FIG. 3 (f)). Then, a gate electrode 10 made of a polycrystalline silicon film is formed (FIG. 3 (g)), a diffusion layer 11 serving as a source and a drain is formed, an interlayer insulating film 12 is formed, a contact hole is formed, and a wiring electrode 13 is formed. Is formed, and a cover insulating film 14 is formed as a protective film (FIG. 3 (h)).
また、本発明の他の実施例の断面図を第４図に示す。
まず、一導電型半導体基板１上に素子分離絶縁膜２を有
する素子分離領域と第１の酸化膜３を有する素子領域を
形成し、第１の酸化膜３としては例えば800℃〜1150℃
の熱酸化により100Å〜400Å程度形成し、全面に不純
物、例えば燐を含有した第１の多結晶シリコン膜15′を
形成する（第４図（ａ））。続いて、フォトレジスト４
を用いて選択的に浮遊ゲート電極15を形成し（第４図
（ｂ）全）、フォトレジスト４を除去した後に第２の酸
化膜５を例えば800℃〜1150℃の熱酸化により50Å〜200
Å程度形成する。この時には、浮遊ゲート電極15に覆わ
れていない領域の第１の酸化膜３も熱酸化に晒されるの
で膜厚が厚くなり３′となる（第３図（ｃ））。FIG. 4 shows a sectional view of another embodiment of the present invention.
First, an element isolation region having an element isolation insulating film 2 and an element region having a first oxide film 3 are formed on a semiconductor substrate 1 of one conductivity type, and the first oxide film 3 is formed, for example, at 800 ° C. to 1150 ° C.
A first polycrystalline silicon film 15 'containing impurities, for example, phosphorus, is formed on the entire surface by thermal oxidation (FIG. 4 (a)). Then, photoresist 4
The floating gate electrode 15 is selectively formed by using (FIG. 4 (b)), and after removing the photoresist 4, the second oxide film 5 is subjected to thermal oxidation at, for example, 800.degree.
Å formed. At this time, the first oxide film 3 in the region not covered by the floating gate electrode 15 is also exposed to the thermal oxidation, so that the film thickness is increased to 3 '(FIG. 3 (c)).
こうして浮遊ゲート電極15上に第２の酸化膜５を形成
した後に窒素ガス雰囲気又はアンモニアガス雰囲気で熱
処理を行ない全面を窒化する。窒化の時の温度は窒素ガ
ス雰囲気の場合は1000℃〜1200℃で、アンモニアガス雰
囲気の場合は窒素ガス雰囲気の場合よりも反応性が高い
ので多少低めの900℃〜1150℃で行なう。その後に、窒
化された酸化膜の膜質の均質化の為に熱酸化を例えば80
0℃〜1150℃で行なう（第４図（ｄ））。そして、フォ
トレジスト８を用いて選択的に、窒化された第１の酸化
膜６を例えば弗酸を用いて除去する（第４図（ｅ））。
それから、第３の酸化膜９を例えば800℃〜1150℃の熱
酸化により100Å〜500Å程度形成する。この時、窒化さ
れた第２の酸化膜７はほとんど酸化されず膜厚の増大は
無い（第４図（ｆ））。そして、不純物、例えば燐を含
有する第２の多結晶シリコン膜10′を形成し（第４図
（ｇ））、公知のフォトリソグラフィー技術を用いてゲ
ート電極10を形成し（第４図（ｈ））、ソース及びドレ
インとなる拡散層11を形成し、層間絶縁膜12を形成し、
コンタクト孔を形成して配線電極13を形成し、保護膜と
してカバー絶縁膜14を形成する（第４図（ｉ））。After forming the second oxide film 5 on the floating gate electrode 15 in this manner, heat treatment is performed in a nitrogen gas atmosphere or an ammonia gas atmosphere, and the entire surface is nitrided. The temperature at the time of nitriding is 1000 ° C. to 1200 ° C. in the case of a nitrogen gas atmosphere, and is slightly lower in the case of an ammonia gas atmosphere because it has higher reactivity than in the case of a nitrogen gas atmosphere. Thereafter, thermal oxidation is performed, for example, for 80 hours to homogenize the film quality of the nitrided oxide film.
Perform at 0 ° C. to 1150 ° C. (FIG. 4 (d)). Then, the nitrided first oxide film 6 is selectively removed using a photoresist 8 using, for example, hydrofluoric acid (FIG. 4E).
Then, a third oxide film 9 is formed by thermal oxidation at, for example, 800 ° C. to 1150 ° C., for about 100 ° to 500 °. At this time, the nitrided second oxide film 7 is hardly oxidized and there is no increase in the film thickness (FIG. 4 (f)). Then, a second polycrystalline silicon film 10 'containing an impurity, for example, phosphorus is formed (FIG. 4 (g)), and a gate electrode 10 is formed using a known photolithography technique (FIG. 4 (h)). )), Forming a diffusion layer 11 serving as a source and a drain, forming an interlayer insulating film 12,
A contact hole is formed to form a wiring electrode 13, and a cover insulating film 14 is formed as a protective film (FIG. 4 (i)).
また、本発明の他の実施例の断面図を第５図に示す。
まず、一導電型半導体基板１上に素子分離絶縁膜２を有
する素子分離領域と第１の酸化膜３を有する素子領域を
形成し、素子領域の所定の領域に一導電型半導体基板１
と逆導電型の不純物をイオン注入法により導入し、熱処
理を例えば800℃〜1150℃で行ない、書込み拡散層16を
形成する。例えば、一導電型半導体基板１がＰ型の時に
は不純物として燐又は砒素を用いる（第５図（ａ））。
続いて、公知のフォトエッチング技術を用いて、書込み
拡散層16上の第１の酸化膜３を一部、例えば弗酸により
エッチング除去して書込み拡散層16の表面を露出させた
後に、第２の酸化膜５を例えば700℃〜1100℃の熱酸化
により50Å〜150Å程度形成する。（第５図（ｂ））。
この後、窒素ガス雰囲気又はアンモニアガス雰囲気で熱
処理を行ない全面を窒化する。窒化の時の温度は窒素ガ
ス雰囲気の場合は1000℃〜1200℃、アンモニアガス雰囲
気の場合は窒素ガス雰囲気の場合よりも反応性が高いの
で、多少低めの900℃〜1150℃で行なう。その後、窒化
された酸化膜の膜厚の均質化の為に熱酸化を例えば800
℃〜1150℃で行なう（第５図（ｃ））。そして、不純
物、例えば燐を含有した多結晶シリコン膜より成る浮遊
ゲート電極15を所定の領域に形成する（第５図
（ｄ））。そして、第３図の酸化膜９を例えば800℃〜1
150℃の熱酸化により50Å〜200Å程度形成する。この時
には、素子領域上の第１の酸化膜３は窒化されて窒化さ
れた第１の酸化膜６となっている為、熱酸化による膜厚
の増大は無い（第５図（ｅ））。そして、全面を再度、
窒素ガス雰囲気又はアンモニアガス雰囲気で熱処理して
窒化を行い、続いて熱酸化を行なう。この時の窒化の温
度及び熱酸化の温度は、窒素ガス雰囲気の窒化の場合は
1000℃〜1200℃で、アンモニアガス雰囲気の場合は900
℃〜1150℃で、熱酸化は800℃〜1150℃で行なう（第５
図（ｆ））。そして、フォトレジスト４を用いて選択的
に、窒化された第１の酸化膜６を例えば、弗酸を用いて
除去する（第５図（ｇ））。それから、第４の酸化膜18
を例えば800℃〜1150℃の熱酸化により100Å〜500Å程
度形成する。この時、窒化された第３の酸化膜17はほと
んど酸化されず膜厚の増大は無い（第５図（ｈ））。そ
して、不純物、例えば、燐を含有する第２の多結晶シリ
コン膜によりゲート電極10を形成し（第５図（ｉ））、
ソース及びドレインとなる拡散層11を形成し、層間絶縁
膜12を形成し、コンタクト孔を形成して配線電極13を形
成し、保護膜としてカバー絶縁膜14を形成する（第５図
（ｊ））。FIG. 5 shows a sectional view of another embodiment of the present invention.
First, an element isolation region having an element isolation insulating film 2 and an element region having a first oxide film 3 are formed on a semiconductor substrate 1 of one conductivity type.
Then, a heat treatment is performed at, for example, 800 ° C. to 1150 ° C. to form the write diffusion layer 16. For example, when the one-conductivity-type semiconductor substrate 1 is P-type, phosphorus or arsenic is used as an impurity (FIG. 5A).
Subsequently, the first oxide film 3 on the write diffusion layer 16 is partially removed by, for example, hydrofluoric acid to expose the surface of the write diffusion layer 16 using a known photoetching technique. Oxide film 5 is formed by thermal oxidation at, for example, 700.degree. C. to 1100.degree. (FIG. 5 (b)).
Thereafter, heat treatment is performed in a nitrogen gas atmosphere or an ammonia gas atmosphere, and the entire surface is nitrided. Nitriding is performed at a temperature of 1000 ° C. to 1200 ° C. in a nitrogen gas atmosphere, and at a somewhat lower temperature of 900 ° C. to 1150 ° C. in an ammonia gas atmosphere because the reactivity is higher than in a nitrogen gas atmosphere. Thereafter, thermal oxidation is performed, for example, for 800 hours to homogenize the thickness of the nitrided oxide film.
C. to 1150.degree. C. (FIG. 5 (c)). Then, a floating gate electrode 15 made of a polycrystalline silicon film containing an impurity, for example, phosphorus is formed in a predetermined region (FIG. 5D). Then, the oxide film 9 of FIG.
Formed at about 50-200 ° by thermal oxidation at 150 ° C. At this time, the first oxide film 3 on the element region is a nitrided first oxide film 6, so that there is no increase in film thickness due to thermal oxidation (FIG. 5 (e)). And the whole surface again,
Heat treatment is performed in a nitrogen gas atmosphere or an ammonia gas atmosphere to perform nitriding, and then thermal oxidation is performed. The nitriding temperature and thermal oxidation temperature at this time are as follows in the case of nitriding in a nitrogen gas atmosphere.
1000 ° C to 1200 ° C, 900 for ammonia gas atmosphere
C. to 1150.degree. C. and thermal oxidation at 800.degree. C. to 1150.degree.
Figure (f). Then, the nitrided first oxide film 6 is selectively removed using the photoresist 4 using, for example, hydrofluoric acid (FIG. 5 (g)). Then, the fourth oxide film 18
Is formed by thermal oxidation at, for example, 800 ° C. to 1150 ° C. to have a thickness of about 100 ° to 500 °. At this time, the nitrided third oxide film 17 is hardly oxidized, and there is no increase in the film thickness (FIG. 5 (h)). Then, a gate electrode 10 is formed from a second polycrystalline silicon film containing an impurity, for example, phosphorus (FIG. 5 (i)).
A diffusion layer 11 serving as a source and a drain is formed, an interlayer insulating film 12 is formed, a contact hole is formed, a wiring electrode 13 is formed, and a cover insulating film 14 is formed as a protective film (FIG. 5 (j)). ).
以上説明したように本発明は、ゲート酸化膜を形成し
た後に、窒素ガス雰囲気又はアンモニアガス雰囲気で熱
処理を行なってゲート酸化膜を窒化しているので、ゲー
ト酸化膜が耐酸化性を持ち、その後の熱酸化に晒されて
も膜厚が変化しないという効果を有する。As described above, in the present invention, after forming the gate oxide film, the gate oxide film is nitrided by performing a heat treatment in a nitrogen gas atmosphere or an ammonia gas atmosphere, so that the gate oxide film has oxidation resistance. Has the effect that the film thickness does not change even if it is exposed to thermal oxidation.
即ち、最初のゲート酸化膜厚を、後の熱酸化によって
形成されるゲート酸化膜と全く独立に設定出来、従来、
２度の酸化により形成されていたゲート酸化膜を１度で
形成出来る様になるので膜厚のバラツキを小さく出来
る。That is, the initial gate oxide film thickness can be set completely independently of the gate oxide film formed by the subsequent thermal oxidation.
Since the gate oxide film formed by the two oxidations can be formed at one time, the variation in the film thickness can be reduced.
第１図は本考案の一実施例の断面図。第２図は従来例の
断面図。第３図は本発明の他の一実施例の断面図、第４
図は本発明の他の一実施例の断面図、第５図は本発明の
他の一実施例の断面図。 １……一導電型半導体基板、２……素子分離絶縁膜、３
……第１の酸化膜、３′……厚くなった第１の酸化膜、
4,8……フォトレジスト、５……第２の酸化膜、６……
窒化された第１の酸化膜、７……窒化された第２の酸化
膜、９……第３の酸化膜、17……窒化された第３の酸化
膜、10′……第２の多結晶シリコン膜、10……ゲート電
極、11……拡散層、12……層間絶縁膜、13……配線電
極、14……カバー絶縁膜、15′……第１の多結晶シリコ
ン膜、15……浮遊ゲート電極、16……書込み拡散層、18
……第４の酸化膜。FIG. 1 is a sectional view of one embodiment of the present invention. FIG. 2 is a sectional view of a conventional example. FIG. 3 is a sectional view of another embodiment of the present invention, and FIG.
FIG. 5 is a sectional view of another embodiment of the present invention, and FIG. 5 is a sectional view of another embodiment of the present invention. 1 ... one conductivity type semiconductor substrate, 2 ... element isolation insulating film, 3
... a first oxide film, 3 '... a thickened first oxide film,
4,8 ... photoresist, 5 ... second oxide film, 6 ...
Nitrided first oxide film, 7... Nitrided second oxide film, 9... Third oxide film, 17... Nitrided third oxide film, 10 ′. Crystal silicon film, 10 gate electrode, 11 diffusion layer, 12 interlayer insulating film, 13 wiring electrode, 14 cover insulating film, 15 'first polycrystalline silicon film, 15 … Floating gate electrode, 16 …… Write diffusion layer, 18
... Fourth oxide film.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/792 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical display location H01L 29/792
Claims (4)
分離領域を形成する工程と、前記素子領域に熱酸化法に
よりゲート絶縁膜となる第１の酸化膜を形成する工程
と、窒素又はアンモニア雰囲気中で熱処理を行ない全面
を窒化した後に熱酸化を行なう工程と、フォトエッチン
グ技術により所定の領域の窒化された前記第１の酸化膜
を除去し、熱酸化法により前記窒化された前記第１の酸
化膜をマスクとして所定の領域にゲート絶縁膜となる第
２の酸化膜を形成する工程と、多結晶シリコン膜より成
るゲート電極を形成する工程とを有する事を特徴とする
MOS型半導体装置の製造方法。A step of forming an element region and an element isolation region on a semiconductor substrate of one conductivity type; a step of forming a first oxide film serving as a gate insulating film in the element region by a thermal oxidation method; Performing a heat treatment in an ammonia atmosphere and nitriding the entire surface, and then performing a thermal oxidation; removing the nitrided first oxide film in a predetermined region by a photoetching technique; A step of forming a second oxide film serving as a gate insulating film in a predetermined region using the first oxide film as a mask; and a step of forming a gate electrode made of a polycrystalline silicon film.
A method for manufacturing a MOS type semiconductor device.
分離領域を形成する工程と、前記素子領域に熱酸化法に
よりゲート絶縁膜となる第１の酸化膜を形成する工程
と、フォトエッチング技術により所定の前記素子領域の
前記第１の酸化膜の一部を除去し熱酸化法によりゲート
絶縁膜となる第２の酸化膜を形成する工程と、窒素又は
アンモニア雰囲気中で熱処理を行ない全面を窒化した後
に熱酸化を行なう工程と、フォトエッチング技術により
所定の領域の窒化された前記第１の酸化膜を除去し熱酸
化法により前記窒化された前記第１の酸化膜及び窒化さ
れた前記第２の酸化膜をマスクとして所定の領域にゲー
ト絶縁膜となる第３の酸化膜を形成する工程と、多結晶
シリコン膜より成るゲート電極を形成する工程とを有す
る事を特徴とするMOS型半導体装置の製造方法。A step of forming an element region and an element isolation region on a semiconductor substrate of one conductivity type; a step of forming a first oxide film serving as a gate insulating film in the element region by a thermal oxidation method; Forming a second oxide film to be a gate insulating film by a thermal oxidation method by removing a part of the first oxide film in a predetermined element region by a technique; and performing heat treatment in a nitrogen or ammonia atmosphere. Performing a thermal oxidation after nitriding, and removing the nitrided first oxide film in a predetermined region by a photo-etching technique, and nitriding the first oxide film and the nitrided A MOS having a step of forming a third oxide film serving as a gate insulating film in a predetermined region using the second oxide film as a mask, and a step of forming a gate electrode made of a polycrystalline silicon film. The method of manufacturing a semiconductor device.
分離領域を形成する工程と、前記素子領域にゲート絶縁
膜となる第１の酸化膜を形成する工程と、所定の領域に
浮遊ゲート電極となる第１の多結晶シリコン膜を形成す
る工程と、熱酸化法により前記第１の多結晶シリコン膜
上に第２の酸化膜を形成し、窒素又はアンモニア雰囲気
中で熱処理を行ない全面を窒化した後に熱酸化を行なう
工程と、フォトエッチング技術により所定の前記素子領
域の窒化された第１の酸化膜を除去し、熱酸化法により
前記窒化された第２の酸化膜をマスクとして所定の領域
にゲート絶縁膜となる第３の酸化膜を形成する工程と、
第２の多結晶シリコン膜より成るゲート電極を形成する
工程とを有する事を特徴とするMOS型半導体装置の製造
方法。3. A step of forming an element region and an element isolation region on a semiconductor substrate of one conductivity type, a step of forming a first oxide film serving as a gate insulating film in the element region, and a step of forming a floating gate in a predetermined region. Forming a first polycrystalline silicon film serving as an electrode, forming a second oxide film on the first polycrystalline silicon film by a thermal oxidation method, and performing a heat treatment in a nitrogen or ammonia atmosphere to cover the entire surface; Performing a thermal oxidation after nitriding; removing a nitrided first oxide film in the predetermined element region by a photo-etching technique; and performing a predetermined oxidation using the nitrided second oxide film as a mask by a thermal oxidation method Forming a third oxide film to be a gate insulating film in the region;
Forming a gate electrode made of a second polycrystalline silicon film.
分離領域を形成する工程と、前記素子領域に熱酸化法に
よりゲート絶縁膜となる第１の酸化膜を形成する工程
と、所定の領域に前記一導電型半導体基板と逆導電型の
拡散層を形成する工程と、フォトエッチング技術により
前記拡散層上に前記第１の酸化膜の一部を除去し熱酸化
法によりゲート絶縁膜となる第２の酸化膜を形成する工
程と、窒素又はアンモニア雰囲気中で熱処理を行ない全
面を窒化した後に熱酸化を行なう工程と、所定の領域に
浮遊ゲート電極となる第１の多結晶シリコン膜を形成す
る工程とを有する事を特徴とする第３項記載のMOS型半
導体装置の製造方法。A step of forming an element region and an element isolation region on a semiconductor substrate of one conductivity type; a step of forming a first oxide film serving as a gate insulating film in said element region by a thermal oxidation method; Forming a diffusion layer of the opposite conductivity type to the one conductivity type semiconductor substrate in a region, removing a part of the first oxide film on the diffusion layer by a photo etching technique, and forming a gate insulating film by a thermal oxidation method; Forming a second oxide film, performing a heat treatment in a nitrogen or ammonia atmosphere, nitriding the entire surface and then performing thermal oxidation, and forming a first polycrystalline silicon film serving as a floating gate electrode in a predetermined region. 4. The method for manufacturing a MOS semiconductor device according to claim 3, comprising a step of forming.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2340916A JP2666565B2 (en) | 1990-11-30 | 1990-11-30 | Method for manufacturing semiconductor device |
| US07/779,078 US5254489A (en) | 1990-10-18 | 1991-10-18 | Method of manufacturing semiconductor device by forming first and second oxide films by use of nitridation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2340916A JP2666565B2 (en) | 1990-11-30 | 1990-11-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04208570A JPH04208570A (en) | 1992-07-30 |
| JP2666565B2 true JP2666565B2 (en) | 1997-10-22 |
Family
ID=18341485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2340916A Expired - Lifetime JP2666565B2 (en) | 1990-10-18 | 1990-11-30 | Method for manufacturing semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP2666565B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923983A (en) * | 1996-12-23 | 1999-07-13 | Advanced Micro Devices, Inc. | Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects |
| JP3472727B2 (en) * | 1999-08-13 | 2003-12-02 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device and method of manufacturing semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582071A (en) * | 1981-06-25 | 1983-01-07 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JP2650925B2 (en) * | 1987-11-02 | 1997-09-10 | 株式会社日立製作所 | Method for manufacturing semiconductor integrated circuit device |
| JPH01170094A (en) * | 1987-12-25 | 1989-07-05 | Hitachi Ltd | Substrate packaging structure |
-
1990
- 1990-11-30 JP JP2340916A patent/JP2666565B2/en not_active Expired - Lifetime
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