JPH04154162A - Manufacture of mos-type semiconductor device - Google Patents
Manufacture of mos-type semiconductor deviceInfo
- Publication number
- JPH04154162A JPH04154162A JP2280393A JP28039390A JPH04154162A JP H04154162 A JPH04154162 A JP H04154162A JP 2280393 A JP2280393 A JP 2280393A JP 28039390 A JP28039390 A JP 28039390A JP H04154162 A JPH04154162 A JP H04154162A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- forming
- thermal oxidation
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 30
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 24
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000005121 nitriding Methods 0.000 claims abstract description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 5
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 238000005192 partition Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 9
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 abstract 1
- 239000007789 gas Substances 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
Ｊ産業上の利用分野〕
本発明は〜１０Ｓ型半導体装置の製造方法に関し、特に
ゲート絶縁膜の形成法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a ~10S type semiconductor device, and particularly to a method for forming a gate insulating film.
Ｍ ＯＳ型半導体装置は高集積化 高性能化・多機能化
を目指して開発か進められており、ＭＯ５型トランジス
タ特性に対する要求も多種多様となり、二種類のゲート
酸化膜厚を持ったＭＯ３型トランジスタへの要求もその
一例である。MOS type semiconductor devices are being developed with the aim of becoming highly integrated, high-performance, and multi-functional, and the requirements for MO5 type transistor characteristics have become diverse, and MO3 type transistors with two types of gate oxide film thickness are being developed. One example is the demand for
従来、二種類のゲート酸化膜厚を持ったＭＯ３型半導体
装置の製造方法は第２図に示す様になっていた。以下、
第２図を用いて従来例について説明を行なう。まず、第
２図（ａ＞に示す様に一導電型半導体基板１（単結晶シ
リコン基板）上に素子分離絶縁膜２を素子分離領域とし
て選択的に形成して素子領域を区画し、各素子領域に第
１の酸化膜３を形成する。続いて、第２図（ｂ）に示す
様にフォトレジスト膜４を用いて第１の酸化膜３を選択
的に例えば弗酸を用いてエツチング除去する。そして、
第２図（ｃ）に示す様にフォトレジスト膜４を除去して
熱酸化法により第２の酸化膜５を形成する。この時に第
１の酸化膜３は厚くなり３ａとなる。この後、第２図（
ｄ）に示す様に第１の酸化膜３ａ上および第２の酸化膜
５上にそれぞれ多結晶シリコンより成るゲート電極１０
ｆ！：形成し、続いて、第２図（ｅ）に示す様にソース
及びドレインとなる拡散層１１を形成し、層間絶縁Ｍ１
２を形成し、コンタクト孔を形成し、配線電極１３を形
成し、保護膜としてカバー絶縁膜１４を形成する。Conventionally, a method of manufacturing an MO3 type semiconductor device having two types of gate oxide film thickness was as shown in FIG. below,
A conventional example will be explained using FIG. First, as shown in FIG. 2 (a), an element isolation insulating film 2 is selectively formed as an element isolation region on a one-conductivity type semiconductor substrate 1 (single crystal silicon substrate) to partition element regions, and each element A first oxide film 3 is formed in the area.Next, as shown in FIG. 2(b), the first oxide film 3 is selectively etched away using, for example, hydrofluoric acid using a photoresist film 4. Then,
As shown in FIG. 2(c), the photoresist film 4 is removed and a second oxide film 5 is formed by thermal oxidation. At this time, the first oxide film 3 becomes thicker and becomes 3a. After this, Figure 2 (
As shown in d), a gate electrode 10 made of polycrystalline silicon is provided on the first oxide film 3a and the second oxide film 5, respectively.
f! Then, as shown in FIG. 2(e), a diffusion layer 11 that becomes a source and a drain is formed, and an interlayer insulation
2, a contact hole is formed, a wiring electrode 13 is formed, and a cover insulating film 14 is formed as a protective film.
この従来のＭＯ３型半導体装置の製造方法では、熱酸化
法により第２の酸化膜を形成する時に第１の酸化膜が熱
酸化に晒されて酸化され、膜厚が厚くなる為に、次の様
な問題が生じる６１、第１の酸化膜厚は第２の酸化膜厚
に左右され、膜厚を独立に設定出来ない。In this conventional method for manufacturing MO3 type semiconductor devices, when forming the second oxide film by thermal oxidation, the first oxide film is exposed to thermal oxidation and oxidized, increasing the film thickness. 61. The first oxide film thickness depends on the second oxide film thickness, and the film thickness cannot be set independently.
２、第１の酸化膜は２度の酸化により形成され、膜厚の
バラツキが増大する。2. The first oxide film is formed by oxidation twice, increasing the variation in film thickness.
３、第１の酸化膜厚は第２の酸化膜より薄くする事が出
来ない。即ち、酸化膜の形成は膜厚の厚いものから順番
にしか形成出来ないのでプロセス設計の自由度が少なく
なる。3. The thickness of the first oxide film cannot be made thinner than that of the second oxide film. That is, since oxide films can only be formed in order of thickness, the degree of freedom in process design is reduced.
本願第１の発明のＭＯ３型半導体装置の製造方法は、一
導電型半導体基板に選択的に素子分離領域を形成して素
子領域を区画する工程と、前記素子領域に熱酸化法によ
り第１の酸化膜を形成する工程と、窒素又はアンモニア
雰囲気中で熱処理を行ない全面を窒化した後に熱酸化を
行ない第１のゲート絶縁膜を形成する工程と、フォトエ
ツチング技術により所定の領域の前記第１のゲート絶縁
膜を除去し、熱酸化法により前記窒化された前記第１の
酸化膜をマスクとして所定の領域に第２のゲート絶縁膜
として第２の酸化膜を形成する工程と、前記第１のゲー
ト絶縁膜上および第２のゲート絶縁膜上にそれぞれゲー
ト電極を形成する工程とを有するというものである。A method for manufacturing an MO3 type semiconductor device according to the first invention of the present application includes a step of selectively forming an element isolation region on a semiconductor substrate of one conductivity type to define an element region, and a step of dividing the element region by a thermal oxidation method. a step of forming an oxide film; a step of performing heat treatment in a nitrogen or ammonia atmosphere to nitrid the entire surface and then performing thermal oxidation to form a first gate insulating film; removing the gate insulating film and forming a second oxide film as a second gate insulating film in a predetermined region using the nitrided first oxide film as a mask by thermal oxidation; The method includes a step of forming gate electrodes on the gate insulating film and on the second gate insulating film, respectively.
又、本願第２の発明のＭＯ３型半導体装置の製造方法は
、一導電型半導体基板に選択的に素子分離領域を形成し
て素子領域を区画する工程と、前記素子領域に熱酸化法
により第１の酸化膜を形成する工程と、フォトエツチン
グ技術により所定の前記素子領域の前記第１の酸化膜を
選択的に除去し熱酸化法により第２の酸化膜を形成する
工程と、窒素又はアンモニア雰囲気中て熱処理を行ない
全面を窒化した後に熱酸化を行ない前記素子領域に段差
のある第１のゲート絶縁膜を形成する工程と、フォトエ
ツチング技術により他の所定の素子領域の窒化された前
記第１の酸化膜を除去し熱酸化法により前記窒化された
前記第１の酸化膜及び窒化された前記第２の酸化膜をマ
スクとして前記所定の素子領域に第２のゲート絶縁膜と
して第３の酸化膜を形成する工程と、前記第１のゲート
絶縁膜上および第２のゲート絶縁膜上にそれぞれゲート
電極を形成する工程とを有するというものである。Further, the method for manufacturing an MO3 type semiconductor device according to the second invention of the present application includes a step of selectively forming an element isolation region on a semiconductor substrate of one conductivity type to define an element region, and a step of dividing the element region by a thermal oxidation method. a step of selectively removing the first oxide film in a predetermined element region by a photoetching technique and forming a second oxide film by a thermal oxidation method; and a step of forming a second oxide film by a thermal oxidation method. A step of performing heat treatment in an atmosphere to nitridize the entire surface and then performing thermal oxidation to form a first gate insulating film with steps in the element region, and a step of forming the nitrided first gate insulating film in another predetermined element region by photoetching. A third oxide film is removed as a second gate insulating film in the predetermined device region using the nitrided first oxide film and the nitrided second oxide film as masks by thermal oxidation. The method includes a step of forming an oxide film, and a step of forming gate electrodes on the first gate insulating film and the second gate insulating film, respectively.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｆ）は本願第１、発明の名称施例にお
ける工程順断面図である。FIGS. 1(a) to 1(f) are sectional views in the order of steps in the first embodiment of the present invention.
まず、第１図（ａ）に示すように一導電型半導体基板１
（単結晶シリコン基板）上に素子分離絶縁膜２を素子分
離領域として形成して素子領域を区画し、各素子領域に
第１の酸化膜３を形成する。第１の酸化膜３としては、
例えば８００℃〜１１５０°Ｃの熱酸化により１００八
〜５００八程度の膜厚で形成する。続いて、第１図（ｂ
）に示すように、窒素ガス雰囲気又はアンモニアカス雰
囲気でカーボンヒータにより短時間熱処理を行ない全面
を窒化する。窒化の時の温度は窒素ガス雰囲気の場合は
１０００℃〜１２００’Ｃ，アンモニアガス雰囲気の場
合は９００°Ｃ〜１１５０’Ｃて行なう。その後に、膜
質の均質化の為にカーボンヒータによる短時間熱酸化を
例えば８００℃〜１１５０℃で行なう。このようにして
窒化された第１の酸化膜６が第１のゲート絶縁膜として
得られる。そして、第１図（ｃ）に示すように、フォト
レジストＭ４を用いて図の右側の素子領域とその近傍の
窒化された第１の酸化膜６を例えば弗酸を用いて除去す
る。それから、第１図（ｄ）に示すように、第２の酸化
膜５を、第２のゲート絶縁膜として、例えは８００°Ｃ
〜１１５０°Ｃの短時間熱酸化により１００八〜５００
Ａ程度形成する。First, as shown in FIG. 1(a), a semiconductor substrate 1 of one conductivity type is
An element isolation insulating film 2 is formed as an element isolation region on a (single-crystal silicon substrate) to partition element regions, and a first oxide film 3 is formed in each element region. As the first oxide film 3,
For example, it is formed by thermal oxidation at 800° C. to 1150° C. to a film thickness of about 100.8 to 500.8°. Next, Figure 1 (b
), the entire surface is nitrided by heat treatment for a short time using a carbon heater in a nitrogen gas atmosphere or an ammonia scum atmosphere. The temperature during nitriding is 1000 DEG C. to 1200 DEG C. in a nitrogen gas atmosphere, and 900 DEG C. to 1150 DEG C. in an ammonia gas atmosphere. Thereafter, short-term thermal oxidation is performed using a carbon heater at, for example, 800 DEG C. to 1150 DEG C. in order to homogenize the film quality. The first oxide film 6 thus nitrided is obtained as the first gate insulating film. Then, as shown in FIG. 1(c), the element region on the right side of the figure and the nitrided first oxide film 6 in the vicinity thereof are removed using, for example, hydrofluoric acid, using the photoresist M4. Then, as shown in FIG. 1(d), the second oxide film 5 is heated to 800° C. as a second gate insulating film.
1008-500 by short-term thermal oxidation at ~1150°C
Forms about A.
この時窒化された第１の酸化膜６はほとんど酸化されず
膜厚の増大はほとんと無い。そして、第１図（ｅ）に示
すように、第１のゲート絶縁膜上および第２のゲート絶
縁膜上にそれぞれ多結晶シリコン膜からなるゲート電極
１０を形成し、第１図（ｆ）に示すように、ソース及び
トレインとなる拡散層１１を形成し、層間絶縁Ｍ１２を
形成し、コンタクト孔を形成して配線電極１３を形成し
、保護膜としてカバー絶縁膜１４と形成する。At this time, the nitrided first oxide film 6 is hardly oxidized and there is almost no increase in film thickness. Then, as shown in FIG. 1(e), a gate electrode 10 made of a polycrystalline silicon film is formed on the first gate insulating film and the second gate insulating film, respectively, and as shown in FIG. 1(f). As shown, a diffusion layer 11 serving as a source and a train is formed, an interlayer insulation M12 is formed, a contact hole is formed, a wiring electrode 13 is formed, and a cover insulating film 14 is formed as a protective film.
第１のゲート絶縁膜の厚さは第２のゲート絶縁膜の形成
工程にほとんど影響を受けないので、独立に設定するこ
とができる。The thickness of the first gate insulating film is hardly affected by the process of forming the second gate insulating film, so it can be set independently.
第３図（ａ）〜（ｄ）は本願第２の発明の一実施例にお
ける工程順断面図である。FIGS. 3(a) to 3(d) are sectional views in the order of steps in an embodiment of the second invention of the present application.
第１図（ａ）を参照して説明した工程の後に、第３図（
ａ）に示すように、フォトレジスト膜４を用いて図の左
側の素子領域上の第１の酸化膜３を、例えば弗酸により
選択的にエツチング除去し、第３図（ｂ）に示すように
、フォトレジスト膜４を除去した後に第２の酸化膜５を
例えば８００°Ｃ〜１１５０°Ｃの短時間熱酸化により
５０八〜２００Ａ程度形成する。この時には、第１の酸
化膜３も熱酸化に晒されるので膜厚が厚くなり３ａとな
る。こうして素子領域に厚くなった第１の酸化膜３ａと
第２の酸化膜５の二種類の酸化膜を形成した後に、窒素
ガス雰囲気又はアンモニアカス雰囲気で短時間熱処理を
行ない全面を窒化する。窒化の時の温度は窒素ガス雰囲
気の場合は１０００℃〜１２００℃、アンモニアガス雰
囲気の場合は９００℃〜１１５０℃で行なう。その後に
膜質の均質化の為に熱酸化を例えば８００℃〜１１５０
℃で行なう。そして、第３図（ｄ）に示すように、フォ
トレジスト膜４を用いて選択的に（図の右側の素子領域
の）、窒化された第１の酸化膜６を例えば弗酸を用いて
除去する。このようにして、図の左側の素子領域に段差
のある第１のゲート絶縁膜を形成することができる。そ
れから、第３図（ｅ）に示すように、第３の酸化膜９を
第２のゲート絶縁膜として例えば８００°Ｃ〜１１５０
°Ｃの短時間の熱酸化により１００Ａ〜５００Ａ程度形
成する。この時、窒化された第１の酸化膜６及び窒化さ
れた第２の酸化膜７はほとんど酸化されず膜厚の増大は
ほとんど無い。そして第３図（ｆ）に示すように、多結
晶シリコン膜から成るゲート電ｆｉ１０を形成し、第３
図（ｇ＞に示すように、ソース及びドレインとなる拡散
層１１を形成し、眉間絶縁１１ｇ１２を形成し、コンタ
クト孔を形成して配線電極１３を形成し、保護膜として
カバー絶縁膜１４を形成する。After the process described with reference to FIG. 1(a), the process shown in FIG.
As shown in FIG. 3(a), the first oxide film 3 on the element region on the left side of the figure is selectively etched away using, for example, hydrofluoric acid using the photoresist film 4, and as shown in FIG. 3(b). After removing the photoresist film 4, a second oxide film 5 of about 50.degree. At this time, the first oxide film 3 is also exposed to thermal oxidation, so that the film thickness increases to 3a. After two thick oxide films, the first oxide film 3a and the second oxide film 5, are formed in the element region in this manner, the entire surface is nitrided by heat treatment for a short time in a nitrogen gas atmosphere or an ammonia gas atmosphere. The temperature during nitriding is 1000°C to 1200°C in a nitrogen gas atmosphere, and 900°C to 1150°C in an ammonia gas atmosphere. After that, thermal oxidation is carried out at, for example, 800°C to 1150°C to homogenize the film quality.
Perform at ℃. Then, as shown in FIG. 3(d), the nitrided first oxide film 6 is selectively removed using the photoresist film 4 (in the device region on the right side of the figure) using, for example, hydrofluoric acid. do. In this way, a first gate insulating film having a step can be formed in the element region on the left side of the figure. Then, as shown in FIG. 3(e), the third oxide film 9 is used as a second gate insulating film and heated at a temperature of, for example, 800°C to 1150°C.
Forms about 100A to 500A by short-time thermal oxidation at °C. At this time, the nitrided first oxide film 6 and the nitrided second oxide film 7 are hardly oxidized and there is almost no increase in film thickness. Then, as shown in FIG. 3(f), a gate electrode fi10 made of a polycrystalline silicon film is formed, and a third
As shown in the figure (g>), a diffusion layer 11 serving as a source and a drain is formed, a glabellar insulation 11g12 is formed, a contact hole is formed, a wiring electrode 13 is formed, and a cover insulating film 14 is formed as a protective film. do.
この実施例では、窒化された第１の酸化膜６と窒化され
た第２の酸化膜とで段差のある第１のゲート絶縁膜を有
するＭＯＳ）−ランジスタを形成したが、これらの窒化
された酸化膜を別々の素子領域に形成すれば、ゲート絶
縁膜が異なる三種類のＭＯＳ）ランジスタを同一のシリ
コン基板に集積することができる。In this example, a MOS)-transistor having a first gate insulating film with a step between a nitrided first oxide film 6 and a nitrided second oxide film was formed. By forming oxide films in separate device regions, three types of MOS transistors with different gate insulating films can be integrated on the same silicon substrate.
二のようにして、酸化膜の形成、窒化処理、エノチンク
を適当に組合せることにより、複数のＭＯＳ）ランジス
タを形成することかてきる。そうして、これらのＭＯＳ
トランジスタのゲート絶縁膜の厚さは、互いにほぼ独立
に設定することがてきる。A plurality of MOS transistors can be formed by appropriately combining the formation of an oxide film, nitriding treatment, and etching as described in 2. Then these MOS
The thicknesses of the gate insulating films of transistors can be set almost independently from each other.
以上説明したように本発明は、酸化膜を形成した後に、
窒素カス雰囲気又はアンモニアガス雰囲気て熱処理を行
なって窒化を行なったのちに、これを耐酸化性膜として
別の酸化膜を形成することにより、窒化された酸化膜と
後に形成した酸化膜の厚さをそれぞれほぼ独立に設定す
ることができるので、ゲート絶縁膜の種類や厚さの異な
る複数のＭＯＳトランジスタを制御性よく確実に同一の
半導体基板上に集積することができるという効果がある
。As explained above, in the present invention, after forming an oxide film,
After nitriding by heat treatment in a nitrogen gas atmosphere or an ammonia gas atmosphere, this is used as an oxidation-resistant film and another oxide film is formed, thereby reducing the thickness of the nitrided oxide film and the oxide film formed later. can be set almost independently, which has the effect that a plurality of MOS transistors having different types and thicknesses of gate insulating films can be reliably integrated on the same semiconductor substrate with good controllability.
第１図（ａ）〜（ｆンは本願第１の発明の一実施例にお
ける工程順断面図、第２図（ａ）〜（ｅ）は従来例にお
ける工程順断面図、第３図（ａ）〜（ｇ＞は本願第２の
発明の一実施例の工程順段面図である。
１・・一導電型半導体基板、２・・素子分離絶縁膜、３
・・・第１の酸化膜、３ａ・・・厚くなった第１の酸化
膜、４・・フォトレジスト膜、６・・・窒化された第１
の酸化膜、７・窒化された第２の酸化膜、８・・フォト
レジスト膜、９・・・第３の酸化膜、１０・・・ゲート
電極、１１・・・拡散層、１２・・・層間絶縁膜、１３
・・配線電極、１４・・・カバー絶縁膜。1(a) to (f) are sectional views in the order of steps in an embodiment of the first invention of the present application, FIGS. 2(a) to (e) are sectional views in order of steps in the conventional example, and FIG. ) to (g> are step-by-step sectional views of an embodiment of the second invention of the present application. 1. Semiconductor substrate of one conductivity type, 2. Element isolation insulating film, 3
...First oxide film, 3a... Thickened first oxide film, 4... Photoresist film, 6... Nitrided first
oxide film, 7. nitrided second oxide film, 8.. photoresist film, 9.. third oxide film, 10.. gate electrode, 11.. diffusion layer, 12.. Interlayer insulation film, 13
...Wiring electrode, 14...Cover insulating film.
Claims (1)
して素子領域を区画する工程と、前記素子領域に熱酸化
法により第１の酸化膜を形成する工程と、窒素又はアン
モニア雰囲気中で熱処理を行ない全面を窒化した後に熱
酸化を行ない第１のゲート絶縁膜を形成する工程と、フ
ォトエッチング技術により所定の領域の前記第１のゲー
ト絶縁膜を除去し、熱酸化法により前記窒化された前記
第１の酸化膜をマスクとして所定の領域に第２のゲート
絶縁膜として第２の酸化膜を形成する工程と、前記第１
のゲート絶縁膜上および第２のゲート絶縁膜上にそれぞ
れゲート電極を形成する工程とを有する事を特徴とする
ＭＯＳ型半導体装置の製造方法。 ２、一導電型半導体基板に選択的に素子分離領域を形成
して素子領域を区画する工程と、前記素子領域に熱酸化
法により第１の酸化膜を形成する工程と、フォトエッチ
ング技術により所定の前記素子領域の前記第１の酸化膜
を選択的に除去し熱酸化法により第２の酸化膜を形成す
る工程と、窒素又はアンモニア雰囲気中で熱処理を行な
い全面を窒化した後に熱酸化を行ない前記素子領域に段
差のある第１のゲート絶縁膜を形成する工程と、フォト
エッチング技術により他の所定の素子領域の窒化された
前記第１の酸化膜を除去し熱酸化法により前記窒化され
た前記第１の酸化膜及び窒化された前記第２の酸化膜を
マスクとして前記所定の素子領域に第２のゲート絶縁膜
として第３の酸化膜を形成する工程と、前記第１のゲー
ト絶縁膜上および第２のゲート絶縁膜上にそれぞれゲー
ト電極を形成する工程とを有する事を特徴とするＭＯＳ
型半導体装置の製造方法。[Claims] 1. A step of selectively forming an element isolation region on a semiconductor substrate of one conductivity type to partition an element region, and a step of forming a first oxide film in the element region by a thermal oxidation method. , performing heat treatment in a nitrogen or ammonia atmosphere to nitrid the entire surface, and then performing thermal oxidation to form a first gate insulating film; and removing the first gate insulating film in a predetermined region by photo-etching technology; forming a second oxide film as a second gate insulating film in a predetermined region using the nitrided first oxide film as a mask by a thermal oxidation method;
1. A method for manufacturing a MOS type semiconductor device, comprising the step of forming gate electrodes on a gate insulating film and a second gate insulating film, respectively. 2. A step of selectively forming an element isolation region on a semiconductor substrate of one conductivity type to partition the element region, a step of forming a first oxide film in the element region by a thermal oxidation method, and a step of forming a first oxide film by a photo-etching technique. selectively removing the first oxide film in the element region and forming a second oxide film by a thermal oxidation method, and performing thermal oxidation after nitriding the entire surface by heat treatment in a nitrogen or ammonia atmosphere. forming a first gate insulating film with a step in the element region; removing the nitrided first oxide film in another predetermined element region by photo-etching; and removing the nitrided first oxide film by a thermal oxidation method; forming a third oxide film as a second gate insulating film in the predetermined device region using the first oxide film and the nitrided second oxide film as a mask; and forming gate electrodes on the upper and second gate insulating films, respectively.
A method for manufacturing a type semiconductor device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2280393A JPH04154162A (en) | 1990-10-18 | 1990-10-18 | Manufacture of mos-type semiconductor device |
| KR1019910018258A KR940011478B1 (en) | 1990-10-18 | 1991-10-17 | Method of manufacturing semiconductor device |
| US07/779,078 US5254489A (en) | 1990-10-18 | 1991-10-18 | Method of manufacturing semiconductor device by forming first and second oxide films by use of nitridation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2280393A JPH04154162A (en) | 1990-10-18 | 1990-10-18 | Manufacture of mos-type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04154162A true JPH04154162A (en) | 1992-05-27 |
Family
ID=17624404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2280393A Pending JPH04154162A (en) | 1990-10-18 | 1990-10-18 | Manufacture of mos-type semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH04154162A (en) |
| KR (1) | KR940011478B1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0597124A1 (en) * | 1992-05-29 | 1994-05-18 | Citizen Watch Co. Ltd. | Semiconductor nonvolatile storage device, semiconductor device, and its manufacture method |
| KR100344825B1 (en) * | 1999-11-12 | 2002-07-20 | 주식회사 하이닉스반도체 | Method for fabricating of semiconductor device |
| US6458663B1 (en) * | 2000-08-17 | 2002-10-01 | Micron Technology, Inc. | Masked nitrogen enhanced gate oxide |
| US6475862B1 (en) * | 1999-08-13 | 2002-11-05 | Nec Corporation | Semiconductor device having gate insulating layers different in thickness and material and process for fabrication thereof |
| KR100400764B1 (en) * | 1997-12-29 | 2003-12-24 | 주식회사 하이닉스반도체 | Method for forming dual gate of semiconductor device |
| EP1548823A1 (en) * | 2002-11-25 | 2005-06-29 | Texas Instruments Inc. | Reliable high voltage gate dielectric layers using a dual nitridation process |
-
1990
- 1990-10-18 JP JP2280393A patent/JPH04154162A/en active Pending
-
1991
- 1991-10-17 KR KR1019910018258A patent/KR940011478B1/en not_active IP Right Cessation
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0597124A1 (en) * | 1992-05-29 | 1994-05-18 | Citizen Watch Co. Ltd. | Semiconductor nonvolatile storage device, semiconductor device, and its manufacture method |
| EP0597124A4 (en) * | 1992-05-29 | 1995-02-15 | Citizen Watch Co Ltd | Semiconductor nonvolatile storage device, semiconductor device, and its manufacture method. |
| KR100400764B1 (en) * | 1997-12-29 | 2003-12-24 | 주식회사 하이닉스반도체 | Method for forming dual gate of semiconductor device |
| US6475862B1 (en) * | 1999-08-13 | 2002-11-05 | Nec Corporation | Semiconductor device having gate insulating layers different in thickness and material and process for fabrication thereof |
| KR100344825B1 (en) * | 1999-11-12 | 2002-07-20 | 주식회사 하이닉스반도체 | Method for fabricating of semiconductor device |
| US6458663B1 (en) * | 2000-08-17 | 2002-10-01 | Micron Technology, Inc. | Masked nitrogen enhanced gate oxide |
| US6699743B2 (en) | 2000-08-17 | 2004-03-02 | Micron Technology, Inc. | Masked nitrogen enhanced gate oxide |
| US7186608B2 (en) | 2000-08-17 | 2007-03-06 | Micron Technology, Inc. | Masked nitrogen enhanced gate oxide |
| EP1548823A1 (en) * | 2002-11-25 | 2005-06-29 | Texas Instruments Inc. | Reliable high voltage gate dielectric layers using a dual nitridation process |
| US7183165B2 (en) | 2002-11-25 | 2007-02-27 | Texas Instruments Incorporated | Reliable high voltage gate dielectric layers using a dual nitridation process |
| US7560792B2 (en) | 2002-11-25 | 2009-07-14 | Texas Instruments Incorporated | Reliable high voltage gate dielectric layers using a dual nitridation process |
Also Published As
| Publication number | Publication date |
|---|---|
| KR940011478B1 (en) | 1994-12-19 |
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