JP2655371B2 - Method for forming mask pattern of semiconductor device - Google Patents
Method for forming mask pattern of semiconductor deviceInfo
- Publication number
- JP2655371B2 JP2655371B2 JP3234763A JP23476391A JP2655371B2 JP 2655371 B2 JP2655371 B2 JP 2655371B2 JP 3234763 A JP3234763 A JP 3234763A JP 23476391 A JP23476391 A JP 23476391A JP 2655371 B2 JP2655371 B2 JP 2655371B2
- Authority
- JP
- Japan
- Prior art keywords
- mask
- photosensitive film
- layer
- charge storage
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 29
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000003860 storage Methods 0.000 claims description 68
- 239000000758 substrate Substances 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 239000011159 matrix material Substances 0.000 claims 1
- 230000007261 regionalization Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 208000024891 symptom Diseases 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は高集積半導体装置のマ
スクパターン形成方法に関するもので、特に半導体基板
上の予め定められた部分に形成されるパターンの間隔を
最小化するため、第１感光膜を塗布して露光および現像
工程で第１感光膜マスクを形成して予め定められた間隔
をおいて第２感光膜を塗布して露光および現像工程で第
２感光膜マスクを形成してパターンを形成する、半導体
装置のマスクパターン形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a mask pattern of a highly integrated semiconductor device, and more particularly to a method of forming a first photosensitive film on a semiconductor substrate in order to minimize the interval between patterns formed on a predetermined portion thereof. Is applied to form a first photosensitive film mask in an exposure and development process, and a second photosensitive film is applied at predetermined intervals to form a second photosensitive film mask in an exposure and development process to form a pattern. The present invention relates to a method for forming a mask pattern of a semiconductor device to be formed.
【０００２】[0002]
【従来の技術】従来の技術は所定形状の電極または配線
を形成するため、まず所定の導電層を半導体基板の上部
に形成する。そして、その上部に感光膜を塗布した後、
露光および現像技術によって所望の大きさ、すなわち、
予め定められた幅と長さとを有する感光膜マスクを形成
する。その後、その感光膜マスクによって露出された部
分の導電層をエッチングして予め定められた目的の電極
または配線を形成した。2. Description of the Related Art In the prior art, a predetermined conductive layer is first formed on a semiconductor substrate in order to form an electrode or a wiring having a predetermined shape. And after applying a photosensitive film on the top,
Depending on the exposure and development technology, the desired size, ie,
A photosensitive mask having a predetermined width and length is formed. Thereafter, the portion of the conductive layer exposed by the photosensitive film mask was etched to form a predetermined target electrode or wiring.
【０００３】しかし、上記の方法によると、露光および
現像技術によって形成することができる感光膜マスクパ
ターン間の間隔は制限を受けるようになる。たとえば、
現在まで一般的に用いられる装備および技術によると、
０．６μｍ程度以上の最小限の感光膜マスク線幅の大き
さが要求されなければならない。However, according to the above-mentioned method, the distance between the photosensitive mask patterns that can be formed by the exposure and development techniques is limited. For example,
According to equipment and technology commonly used to date,
A minimum photosensitive mask line width of about 0.6 μm or more must be required.
【０００４】したがって、この発明は上記の制限された
マスク線幅間の間隔を最小かするため第１感光膜を利用
した第１感光膜マスクと、上記第１感光膜マスクに予め
定められた間隔をおき第２間隔を利用する第２感光膜マ
スクとを形成するが、前記第１および第２感光膜マスク
等の間の間隔を最小化することによりマスクの線幅の大
きさを縮めることかできる、半導体装置のマスクパター
ン形成方法を提供することにある。Accordingly, the present invention provides a first photosensitive film mask using a first photosensitive film to minimize the space between the limited mask line widths, and a predetermined distance between the first photosensitive film mask and the first photosensitive film mask. And forming a second photosensitive film mask using the second space. In order to reduce the line width of the mask by minimizing the space between the first and second photosensitive film masks, etc. It is an object of the present invention to provide a method for forming a mask pattern of a semiconductor device.
【０００５】[0005]
【課題を解決するための手段】本発明による半導体装置
のマスクパターン形成方法によると、上部にマスクパタ
ーンが形成される導電層を有する基板を提供する段階
と、前記全体構造上部に第１感光膜層を形成し前記第１
感光膜上部に予め定められた部分のみ露出されるように
構成した第１マスクを配列する段階と、前記第１マスク
によって露出された第１感光膜の一部を紫外線に露出し
前記構造を現像液に入れて紫外線に露出された第１感光
膜を取除いて、第１感光膜マスク層を形成する段階と、
前記露出された全体構造の上部に第２感光膜を沈着し前
記第２感光膜上部に第１感光膜マスク層の一側面から予
め定められた距離を隔てて第２マスクを配列する段階
と、前記第２電荷保存電極用マスクによって露出された
第２感光膜の一部を紫外線に露出し前記構造を現像液に
入れて紫外線に露出された第２感光膜を取除いて前記第
１感光膜マスクの一側面から予め定められた距離の間隔
を有する第２感光膜マスク層を形成してエッチングを望
む導電層を露出させる段階と、前記第１および第２感光
膜マスク層の間に予め定められた間隔をもって露出され
た導電層を除き導電層のマスクパターンを実行する段階
とを含み、それにより前記導電層のマスクパターンの幅
を最小化することができるようにしたことを特徴とす
る。According to the method of forming a mask pattern of a semiconductor device according to the present invention, a substrate having a conductive layer on which a mask pattern is formed is provided, and a first photosensitive film is provided on the entire structure. Forming a layer,
Arranging a first mask configured such that only a predetermined portion is exposed above the photosensitive film, and exposing a part of the first photosensitive film exposed by the first mask to ultraviolet rays to develop the structure; Removing the first photosensitive film exposed to ultraviolet light in a liquid to form a first photosensitive film mask layer;
Depositing a second photosensitive film on the exposed entire structure, and arranging a second mask on the second photosensitive film at a predetermined distance from one side of the first photosensitive mask layer; A portion of the second photosensitive film exposed by the mask for the second charge storage electrode is exposed to ultraviolet light, and the structure is put into a developer to remove the second photosensitive film exposed to ultraviolet light to remove the first photosensitive film. Forming a second photosensitive mask layer having a predetermined distance from one side of the mask to expose a conductive layer desired to be etched; and defining a predetermined distance between the first and second photosensitive mask layers. Performing a mask pattern of the conductive layer except for the conductive layer exposed at a predetermined interval, thereby minimizing the width of the mask pattern of the conductive layer.
【０００６】この発明による半導体装置のマスクパター
ン形成方法の他の実施例は、基板を提供する段階と、前
記基板上部に絶縁層、電荷保存電極用導電層および第１
感光膜層を順次に形成する段階と、前記第１感光膜上部
に予め定められた部分のみ露出されるように構成した第
１電荷保存電極用マスクを配列する段階と、前記第１電
荷保存電極用マスクによって露出された第１感光膜の一
部を紫外線に露出させる段階と、前記構造を現像液に入
れて紫外線に露出された第１感光膜を取除いて第１感光
膜マスク層を形成しその下にある電荷保存電極用導電層
の一部を露出させる段階と、前記第１感光膜マスク層を
硬化させるようにこれを予め定められた温度で予め定め
られた時間の間焼く段階と、前記露出された全体構造の
上部に第２感光膜を沈着する段階と、前記第２感光膜上
部に第１感光膜マスク層の一側面から予め定められた距
離を離隔させて第２電荷保存用マスクを配列する段階
と、前記第２電荷保存電極用マスクによって露出された
第２感光膜の一部を紫外線に露出させる段階と、前記構
造を現像液に入れて紫外線に露出された第２感光膜を取
除いて前記硬化された第２感光膜マスクの一側面から予
め定められた距離の間隔を有する第２感光膜マスク層を
形成してエッチングを望む電荷保存電極用導電層を露出
させる段階と、前記第１および第２感光膜マスク層の間
に予め定められた間隔をもって露出された電荷保存電極
用導電層を除き電荷保存電極を形成する段階とを含み、
それにより前記電荷保存電極の間の間隔を最小化できる
ようにしたことを特徴とする。According to another embodiment of the present invention, there is provided a method of forming a mask pattern of a semiconductor device, comprising the steps of providing a substrate, and forming an insulating layer, a charge storage electrode conductive layer and a first layer on the substrate.
Sequentially forming a photosensitive film layer; arranging a first charge storage electrode mask configured to expose only a predetermined portion on the first photosensitive film; and forming the first charge storage electrode. Exposing a part of the first photosensitive film exposed by the mask to ultraviolet light, and forming the first photosensitive film mask layer by removing the first photosensitive film exposed to ultraviolet light by putting the structure in a developer. Exposing a portion of the conductive layer for the charge storage electrode thereunder; and baking the first photosensitive mask layer at a predetermined temperature for a predetermined time so as to cure the first photosensitive film mask layer. Depositing a second photosensitive layer on the exposed entire structure, and storing a second charge on the second photosensitive layer at a predetermined distance from one side of the first photosensitive mask layer. Arranging a mask for the second electric charge, Exposing a portion of the second photosensitive film exposed by the electrode mask to ultraviolet light; and removing the second photosensitive film exposed to ultraviolet light by putting the structure in a developer to remove the cured second photosensitive film. Forming a second photosensitive film mask layer having a predetermined distance from one side of the film mask to expose a conductive layer for a charge storage electrode to be etched; and forming the first and second photosensitive film mask layers. Forming a charge storage electrode excluding the charge storage electrode conductive layer exposed at a predetermined interval between,
Thus, the distance between the charge storage electrodes can be minimized.
【０００７】この発明によれば、前記第１感光膜マスク
層を焼く段階は１００〜１５０℃の温度で１０〜６０分
程度のハードベーキングすることを特徴とする。According to the present invention, the step of baking the first photosensitive film mask layer is characterized by hard baking at a temperature of 100 to 150 ° C. for about 10 to 60 minutes.
【０００８】この発明によれば、前記第２電荷保存電極
用マスクは前記第１感光膜マスクの一側面からマスク工
程上で要求される最小の誤配列有効距離および後に形成
される電荷保存電極間の最小の絶縁間隔のみを考慮して
配列されることを特徴とする。According to the present invention, the mask for the second charge storage electrode is disposed between one side surface of the first photosensitive film mask and a minimum misalignment effective distance required in a mask process and between the charge storage electrodes formed later. Are arranged in consideration of only the minimum insulation interval of
【０００９】この発明のマスクパターン方法により所定
の電極または配線を形成する場合、前記第１および第２
感光膜マスク間の間隔を最小化し、線幅の大きさを０．
６μｍ以下に減ずることができる。When a predetermined electrode or wiring is formed by the mask pattern method of the present invention, the first and second electrodes are formed.
Minimize the distance between the photosensitive film masks and reduce the line width to 0.
It can be reduced to 6 μm or less.
【００１０】この発明のマスクパターン形成方法は、電
荷保存電極の製造方法、たとえば、配線間の間隔を最小
化するための方法または配線の線幅を最小化するための
方法等にも適用されることができる。The method for forming a mask pattern according to the present invention is also applied to a method for manufacturing a charge storage electrode, for example, a method for minimizing a space between wirings or a method for minimizing a line width of wirings. be able to.
【００１１】[0011]
【実施例の説明】以下、添付の図面を参考にして本願発
明を詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
【００１２】第１図は従来技術により積層キャパシタ構
造を有するＤＲＡＭ（ダイナミック・ランダム・アクセ
ス・メモリ）セルを製造するための主要マスク層を配列
したレイアウト図である。一般的にＭＯＳＦＥＴのソー
スおよびドレイン電極（図示せず）等が形成される領域
の活性マスクＡと、ＭＯＳＦＥＴのゲート電極（図示せ
ず）が長く形成されるゲート電極用マスクＢと、ゲート
電極間および活性領域等の所定上部の電荷保存電極用マ
スクＣとが配列される。ここで、電荷保存電極用マスク
Ｃは電荷保存電極間の縦、横間隔（ｄ１，ｄ２）を露
光、現像工程で形成することができる最小の線幅間隔に
配列したことに注目すべきである。FIG. 1 is a layout diagram in which main mask layers for manufacturing a DRAM (Dynamic Random Access Memory) cell having a laminated capacitor structure according to the prior art are arranged. Generally, an active mask A in a region where source and drain electrodes (not shown) of the MOSFET are formed, a mask B for a gate electrode in which a long gate electrode (not shown) of the MOSFET is formed, And a mask C for a charge storage electrode on a predetermined upper portion such as an active region. Here, it should be noted that the charge storage electrode mask C is arranged such that the vertical and horizontal intervals (d1, d2) between the charge storage electrodes are the minimum line width intervals that can be formed in the exposure and development processes. .
【００１３】第２図の（Ａ）ないし（Ｄ）は第１図のａ
−ａ′端面を切断して電荷保存電極を形成する段階を示
すために図示された断面図である。FIGS. 2A to 2D show a of FIG.
FIG. 6 is a cross-sectional view illustrating a step of forming a charge storage electrode by cutting an end surface of a-a ′.
【００１４】第２図の（Ａ）は、第１図に説明したよう
に、ＭＯＳＦＥＴのソース電極およびドレイン電極が形
成される活性マスク領域（Ａ）上部とＭＯＳＦＥＴのゲ
ート電極が通過するゲート電極用マスク領域（Ｂ）上部
との点線で図示された電荷保存電極用マスク（Ｃ）領域
でソース電極に接続される電荷保存電極を形成するもの
と仮定し、ＭＯＳＦＥＴを包含する基板１０の上部に絶
縁層１、電荷保存電極用導電層２、およびその上部の感
光膜３を順次に塗布した状態を示す断面図である。FIG. 2A shows, as described in FIG. 1, an upper portion of an active mask region (A) where a source electrode and a drain electrode of a MOSFET are formed and a gate electrode through which a gate electrode of the MOSFET passes. It is assumed that the charge storage electrode connected to the source electrode is formed in the charge storage electrode mask (C) region shown by a dotted line above the mask region (B), and an insulating layer is formed on the substrate 10 including the MOSFET. FIG. 2 is a cross-sectional view showing a state in which a layer 1, a conductive layer 2 for charge storage electrodes, and a photosensitive film 3 thereon are sequentially applied.
【００１５】第２図の（Ｂ）は、上記感光膜３の上部に
ガラス４Ａと光遮断用クロム４Ｂとからなるマスク窓４
Ｃが形成された電荷保存電極用マスク４を配列して前記
マスク窓４Ｃを通じて前記感光膜３の一部を紫外線に露
光させる状態を示す断面図である。FIG. 2 (B) shows a mask window 4 made of glass 4A and chromium 4B for shielding light above the photosensitive film 3.
FIG. 4 is a cross-sectional view illustrating a state in which a mask 4 for a charge storage electrode on which C is formed is arranged and a part of the photosensitive film 3 is exposed to ultraviolet rays through the mask window 4C.
【００１６】第２図の（Ｃ）は、上記工程で露光された
感光膜３を現像液中に入れて除去し感光膜マスク層３Ａ
および３Ｂを形成し、その下にある電荷保存電極用導電
層１の一部を露出した状態の断面図である。上記の露光
および現像工程で感光膜マスク層３Ａおよび３Ｂを形成
することができる最小間隔（ｄ１）は一般的に約０．６
μｍ以内である。FIG. 2C shows that the photosensitive film 3 exposed in the above step is removed by placing it in a developing solution.
And FIG. 3B is a cross-sectional view showing a state in which a part of a conductive layer 1 for a charge storage electrode under the conductive layer is exposed. The minimum distance (d1) at which the photosensitive mask layers 3A and 3B can be formed in the above exposure and development steps is generally about 0.6.
It is within μm.
【００１７】第２図の（Ｄ）は、上記感光膜マスク層３
Ａおよび３Ｂの下部の露出された電荷保存電極用導電層
２をエッチングして電荷保存電極２Ａおよび２Ｂを形成
し、前記感光膜マスク層３Ａおよび３Ｂを取除いた状態
の断面図である。FIG. 2D shows the photosensitive film mask layer 3.
FIG. 4 is a cross-sectional view showing a state in which exposed conductive layers 2 for charge storage electrodes below A and 3B are etched to form charge storage electrodes 2A and 2B, and the photosensitive film mask layers 3A and 3B are removed.
【００１８】以上のような従来技術は電荷保存電極と電
荷保存電極との最小間隔（ｄ１）を露光および現像技術
による最小限度の関係で、たとえば、６μｍ以下にはす
ることができなかった。In the prior art described above, the minimum distance (d1) between the charge storage electrodes cannot be reduced to, for example, 6 μm or less due to the minimum relationship between the exposure and development techniques.
【００１９】第３図はこの発明に従って積層キャパシタ
構造を有するＤＲＡＭセルを製造するための主要マスク
層を配列した状態のレイアウト図である。ＭＯＳＦＥＴ
のソースおよびドレイン電極（図示せず）が形成される
領域の活性マスクＡ、ＭＯＳＦＥＴのゲート電極（図示
せず）が長く形成されるゲート電極用マスクＢ、ゲート
電極間および活性領域等の所定上部に第１電荷保存電極
用マスクＣ１と第１電荷保存電極用マスクＣ１周辺に第
２電荷保存電極用マスクＣ２とを配列したものである。
第１図と第３図を比較してみると、前記活性マスクＡお
よびゲート電極用マスクＢの大きさは互いに同一に配列
される反面、第１、第２電荷保存電極用マスクＣ１およ
びＣ２の面積は大きくなり、第１、第２電荷保存電極用
マスクＣ１およびＣ２間の間隔（ｄ３およびｄ４）は第
１図の電荷保存電極用マスクＣ間の間隔（ｄ１およびｄ
２）よりも狭くしたものが図示される。FIG. 3 is a layout diagram in which main mask layers for manufacturing a DRAM cell having a multilayer capacitor structure according to the present invention are arranged. MOSFET
Mask A in a region where source and drain electrodes (not shown) are formed, a mask B for a gate electrode in which a gate electrode (not shown) of a MOSFET is formed long, and a predetermined upper portion between gate electrodes and an active region. A first charge storage electrode mask C1 and a second charge storage electrode mask C2 are arranged around the first charge storage electrode mask C1.
Comparing FIG. 1 with FIG. 3, the sizes of the active mask A and the mask B for the gate electrode are the same, but the sizes of the first and second charge storage electrode masks C1 and C2 are different. The area between the masks C1 and C2 for the first and second charge storage electrodes (d3 and d4) is larger than the area (d1 and d) between the masks C for the charge storage electrodes in FIG.
The drawing narrower than 2) is shown.
【００２０】第４図の（Ａ）ないし（Ｃ）および第５図
の（Ａ）ないし（Ｃ）は第３図のｂ−ｂ′端面を切断し
て電荷保存電極を形成する段階を示すために図示された
断面図である。FIGS. 4 (A) to 4 (C) and FIGS. 5 (A) to 5 (C) show steps of cutting the bb 'end face of FIG. 3 to form a charge storage electrode. FIG.
【００２１】第４図の（Ａ）は、第３図に図示したよう
に、ＭＯＳＦＥＴのソース電極およびドレイン電極が形
成される活性領域Ａ上部とＭＯＳＦＥＴのゲート電極が
通過するゲート電極用マスク領域Ｂ上部の点線で図示さ
れた第１および第２電荷保存電極用マスクＣ１およびＣ
２領域でソース電極に接続される電荷保存電極を形成す
ると仮定し、ＭＯＳＦＥＴを包含する基板２０上部に絶
縁層１１、電荷保存電極用導電層１２（たとえばポリシ
リコン、単結晶シリコンまたはアモルファスシリコン）
および第１感光膜１３を順次に塗布した状態を示す断面
図である。FIG. 4A shows the upper part of the active region A where the source and drain electrodes of the MOSFET are formed and the mask region B for the gate electrode through which the gate electrode of the MOSFET passes, as shown in FIG. Masks C1 and C for the first and second charge storage electrodes illustrated by upper dotted lines
Assuming that a charge storage electrode connected to a source electrode is formed in two regions, an insulating layer 11 and a conductive layer 12 for a charge storage electrode (for example, polysilicon, single crystal silicon, or amorphous silicon) are formed on a substrate 20 including a MOSFET.
FIG. 4 is a cross-sectional view illustrating a state where a first photosensitive film 13 is sequentially applied.
【００２２】第４図（Ｂ）は、前記第１感光膜１３の上
部にガラス１４Ａおよび一側面のみに形成された光遮断
用クロム１４Ｂから構成される第１電荷保存電極用マス
ク１４を予め定められた領域にのみ配列し、露出された
第１感光膜１３の一部を紫外線に露光させる状態にした
断面図である。FIG. 4 (B) shows in advance a first charge storage electrode mask 14 composed of glass 14A and chromium 14B for blocking light formed on one side only on the first photosensitive film 13. FIG. 6 is a cross-sectional view showing a state where only a part of the exposed first photosensitive film 13 is arranged to be exposed to ultraviolet rays only in a region where the first photosensitive film 13 is exposed.
【００２３】ここで注目すべきことは、たとえば、ＭＯ
ＳＦＥＴに接続される１つの４面を有する第１電荷保存
電極マスクが配列されると４面の周辺には４個の第２電
荷保存電極マスクが配列されなければならないことであ
る。It should be noted that, for example, the MO
If a first charge storage electrode mask having four surfaces connected to the SFET is arranged, four second charge storage electrode masks must be arranged around the four surfaces.
【００２４】第４図（Ｃ）は、上記工程で露光された第
１感光膜１３を現像液に入れて取除き、第１感光膜マス
ク層１３Ａを形成し、その下にある電荷保存電極用導電
層１２の一部を露出させ、前記第１感光膜マスク層１３
Ａを１００ないし１５０℃の温度で１０ないし６０分程
度焼いて硬化させた状態を示す断面図である。FIG. 4 (C) shows that the first photosensitive film 13 exposed in the above process is removed by putting it in a developing solution to form a first photosensitive film mask layer 13A, and a charge storage electrode underlying the same. A part of the conductive layer 12 is exposed, and the first photosensitive film mask layer 13 is exposed.
FIG. 3 is a cross-sectional view showing a state in which A is baked at a temperature of 100 to 150 ° C. for about 10 to 60 minutes and cured.
【００２５】第５図の（Ａ）は、上記第１感光膜マスク
層１３Ａおよび露出された導電層１２の上部に第２感光
膜１５を塗布し、ガラス１６Ａおよび一側面にのみ形成
された光遮断用クロム１６Ｂからなる第２電荷保存電極
用マスク１６を第１感光膜マスク層１３Ａの４面周囲か
ら望む距離に離隔させて配列し、上部から紫外線を露光
させる状態を示す断面図である。FIG. 5A shows that the second photosensitive film 15 is applied on the first photosensitive film mask layer 13A and the exposed conductive layer 12 to form a glass 16A and light formed only on one side. FIG. 9 is a cross-sectional view showing a state in which a second charge storage electrode mask 16 made of blocking chromium 16B is arranged at a desired distance from the periphery of four surfaces of a first photosensitive film mask layer 13A and exposed to ultraviolet rays from above.
【００２６】第５図の（Ｂ）は、上記工程で露光された
第２感光膜１５を現像液に入れて取除いて第２感光膜マ
スク層１５Ａを形成した状態を示す断面図である。この
とき、前記第１感光膜マスク層１３Ａはすでに硬化され
たので残っている。FIG. 5B is a cross-sectional view showing a state in which the second photosensitive film 15 exposed in the above process is removed by putting it in a developing solution to form a second photosensitive film mask layer 15A. At this time, the first photosensitive film mask layer 13A has already been cured and remains.
【００２７】第５図の（Ｃ）は前記第１感光膜マスク層
１３Ａおよび第２感光膜マスク層１５Ａ間で露出された
領域の電荷保存電極用導電層１２をエッチングして各々
の電荷保存電極１２Ａおよび１２Ｂを形成し、前記第１
感光膜マスク層１３Ａおよび第２感光膜マスク層１５Ａ
を取り除いた状態を示す断面図である。ここで、電荷保
存電極１２Ａと電荷保存電極１２Ｂとの間の間隔ｄ３は
２つのマスクを順次使用することによる誤配列有効距離
０．１μｍと、電荷保存電極１２Ａおよび１２Ｂ間の縁
縁のための距離０．１μｍのみとを考慮して０．２μｍ
の間隔にすることができる。FIG. 5 (C) shows that each of the charge storage electrodes is etched by etching the charge storage electrode conductive layer 12 in a region exposed between the first photosensitive film mask layer 13A and the second photosensitive film mask layer 15A. 12A and 12B, and the first
Photosensitive film mask layer 13A and second photosensitive film mask layer 15A
It is sectional drawing which shows the state which removed. Here, the distance d3 between the charge storage electrode 12A and the charge storage electrode 12B is set to 0.1 μm for the effective misalignment distance due to the sequential use of two masks and the margin between the charge storage electrodes 12A and 12B. 0.2 μm considering only distance 0.1 μm
Interval.
【００２８】[0028]
【発明の効果】上記のとおりこの発明によれば、同一チ
ップ面積で電荷保存電極の間隔を従来技術に比較して
０．４μｍほど小さくすることができて電荷保存電極の
面積を６０％程度大きくすることができる。また、この
発明の技術を半導体の配線製造技術に適用する場合、配
線の幅と配線と配線との間の間隔を縮小することができ
高集積化に寄与することができる。As described above, according to the present invention, the distance between the charge storage electrodes can be reduced by about 0.4 μm in the same chip area as compared with the prior art, and the area of the charge storage electrodes is increased by about 60%. can do. Further, when the technology of the present invention is applied to a semiconductor wiring manufacturing technology, the width of the wiring and the distance between the wirings can be reduced, which can contribute to high integration.
【図１】従来技術により積層キャパシタを備える多数の
ＤＲＡＭセルを製造するため主要マスク層を配列したレ
イアウト図である。FIG. 1 is a layout diagram in which main mask layers are arranged in order to manufacture a large number of DRAM cells having a multilayer capacitor according to the related art.
【図２】第１図のａ−ａ′線を切り取って電荷保存電極
を形成する段階を示す断面図である。FIG. 2 is a cross-sectional view illustrating a step of forming a charge storage electrode by cutting the line aa ′ of FIG. 1;
【図３】この発明により積層キャパシタを備える多数の
ＤＲＡＭセルを製造するため主要マスク層を配列したレ
イアウト図である。FIG. 3 is a layout diagram in which main mask layers are arranged in order to manufacture a large number of DRAM cells having a multilayer capacitor according to the present invention.
【図４】第３図のｂ−ｂ′線を切り取って電荷保存電極
を形成する段階を示した断面図である。FIG. 4 is a cross-sectional view illustrating a step of forming a charge storage electrode by cutting a line bb ′ of FIG. 3;
【図５】第３図Ｋ ｂ−ｂ′線を切り取って電荷保存電
極を形成する段階を示した断面図である。FIG. 5 is a cross-sectional view illustrating a step of forming a charge storage electrode by cutting a line Kbb ′ in FIG. 3;
Ａ：活性マスク，Ｂ：ゲートマスク，Ｃ：電荷保存電極
マスク，Ｃ１：第１電荷保存電極マスク，Ｃ２：第２電
荷保存電極マスク，１および１１：絶縁層，２および１
２：電荷保存電極導電層，２Ａ，２Ｂ，１２Ａおよび１
２Ｂ：電荷保存電極、３，１３および１５：感光膜、
４：電荷保存電極用マスク ３Ａ，３Ｂ，１３Ａおよび１５Ａ：感光膜マスク層 １４，１６：第１および第２電荷保存電極用マスクA: active mask, B: gate mask, C: charge storage electrode mask, C1: first charge storage electrode mask, C2: second charge storage electrode mask, 1 and 11: insulating layer, 2 and 1
2: Charge storage electrode conductive layer, 2A, 2B, 12A and 1
2B: charge storage electrode, 3, 13 and 15: photosensitive film
4: Mask for charge storage electrode 3A, 3B, 13A and 15A: Photosensitive film mask layer 14, 16: First and second mask for charge storage electrode
Claims (6)
層を有する基板を提供する段階と、 前記全体構造上部に第１感光膜層を形成し前記第１感光
膜上部に予め定められた部分のみ露出されるように構成
した第１のマスクを配列する段階と、 前記第１のマスクによって露出された第１感光膜の一部
を紫外線に露出し前記構造を現像液に入れて紫外線に露
出された第１感光膜を取り除いて、第１感光膜マスク層
を形成する段階と、 前記第１感光膜を１００〜１５０℃の温度で１０〜６０
分程度ハードベーキングする段階と、 前記露出された全体構造の上部に第２感光膜を形成し前
記第２感光膜上部に第１感光膜マスク層の一側面から予
め定められた距離を隔てて第２マスクを配列する段階
と、 前記第２マスクによって露出された第２感光膜の一部を
紫外線に露出し前記構造を現像液に入れて紫外線に露出
された第２感光膜を取り除いて前記第１感光膜マスク層
の一側面から予め定められた距離の間隔を有する第２感
光膜マスクを形成してエッチングされるべき導電層を露
出させる段階と、 前記第１および第２感光膜マスク層の間に予め定められ
た間隔をもって露出された導電層を除き導電層のマスク
パターンを形成する段階とを含み、それにより前記導電
層のマスクパターンの幅を最小化することができるよう
にしたことを特徴とする、半導体装置のマスクパターン
形成方法。Providing a substrate having a conductive layer on which a mask pattern is to be formed, forming a first photosensitive layer on the entire structure, and forming only a predetermined portion on the first photosensitive film. Arranging a first mask configured to be exposed, exposing a portion of the first photosensitive film exposed by the first mask to ultraviolet light, and placing the structure in a developer to be exposed to ultraviolet light. Removing the first photosensitive film and forming a first photosensitive film mask layer; and forming the first photosensitive film at a temperature of 100 to 150 ° C. for 10 to 60 minutes.
Hard baking for about a minute, forming a second photosensitive film on the exposed entire structure, and forming a second photosensitive film on the second photosensitive film at a predetermined distance from one side of the first photosensitive mask layer. Arranging two masks; exposing a portion of the second photosensitive film exposed by the second mask to ultraviolet light; placing the structure in a developing solution to remove the second photosensitive film exposed to ultraviolet light; (1) forming a second photosensitive film mask having a predetermined distance from one side surface of the photosensitive film mask layer to expose a conductive layer to be etched; Forming a mask pattern of the conductive layer except for the conductive layer exposed at a predetermined interval therebetween, whereby the width of the mask pattern of the conductive layer can be minimized. The symptom, the mask pattern formation method of a semiconductor device.
リコン層、アモルファスシリコン層を使用することを特
徴とする、請求項１記載の半導体装置のマスクパターン
形成方法。2. The method according to claim 1, wherein the conductive layer uses a single-crystal polysilicon layer, a silicon layer, or an amorphous silicon layer.
の一側面からマスク工程上で要求される最小の誤配列有
効距離および後に形成される導電層のマスクパターン幅
間の最小の絶縁間隔のみを考慮して配列されることを特
徴とする、請求項１に記載の半導体装置のマスクパター
ン形成方法。3. The second mask has a minimum misalignment effective distance required in a mask process from one side surface of the first photosensitive film mask and a minimum insulation interval between mask pattern widths of a conductive layer formed later. The method according to claim 1, wherein the semiconductor device is arranged in consideration of only the pattern.
用導電層（１２）および第１感光膜層（１３）を順次に
形成する段階と、 前記第１感光膜（１３）上部に予め定められた部分のみ
露出されるように構成した第１電荷保存電極用マスク
（１４）を配列する段階と、 前記第１電荷保存電極用マスク（１４）によって露出さ
れた第１感光膜（１３）の一部を紫外線に露出させる段
階と、 前記構造を現像液に入れて紫外線に露出された第１感光
膜を取り除いて、第１感光膜マスク層（１３Ａ）を形成
しその下にある電荷保存電極用導電層（１２）の一部を
露出させる段階と、 前記第１感光膜マスク層（１３Ａ）を硬化させるように
これを１００℃〜１５０℃の温度で１０〜６０分程度焼
く段階と、 前記露出された全体構造の上部に第２感光膜（１５）を
形成する段階と、 前記第２感光膜（１５）上部に第１感光膜マスク層（１
３Ａ）の一側面から予め定められた距離を離隔させて第
２電荷保存用マスク（１６）を配列する段階と、 前記第２マスクによって露出された第２感光膜の一部を
紫外線に露出させる段階と、 前記構造を現像液に入れて紫外線に露出された第２感光
膜（１５）を取り除いて前記硬化された第１感光膜マス
ク（１３Ａ）一側面からら予め定められた距離の間隔を
有する第２感光膜マスク層（１５Ａ）を形成してエッチ
ングされるべき電荷保存電極用導電層（１２）を露出さ
せる段階と、 前記第１および第２感光膜マスク層の間に予め定められ
た間隔をもって露出された電荷保存電極用導電層（１
２）を除き電荷保存電極（１２Ａ，１２Ｂ）を形成する
段階とを含み、それにより前記電荷保存電極（１２Ａ，
１２Ｂ）の間の間隔を最小化できるようにしたことを特
徴とする、半導体装置のマスクパターン形成方法。4. Providing a substrate (20), and sequentially forming an insulating layer (11), a conductive layer for a charge storage electrode (12) and a first photosensitive film layer (13) on the substrate (20). Arranging a first charge storage electrode mask configured to expose only a predetermined portion on the first photosensitive film; and forming a first charge storage electrode mask on the first photosensitive film. Exposing a portion of the first photosensitive film 13 exposed by the mask 14 to ultraviolet light; removing the first photosensitive film exposed to ultraviolet light by putting the structure in a developer; Forming a film mask layer (13A) and exposing a portion of the underlying conductive layer (12) for charge storage electrodes; and curing the first photosensitive film mask layer (13A) at 100 ° C. Baking at a temperature of ~ 150 ° C for about 10-60 minutes And forming a second photosensitive layer (15) on top of the exposed entire structure, the second photosensitive layer (15) first photosensitive film mask layer on top (1
3A) arranging a second charge storage mask (16) at a predetermined distance from one side surface, and exposing a part of the second photosensitive film exposed by the second mask to ultraviolet rays. And removing the second photosensitive film (15) exposed to ultraviolet rays by putting the structure in a developer and removing a predetermined distance from one side of the cured first photosensitive film mask (13A). Forming a second photosensitive film mask layer (15A) having a conductive layer (12) for a charge storage electrode to be etched, and a predetermined distance between the first and second photosensitive film mask layers. The conductive layer for charge storage electrode (1
Forming the charge storage electrodes (12A, 12B) except for 2), whereby the charge storage electrodes (12A, 12B) are formed.
12B) a method of forming a mask pattern for a semiconductor device, characterized in that the interval between the two can be minimized.
結晶シリコン層、ポリシリコン層、アモルファスシリコ
ン層を使用することを特徴とする、請求項４記載の半導
体装置のマスクパターン形成方法。5. The method according to claim 4, wherein the charge storage electrode conductive layer comprises a single crystal silicon layer, a polysilicon layer, or an amorphous silicon layer.
は前記第１感光膜マスク（１３Ａ）の一側面からマスク
工程上で要求される最小の誤配列有効距離および後に形
成される電荷保存電極（１２Ａおよび１２Ｂ）間の最小
の絶縁間隔のみを考慮して配列されることを特徴とす
る、請求項４に記載の半導体装置のマスクパターン形成
方法。6. The second charge storage electrode mask (16).
Takes into account only the minimum misalignment effective distance required in the masking process from one side of the first photosensitive film mask (13A) and the minimum insulation interval between the charge storage electrodes (12A and 12B) formed later. 5. The method according to claim 4, wherein the mask patterns are arranged in a matrix.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR90-14649 | 1990-09-17 | ||
| KR1019900014649A KR920007184A (en) | 1990-09-17 | 1990-09-17 | Manufacturing Method of Semiconductor Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04332114A JPH04332114A (en) | 1992-11-19 |
| JP2655371B2 true JP2655371B2 (en) | 1997-09-17 |
Family
ID=19303670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3234763A Expired - Fee Related JP2655371B2 (en) | 1990-09-17 | 1991-09-13 | Method for forming mask pattern of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2655371B2 (en) |
| KR (1) | KR920007184A (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5651827A (en) * | 1979-10-05 | 1981-05-09 | Seiko Epson Corp | Preparation of semiconductor device |
| JPS5656632A (en) * | 1979-10-15 | 1981-05-18 | Fujitsu Ltd | Manufacture of semiconductor element |
| JPS58101427A (en) * | 1981-12-11 | 1983-06-16 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS58209124A (en) * | 1982-05-31 | 1983-12-06 | Toshiba Corp | Forming method for resist pattern |
| JPS61101030A (en) * | 1984-10-24 | 1986-05-19 | Fujitsu Ltd | Forming method of ultrafine pattern |
| JPH01128522A (en) * | 1987-11-13 | 1989-05-22 | Fujitsu Ltd | Forming method for resist pattern |
-
1990
- 1990-09-17 KR KR1019900014649A patent/KR920007184A/en not_active Application Discontinuation
-
1991
- 1991-09-13 JP JP3234763A patent/JP2655371B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04332114A (en) | 1992-11-19 |
| KR920007184A (en) | 1992-04-28 |
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