JP2654461B2 - Package for semiconductor integrated circuit - Google Patents
Package for semiconductor integrated circuitInfo
- Publication number
- JP2654461B2 JP2654461B2 JP63170388A JP17038888A JP2654461B2 JP 2654461 B2 JP2654461 B2 JP 2654461B2 JP 63170388 A JP63170388 A JP 63170388A JP 17038888 A JP17038888 A JP 17038888A JP 2654461 B2 JP2654461 B2 JP 2654461B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- package
- integrated circuit
- semiconductor integrated
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体集積回路用パッケージに関する。Description: TECHNICAL FIELD The present invention relates to a package for a semiconductor integrated circuit.
従来の技術とその問題点 従来のセラミックパッケージの組立方法は、通常グリ
ーンシート上に所定の配線を形成する工程、グリーンシ
ートを複数枚組合わせて焼成する工程、焼成されたパッ
ケージの側面、底面などに１本ずつリードを接続する工
程、これらリードおよび配線部分に電気メッキを施す工
程およびパッケージを樹脂により封止する工程からなっ
ている（例えば、実公昭59−8361号公報参照）。Conventional technology and its problems Conventional ceramic package assembling methods usually include a process of forming predetermined wiring on a green sheet, a process of combining and firing a plurality of green sheets, a side surface and a bottom surface of a fired package. A step of connecting leads one by one, a step of electroplating these leads and wiring portions, and a step of sealing the package with a resin (see, for example, Japanese Utility Model Publication No. 59-8361).
しかしながら、この様な方法では、多くの工程が必要
であること、各工程での歩留りが低いこと、多ピン製品
の場合には、工程がさらに複雑となり、安価に製品を提
供することが難しいことなどの問題点がある。However, in such a method, many steps are required, the yield in each step is low, and in the case of a multi-pin product, the steps are further complicated, and it is difficult to provide a product at low cost. There are problems such as.
また、PLCC、フラットパッケージなどの多ピン薄型パ
ッケージの場合には、封止用樹脂に含まれている水分お
よび空気中の水分がICチップにまで次第に浸透していく
ため、耐水性が不充分であるなどの問題点もある。In the case of multi-pin thin packages such as PLCC and flat packages, the moisture contained in the encapsulating resin and the moisture in the air gradually penetrate into the IC chip, resulting in insufficient water resistance. There are also some problems.
さらに、グリーンシートの焼成を1000℃以上の高温度
で行う必要があるため、配線に使用する材料として、貴
金属系、稀土類系などの高価な材料を使用する必要があ
る。Furthermore, since it is necessary to fire the green sheet at a high temperature of 1000 ° C. or higher, it is necessary to use an expensive material such as a noble metal or a rare earth as a material used for wiring.
一方、ユーザー側からみれば、セラミックパッケージ
の特性である高信頼性および高熱伝導性が常に必要であ
るわけではないが、高熱伝導性のみが必要とされる場合
にも、あてて高価格のセラミックパッケージを使用せざ
るを得ないという難点がある。On the other hand, from the user's point of view, high reliability and high thermal conductivity, which are the characteristics of ceramic packages, are not always necessary. There is a drawback that the package must be used.
問題点を解決するための手段 本発明者は、上記の如き従来技術の現状に鑑みて種々
研究を重ねた結果、セラミック基板上に予め樹脂により
リードフレームを固定して半導体集積回路用パッケージ
とした後、常法に従って該半導体集積回路用パッケージ
内のセラミック基板上に半導体集積回路を形成する場合
には、従来技術の問題点が大巾に軽減されることを見出
した。Means for Solving the Problems The present inventor has conducted various studies in view of the current state of the prior art as described above, and as a result, a lead frame was fixed in advance with a resin on a ceramic substrate to form a package for a semiconductor integrated circuit. Later, it has been found that when a semiconductor integrated circuit is formed on a ceramic substrate in the package for a semiconductor integrated circuit according to a conventional method, the problems of the prior art are greatly reduced.
すなわち、本発明は、セラミック基板上にリードフレ
ームを樹脂により固定し、該樹脂の内壁部を耐水性材で
コーティングしたことを特徴とする半導体集積回路用パ
ッケージに係る。That is, the present invention relates to a package for a semiconductor integrated circuit, wherein a lead frame is fixed on a ceramic substrate with a resin, and an inner wall portion of the resin is coated with a water-resistant material.
実 施 例 以下図面に示す実施態様を参照しつつ、本発明をより
詳細に説明する。EXAMPLES The present invention will be described in more detail with reference to embodiments shown in the drawings.
第１図は、本発明による半導体集積回路用パッケージ
の概要を示す断面図である。FIG. 1 is a sectional view showing an outline of a package for a semiconductor integrated circuit according to the present invention.
第１図において、セラミック基板（１）は、必要に応
じ、フィン（３）を備えている。本発明においては、リ
ードフレーム（５）を樹脂層（７）により固定するの
で、中空部（15）が形成される。セラミック基板（１）
の材料としては、公知のものが使用可能であり、窒化ア
ルミニウム、アルミナ、窒化硼素、ベリリア、窒化ケイ
素などが例示される。リードフレーム（５）の材料とし
ても、銅、銅合金、鉄、鉄合金（例えば42アロイ）など
の公知の材料が使用される。また、樹脂層（７）の材料
としては、従来から半導体素子封止用材料として使用さ
れているエポキシ樹脂、フェノール樹脂、ポリイミド樹
脂、シリコーン樹脂、フッ素樹脂、ポリブタジエン、ポ
リエステル樹脂、ポリフェニレンサルファイド樹脂など
を使用することができる。本発明の半導体集積回路用ピ
ッケージは、常法による半導体素子形成工程に送られ、
常法に従って、セラミック基板（１）上のリードフレー
ム（５）により囲まれた孔部にICチップ（９）が固着さ
れ、次いで該ICチップ（９）とリードフレーム（５）と
が、アルミニウム細線（11）により接続された後、セラ
ミック製または樹脂製のキャップ（13）により封止さ
れ、半導体素子とされる。中空部（15）は、既存の樹脂
モールド製品の場合とは異なり、水分の浸透を防止する
バリアーとしての働きをする。なお、中空部（15）を囲
む樹脂内壁部（17）を耐水性材料で予めコーティングし
ておくことにより、半導体素子の耐水性をより一層改善
することができる。このような耐水性材料のコーティン
グは、溶射による酸化物セラミック層の形成、イミド樹
脂、シリコーン樹脂などの塗付による樹脂層の形成、金
属アルコキシド法による金属酸化物層の形成などの手段
により行われる。リードフレーム（５）の端部は、必要
に応じ、（５′）として破線で示す様に、折曲げ加工さ
れる。In FIG. 1, the ceramic substrate (1) is provided with fins (3) as required. In the present invention, since the lead frame (5) is fixed by the resin layer (7), a hollow portion (15) is formed. Ceramic substrate (1)
Known materials can be used as the material, and examples thereof include aluminum nitride, alumina, boron nitride, beryllia, and silicon nitride. As a material of the lead frame (5), a known material such as copper, copper alloy, iron, and iron alloy (for example, 42 alloy) is used. Examples of the material of the resin layer (7) include epoxy resin, phenol resin, polyimide resin, silicone resin, fluorine resin, polybutadiene, polyester resin, and polyphenylene sulfide resin which have been conventionally used as a semiconductor element sealing material. Can be used. The package for a semiconductor integrated circuit of the present invention is sent to a semiconductor element forming step by a conventional method,
According to a conventional method, an IC chip (9) is fixed in a hole surrounded by a lead frame (5) on a ceramic substrate (1). Then, the IC chip (9) and the lead frame (5) are connected to an aluminum thin wire. After being connected by (11), it is sealed by a ceramic or resin cap (13) to form a semiconductor element. The hollow portion (15) functions as a barrier for preventing the penetration of moisture, unlike the case of existing resin molded products. The water resistance of the semiconductor element can be further improved by coating the resin inner wall portion (17) surrounding the hollow portion (15) with a water resistant material in advance. The coating of such a water-resistant material is performed by means such as formation of an oxide ceramic layer by thermal spraying, formation of a resin layer by application of imide resin, silicone resin, or the like, or formation of a metal oxide layer by a metal alkoxide method. . The end of the lead frame (5) is bent as required, as indicated by a broken line as (5 ').
発明の効果 本発明によれば、以下の如き顕著な効果が達成され
る。Effects of the Invention According to the present invention, the following remarkable effects are achieved.
（ａ）半導体素子の製造コストが低減される。(A) The manufacturing cost of the semiconductor element is reduced.
（ｂ）熱伝導に優れ、樹脂モールド品に比して、信頼性
の高い半導体素子が得られる。(B) A semiconductor element having excellent heat conduction and higher reliability than a resin molded product can be obtained.
（ｃ）セラミック基板とキャップとの間にある中空部
が、水分の浸透を防ぐので、樹脂モールド品に比して、
耐水性が著るしく改善される。(C) Since the hollow portion between the ceramic substrate and the cap prevents the penetration of moisture, compared to the resin molded product,
Water resistance is remarkably improved.
（ｄ）ICチップを収容する中空部内壁に耐水性材料層を
形成するので、耐水性にさらに優れた半導体素子が得ら
れる。(D) Since the water-resistant material layer is formed on the inner wall of the hollow portion accommodating the IC chip, a semiconductor device having more excellent water resistance can be obtained.
第１図は、本発明による半導体集積回路用パッケージの
概要を示す断面図である。 （１）……セラミック基板 （３）……フィン （５）……リードフレーム （７）……樹脂層 （９）……ICチップ （13）……セラミック製または樹脂製キャップFIG. 1 is a sectional view showing an outline of a package for a semiconductor integrated circuit according to the present invention. (1) Ceramic substrate (3) Fin (5) Lead frame (7) Resin layer (9) IC chip (13) Ceramic or resin cap
───────────────────────────────────────────────────── フロントページの続き (72)発明者 谷川 栄機 東京都港区浜松町１―18―８ エディッ ク株式会社東京事務所内 (72)発明者 加藤 一成 埼玉県川口市並木２丁目30番１号 第一 精工株式会社内 (56)参考文献 特開 昭58−89847（ＪＰ，Ａ) ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Eiki Tanigawa 1-18-8 Hamamatsucho, Minato-ku, Tokyo Inside EDIC Co., Ltd. Tokyo Office (72) Inventor Kazunari Kato 2-30 Namiki, Kawaguchi City, Saitama Prefecture No. 1 Daiichi Seiko Co., Ltd. (56) References JP-A-58-89847 (JP, A)
Claims (1)
により固定し、該樹脂の内壁部を耐水性材でコーティン
グしたことを特徴とする半導体集積回路用パッケージ。1. A package for a semiconductor integrated circuit, wherein a lead frame is fixed on a ceramic substrate with a resin, and an inner wall portion of the resin is coated with a water-resistant material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63170388A JP2654461B2 (en) | 1988-07-07 | 1988-07-07 | Package for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63170388A JP2654461B2 (en) | 1988-07-07 | 1988-07-07 | Package for semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0220052A JPH0220052A (en) | 1990-01-23 |
| JP2654461B2 true JP2654461B2 (en) | 1997-09-17 |
Family
ID=15904007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63170388A Expired - Lifetime JP2654461B2 (en) | 1988-07-07 | 1988-07-07 | Package for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2654461B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5889847A (en) * | 1981-11-24 | 1983-05-28 | Sharp Corp | Sealing type integrated circuit package |
-
1988
- 1988-07-07 JP JP63170388A patent/JP2654461B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0220052A (en) | 1990-01-23 |
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