JP2586196B2 - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JP2586196B2 JP2586196B2 JP2243186A JP24318690A JP2586196B2 JP 2586196 B2 JP2586196 B2 JP 2586196B2 JP 2243186 A JP2243186 A JP 2243186A JP 24318690 A JP24318690 A JP 24318690A JP 2586196 B2 JP2586196 B2 JP 2586196B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- power supply
- gate
- node
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は出力回路に関し、時に相補型集積回路の出力
回路に関する。Description: BACKGROUND OF THE INVENTION The present invention relates to output circuits, and sometimes to complementary integrated circuit output circuits.
従来の相補型集積回路の出力回路は、第４図に示すよ
うな完全相補型の回路を用いた場合、少なくとも出力用
MOSトランジスタのゲートには、電源，電位及び基準電
位（接地電位）を供給する構成となっていた。この例で
は、Ｐチャネルトランジスタ（以下Ｐ−Trと称す）とＮ
チャネルトランジスタ（以下Ｎ−Trと称す）23とにより
インバータが構成されている。このような回路におい
て、第５図（ａ）に示すように出力用Ｐ−Trのゲートに
オン電圧として接地電位S1を、オフ電位として電源電位
が供給される。又、Ｐ−Tr25とＮ−Tr6とで構成したイ
ンバータで出力用Ｎ−Trのゲートにオン電位として電源
電位S2を、オフ電位として接地電位が供給されデータ出
力を行う。When a completely complementary circuit as shown in FIG. 4 is used, the output circuit of the conventional complementary integrated circuit has at least an output circuit.
The power supply, the potential, and the reference potential (ground potential) are supplied to the gate of the MOS transistor. In this example, a P-channel transistor (hereinafter referred to as P-Tr) and N
The channel transistor (hereinafter referred to as N-Tr) 23 forms an inverter. In such a circuit, as shown in FIG. 5 (a), the gate of the output P-Tr is supplied with the ground potential S1 as the ON voltage and the power supply potential as the OFF potential. Further, a power supply potential S2 is supplied as an ON potential to the gate of the output N-Tr and a ground potential is supplied as an OFF potential to the gate of the output N-Tr by an inverter composed of P-Tr25 and N-Tr6, and data is output.
この時、出力トランジスタのオン電流により、出力端
子DOに付加される負荷容量を充・放電する事により、デ
ータ出力を行う。この回路の特性としては、オン電流を
大きくして動作速度を早くする方が望ましい。At this time, data is output by charging / discharging the load capacitance added to the output terminal DO by the ON current of the output transistor. As the characteristics of this circuit, it is desirable to increase the on-current to increase the operation speed.
反面、オン電流が大きくなると、電源・接地配線の寄
生抵抗・インダクタンスによる雑音が大きくなってく
る。On the other hand, when the on-current increases, noise due to the parasitic resistance and inductance of the power supply / ground wiring increases.
この従来の出力回路では、第５図（ｃ）に示すよう
に、電源電圧が高くなると、さらに出力トランジスタの
電流駆動能力が増し、動作速度は早まるが、前述の電源
・接地電位の雑音も大きくなり、内部動作の誤動作をま
ねいてしまうおそれがある。つまり、動作速度を犠牲に
して雑音をおさえる必要があるという問題点があった。In this conventional output circuit, as shown in FIG. 5 (c), when the power supply voltage is increased, the current driving capability of the output transistor is further increased and the operation speed is increased, but the noise of the power supply / ground potential is also increased. Therefore, there is a possibility that a malfunction of the internal operation may be caused. That is, there is a problem that it is necessary to reduce noise at the expense of operating speed.
本発明の目的は、高電源電圧領域での出力回路の動作
電流による雑音をおさえしかも低電源電圧領域での駆動
能力を大きく設定できる出力回路を提供することにあ
る。SUMMARY OF THE INVENTION It is an object of the present invention to provide an output circuit capable of suppressing noise due to an operation current of an output circuit in a high power supply voltage region and setting a large driving capability in a low power supply voltage region.
本発明の出力回路は、ソース・ドレイン路が第１の電
源と第１の節点間に接続されゲートに入力信号が印加さ
れる第１の一導電型トランジスタと、ソース・ドレイン
路が前記第１の節点と第２の電源間に接続されゲートに
前記入力信号の反転信号が印加される第２の一導電型ト
ランジスタと、ソース・ドレイン路が前記第１の電源と
第２の節点間に接続されゲートに前記入力信号の反転信
号が印加される第１の逆導電型トランジスタと、ソース
・ドレイン路が前記第２の節点と前記第２の電源間に接
続されゲートに前記入力信号が印加される第２の逆導電
型トランジスタと、ソース・ドレイン路が前記第１の電
源と出力端間に接続されゲートが前記第１の節点に接続
された第３の一導電型トランジスタと、ソース・ドレイ
ン路が前記出力端と前記第２の電源管に接続されゲート
が前記第２の節点に接続された第３の逆導電型トランジ
スタとを有することを特徴とする。An output circuit according to the present invention includes: a first one-conductivity-type transistor having a source / drain path connected between a first power supply and a first node and an input signal applied to a gate; And a second one-conductivity-type transistor connected between the first power supply and the second power supply, the source / drain path being connected between the first power supply and the second node. A first reverse-conductivity-type transistor having a gate to which an inverted signal of the input signal is applied; a source / drain path connected between the second node and the second power supply; and the input signal applied to a gate. A third transistor of a first conductivity type having a source / drain path connected between the first power supply and the output terminal and a gate connected to the first node; Path is connected to the output end Serial second gate is connected to the power supply pipe and having a third opposite conductivity type transistor coupled to the second node.
次に本発明について図面を参照して説明する。第１図
は本発明の一実施例の出力回路の回路図である。出力用
トランジスタＰ−Tr1のゲートにＰ−Tr2,3を直列接続し
た回路の出力を接続し、出力用トランジスタＮ−Tr4の
ゲートにＮ−Tr5,6を直列接続した回路の出力を接続す
る。Ｐ−Tr2とＮ−Tr6のゲートには出力データの正転信
号を、Ｐ−Tr3とＮ−Tr5のゲートには出力データの反転
信号をそれぞれ入力する。Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an output circuit according to one embodiment of the present invention. The output of the circuit in which P-Tr2, 3 is connected in series is connected to the gate of the output transistor P-Tr1, and the output of the circuit in which N-Tr5, 6 is connected in series is connected to the gate of the output transistor N-Tr4. The non-inverted signal of the output data is input to the gates of P-Tr2 and N-Tr6, and the inverted signal of the output data is input to the gates of P-Tr3 and N-Tr5.
このような回路構成により、出力用Ｐ−Trのゲート信
号S1はオン電位として、接地電位Ｐ−Tr3のしきい電圧
レベルが供給される事になる。又、出力用Ｎ−Trのゲー
ト信号S2はオン電位として、電源電圧Vcc−Ｎ−Tr5のし
きい電圧レベルが供給される事になる。With such a circuit configuration, the gate signal S1 of the output P-Tr is supplied with the threshold voltage level of the ground potential P-Tr3 as the ON potential. Further, the gate signal S2 of the output N-Tr is supplied with the threshold voltage level of the power supply voltage Vcc-N-Tr5 as the ON potential.
これにより電源電圧が高くなると、Ｐ−Tr3,N−Tr5は
基板電位が深くなるため、しきい電圧の絶対値が大きく
なり、各出力トランジスタのゲート入力信号S1,S2が第
２図（ａ）の様になる。従って、第２図（ｂ）に示すよ
うに、出力Trのみ電源電圧の上昇による駆動能力の上昇
が緩和される。As a result, when the power supply voltage is increased, the substrate potential of P-Tr3 and N-Tr5 is increased, so that the absolute value of the threshold voltage is increased, and the gate input signals S1 and S2 of each output transistor are changed as shown in FIG. It becomes like. Therefore, as shown in FIG. 2 (b), an increase in drive capability due to an increase in the power supply voltage of only the output Tr is reduced.
本実施例によれば、通常、雑音が大きくなる高電圧電
源領域で雑音を抑制する効果がある。According to the present embodiment, there is an effect of suppressing noise in a high-voltage power supply region where noise usually increases.
また、高電源電圧領域は内部回路の動作速度が増して
おり、駆動能力の上昇緩和は集積回路の動作特性を悪化
させない範囲に設定可能であり、回路動作が低速になる
低電源電圧領域でのみ出力回路の駆動能力を上げる事が
可能になる。In addition, the operating speed of the internal circuit is increasing in the high power supply voltage region, and the mitigation of the increase in the driving capability can be set within a range that does not deteriorate the operating characteristics of the integrated circuit. It is possible to increase the driving capability of the output circuit.
第２図に本発明の第２の実施例を示す。本実施例は第
１の実施例の出力用Trのゲート入力部に抵抗R1,R2を追
加したものであり、この場合、高電源電圧領域における
Ｐ−Tr3,N−Tr5の変化初期における駆動能力の上昇を制
限してさらに雑音を抑えるものである。FIG. 2 shows a second embodiment of the present invention. In the present embodiment, resistors R1 and R2 are added to the gate input section of the output Tr of the first embodiment. In this case, the driving capability in the initial stage of the change of P-Tr3 and N-Tr5 in the high power supply voltage region To further suppress noise.
以上説明したように、本発明の回路構成とする事によ
り、高電源電圧領域での出力回路の動作電流による雑音
を抑え、低電源電圧領域での駆動能力を大きく設定でき
る事となり、より高速動作可能な集積回路を実現できる
効果がある。As described above, by employing the circuit configuration of the present invention, noise due to the operation current of the output circuit in the high power supply voltage region can be suppressed, and the driving capability in the low power supply voltage region can be set to a large value. There is an effect that a possible integrated circuit can be realized.
第１図は本発明の一実施例の回路図、第２図（ａ）は信
号電圧の電源電圧依存を示す図、第２図（ｂ）は出力充
放電電流のピーク値変化率dI/dtの電源電圧依存を示す
図、第３図は本発明の第２の実施例の回路図、第４図は
従来の出力回路の回路図、第５図（ａ）は信号電圧を示
す図、第５図（ｂ）は電流値を示す図である。 １……出力用チャネルトランジスタ、2,3,23……Ｐチャ
ネルトランジスタ、４……出力用チャネルトランジス
タ、5,6,25……Ｎチャネルトランジスタ、7,8,9,10……
インバータ回路、S1,S2……出力用Trのゲート入力信
号、DI……出力データ内部信号、DO……出力端子、CO…
…出力負荷容量、IO……出力充放電電流、R1,R2……抵
抗素子。FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 (a) is a diagram showing the power supply voltage dependence of a signal voltage, and FIG. 2 (b) is a peak value change rate dI / dt of an output charging / discharging current. FIG. 3 is a circuit diagram of a second embodiment of the present invention, FIG. 4 is a circuit diagram of a conventional output circuit, FIG. 5 (a) is a diagram showing a signal voltage, and FIG. FIG. 5B is a diagram showing a current value. 1 ... Output channel transistor, 2,3,23 ... P-channel transistor, 4 ... Output channel transistor, 5,6,25 ... N-channel transistor, 7,8,9,10 ...
Inverter circuit, S1, S2: Gate input signal of output Tr, DI: Internal signal of output data, DO: Output terminal, CO:
... output load capacity, IO ... output charge / discharge current, R1, R2 ... resistance elements.
Claims (1)
節点間に接続されゲートに入力信号が印加される第１の
一導電型トランジスタと、ソース・ドレイン路が前記第
１の節点と第２の電源間に接続されゲートに前記入力信
号の反転信号が印加される第２の一導電型トランジスタ
と、ソース・ドレイン路が前記第１の電源と第２の節点
間に接続されゲートに前記入力信号の反転信号が印加さ
れる第１の逆導電型トランジスタと、ソース・ドレイン
路が前記第２の節点と前記第２の電源間に接続されゲー
トに前記入力信号が印加される第２の逆導電型トランジ
スタと、ソース・ドレイン路が前記第１の電源と出力端
間に接続されゲートが前記第１の節点に接続された第３
の一導電型トランジスタと、ソース・ドレイン路が前記
出力端と前記第２の電源管に接続されゲートが前記第２
の節点に接続された第３の逆導電型トランジスタとを有
することを特徴とする出力回路。A first transistor having a source / drain path connected between a first power supply and a first node and an input signal applied to a gate; and a source / drain path connected to the first node. And a second one-conductivity-type transistor connected between the first power supply and a second node, the source-drain path being connected between the first power supply and a second node. A first reverse conductivity type transistor to which an inverted signal of the input signal is applied, and a source / drain path connected between the second node and the second power supply and a gate to which the input signal is applied. And a third transistor having a source / drain path connected between the first power supply and the output terminal and a gate connected to the first node.
And a source / drain path connected to the output terminal and the second power supply tube, and a gate connected to the second
And a third reverse-conductivity-type transistor connected to the node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2243186A JP2586196B2 (en) | 1990-09-13 | 1990-09-13 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2243186A JP2586196B2 (en) | 1990-09-13 | 1990-09-13 | Output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04122121A JPH04122121A (en) | 1992-04-22 |
| JP2586196B2 true JP2586196B2 (en) | 1997-02-26 |
Family
ID=17100106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2243186A Expired - Lifetime JP2586196B2 (en) | 1990-09-13 | 1990-09-13 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2586196B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2655053B2 (en) * | 1993-11-01 | 1997-09-17 | 日本電気株式会社 | Semiconductor integrated circuit device |
-
1990
- 1990-09-13 JP JP2243186A patent/JP2586196B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04122121A (en) | 1992-04-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |