JP2585106B2 - Method for forming electrode of semiconductor device - Google Patents
Method for forming electrode of semiconductor deviceInfo
- Publication number
- JP2585106B2 JP2585106B2 JP1269182A JP26918289A JP2585106B2 JP 2585106 B2 JP2585106 B2 JP 2585106B2 JP 1269182 A JP1269182 A JP 1269182A JP 26918289 A JP26918289 A JP 26918289A JP 2585106 B2 JP2585106 B2 JP 2585106B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor substrate
- semiconductor device
- substrate
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、ショットキー電極が形成された後にオーミ
ック電極が形成される半導体装置の電極形成方法に関す
る。Description: TECHNICAL FIELD The present invention relates to an electrode forming method for a semiconductor device in which an ohmic electrode is formed after a Schottky electrode is formed.
（従来の技術） 第６図は従来のGaAs可変容量ダイオードの断面図であ
って、21はn++GaAsの半導体基板、22はn-GaAsのエピタ
キシャル層、23はn+イオン注入領域、24はSiO2層、25は
Ti/Pt/Auのショットキー電極、26はＰ−SiN層、27はAuG
e/Auのオーミック電極である。(Prior Art) FIG. 6 is a cross-sectional view of a conventional GaAs variable capacitance diode, in which 21 is an n ++ GaAs semiconductor substrate, 22 is an n − GaAs epitaxial layer, 23 is an n + ion implantation region, 24 Is the SiO 2 layer, 25 is
Schottky electrode of Ti / Pt / Au, 26 is a P-SiN layer, 27 is AuG
e / Au ohmic electrode.
第７図は前記GaAs可変容量ダイオードの製造工程を示
すフローチャートであって、エピタキシャル層22の前処
理エッチングをし（Ｓ−１）、その後、イオン注入マス
ク層としてのSiO2層をエピタキシャル層22の上に設け、
フォトリソグラフィにより注入領域窓の形成を行い、Si
+イオンを注入し、（Ｓ−２）、その後、SiO2層を除去
してアニールを行って（Ｓ−３）、n+イオン注入領域23
を形成する。続いてSiO2層24を設けた後、フォトリソグ
ラフィおよびリフトオフ処理をしてショットキー電極用
の窓を形成（Ｓ−４）、その後、電子ビーム蒸着による
ショットキー電極25をn+イオン注入領域23の上に形成す
る（Ｓ−５）。ショットキー電極25を、400℃のグリー
ンガス（H210％,N2ベースガス）の雰囲気中で所定の時
間、熱処理をした後、Ｐ−SiN層26を設けて、フォトリ
ソグラフィによる電極用窓を形成する（Ｓ−６）。最後
に、半導体基板21の裏面を150μｍ程度に研磨し（Ｓ−
７）、真空蒸着によりオーミック電極21を設け（Ｓ−
８）、400℃のN2ガスの雰囲気中で所定の時間、合金化
熱処理をしてウエハプロセスが終了する。FIG. 7 is a flow chart showing the manufacturing process of the GaAs variable capacitance diode. The pre-process etching of the epitaxial layer 22 is performed (S-1), and then the SiO 2 layer as an ion implantation mask layer is formed on the epitaxial layer 22. Provided above,
An injection region window is formed by photolithography,
+ Ions are implanted (S-2), and thereafter, the SiO 2 layer is removed and annealing is performed (S-3) to obtain an n + ion implanted region 23.
To form Then after forming the SiO 2 layer 24, a window for the Schottky electrode by photolithography and a lift-off process (S-4), then, the Schottky electrode 25 by electron beam evaporation n + ion implantation region 23 (S-5). After heat-treating the Schottky electrode 25 in a green gas (H 2 10%, N 2 base gas) atmosphere at 400 ° C. for a predetermined time, a P-SiN layer 26 is provided, and an electrode window is formed by photolithography. Is formed (S-6). Finally, the back surface of the semiconductor substrate 21 is polished to about 150 μm (S-
7), an ohmic electrode 21 is provided by vacuum evaporation (S-
8) The alloying heat treatment is performed for a predetermined time in an atmosphere of N 2 gas at 400 ° C. to complete the wafer process.
上記の製造工程では、半導体基板21を150μｍ程度に
薄くするので、工程中のウエハの割れを防ぐために、オ
ーミック電極27の形成工程をウエハプロセスの最後にし
ている。すなわちショットキー電極25よりオーミック電
極27の形成工程が後になる。In the above manufacturing process, since the semiconductor substrate 21 is thinned to about 150 μm, the step of forming the ohmic electrode 27 is at the end of the wafer process in order to prevent cracking of the wafer during the process. That is, the step of forming the ohmic electrode 27 is performed after the Schottky electrode 25.
第８図はオーミック電極27の合金化熱処理工程に使用
される製造装置を示す構成図であって、31は石英ボー
ド、32は半導体基板、33は石英管である。FIG. 8 is a configuration diagram showing a manufacturing apparatus used for the alloying heat treatment step of the ohmic electrode 27, wherein 31 is a quartz board, 32 is a semiconductor substrate, and 33 is a quartz tube.
同図において、石英ボード31は、半導体基板32の周辺
部を支持して、半導体基板32を複数枚載置できるように
なっており、半導体基板32を載置後、400℃に昇温され
た石英管33へ投入され、所定の時間、保持されて冷却後
に取り出されるようになっている。In the figure, a quartz board 31 supports a peripheral portion of a semiconductor substrate 32 and can mount a plurality of semiconductor substrates 32.After the semiconductor substrate 32 is mounted, the temperature is raised to 400 ° C. It is put into a quartz tube 33, held for a predetermined time, and taken out after cooling.
（発明が解決しようとする課題） 上記の従来技術では、オーミック電極27の熱処理工程
において、しばしば表面側のショットキー電極24の破壊
を引き起こし、ダイオードの逆方向の耐圧を劣化させる
という問題があった。(Problems to be Solved by the Invention) In the above-described conventional technology, in the heat treatment process of the ohmic electrode 27, there is a problem that the Schottky electrode 24 on the surface side is often broken, and the reverse breakdown voltage of the diode is deteriorated. .
すなわちオーミック電極27の熱処理において、温度の
ばらつきが大きい場合や、不均一に熱が加わる場合に、
熱応力によるショットキー電極25の破壊を引き起こし、
歩留りを著しく低下させていた。That is, in the heat treatment of the ohmic electrode 27, when the temperature variation is large or when the heat is applied unevenly,
Causing the destruction of the Schottky electrode 25 due to thermal stress,
The yield was significantly reduced.
特に第８図に示した製造装置における石英ボード31で
は、半導体基板32の周辺部を支持しているため、半導体
基板32への熱伝導が不均一になり、上記の諸問題を生じ
させ易かった。In particular, in the quartz board 31 in the manufacturing apparatus shown in FIG. 8, since the peripheral portion of the semiconductor substrate 32 is supported, the heat conduction to the semiconductor substrate 32 becomes non-uniform, and the above-described problems are easily caused. .
本発明の目的は、オーミック電極の熱処理において先
に形成したショットキー電極の破壊を防止できる半導体
装置の電極形成方法を提供することにある。An object of the present invention is to provide a method for forming an electrode of a semiconductor device, which can prevent the destruction of a Schottky electrode formed earlier in heat treatment of an ohmic electrode.
（課題を解決するための手段） 上記目的を達成するため、本発明は、ショットキー電
極形成工程の後に、オーミック電極形成工程の合金化熱
処理が行われる半導体装置の電極形成方法において、半
導体基板より大面積で熱伝導性がよく、かつ均一な材質
からなる基板保持体に、半導体基板をすきまなく接触さ
せて載置し、さらに前記基板保持体をボードに載置して
前記合金化熱処理を行うことを特徴とする。(Means for Solving the Problems) In order to achieve the above object, the present invention provides an electrode forming method for a semiconductor device in which an alloying heat treatment in an ohmic electrode forming step is performed after a Schottky electrode forming step. A semiconductor substrate is placed on a substrate holder made of a uniform material with good thermal conductivity and a uniform material without any gap, and the substrate holder is placed on a board and the alloying heat treatment is performed. It is characterized by the following.
（作 用） 上記の手段を採用したため、半導体基板を、熱伝導性
がよく、かつ均一な基板保持体に、すきまなく接触させ
て保持することにより、合金化熱処理の工程において半
導体基板の面を均一に加熱することが可能になり、処理
温度のばらつきや不均一な加熱による熱応力の発生をな
くすることができる。(Operation) Since the above-described means is employed, the semiconductor substrate is held in close contact with a uniform substrate holder having good thermal conductivity and a uniform thermal conductivity, so that the surface of the semiconductor substrate is subjected to the alloying heat treatment step. It is possible to perform uniform heating, and it is possible to eliminate variations in processing temperature and generation of thermal stress due to uneven heating.
（実施例） 以下、本発明の実施例を図面に基づいて説明する。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本発明の半導体装置の電極形状方法に使用さ
れる基板保持体の第１実施例を示す斜視図であって、１
は表面にショットキー電極２が、また裏面にオーミック
電極３が形成された半導体基板、４は一対の保持突起５
を突設した基板保持体であって、基板保持体４は、例え
ばアルミニウムのような熱伝導率の高い材料で全体が形
成され、かつ半導体基板１より大面積である。FIG. 1 is a perspective view showing a first embodiment of a substrate holder used in the method for forming electrodes of a semiconductor device according to the present invention.
Is a semiconductor substrate on which a Schottky electrode 2 is formed on the front surface and an ohmic electrode 3 is formed on the back surface.
The substrate holder 4 is formed entirely of a material having high thermal conductivity such as aluminum, for example, and has a larger area than the semiconductor substrate 1.
同図において、半導体基板１はオーミック電極３が形
成された裏面を基板保持体４にすきまなく接触させて載
置し、保持突起５で保持している。In the figure, a semiconductor substrate 1 is placed with its back surface on which an ohmic electrode 3 is formed being brought into close contact with a substrate holder 4 and held by a holding projection 5.
第２図は本発明のオーミック電極の合金化熱処理工程
に使用されている製造装置の第１実施例を示す断面図で
あって、６は半導体基板１を保持した基板保持体４が嵌
着される受溝７を複数形成した石英製のボード、８は石
英管である。FIG. 2 is a cross-sectional view showing a first embodiment of the manufacturing apparatus used in the ohmic electrode alloying heat treatment step of the present invention, and reference numeral 6 denotes a substrate holder 4 holding the semiconductor substrate 1 fitted therein. A quartz board in which a plurality of receiving grooves 7 are formed, and 8 is a quartz tube.
同図において、半導体基板１は、基板保持体４の表面
に半導体基板１の径より狭い間隔に配設された保持突起
５で保持され、また基板保持体４がボード６に斜めに形
成された受溝７に嵌着されることによって傾斜すること
になるので、傾斜した基板保持体４の全面に対して、半
導体基板１が傾いて密着することになる。In the figure, a semiconductor substrate 1 is held on a surface of a substrate holder 4 by holding protrusions 5 arranged at intervals smaller than the diameter of the semiconductor substrate 1, and the substrate holder 4 is formed obliquely on a board 6. Since the semiconductor substrate 1 is inclined by being fitted into the receiving groove 7, the semiconductor substrate 1 is inclined and adheres to the entire surface of the inclined substrate holder 4.
上記のように半導体基板１を載置した後、複数の基板
保持体４をボードの受溝７に嵌着して、400℃に昇温さ
れた石英管８の内部の所定位置に投入してオーミック電
極３に対する合金化熱処理を行う。After the semiconductor substrate 1 is mounted as described above, the plurality of substrate holders 4 are fitted into the receiving grooves 7 of the board, and are put into predetermined positions inside the quartz tube 8 heated to 400 ° C. An alloying heat treatment is performed on the ohmic electrode 3.
このような熱処理工程においては、基板保持体４を介
して半導体基板１が均一に加熱されるため、ショットキ
ー電極２の破壊を引き起こすような熱応力の発生が抑制
され、ダイオードの逆方向耐圧劣化などの不良を発生さ
せずにオーミック電極３の合金化熱処理が行える。In such a heat treatment step, the semiconductor substrate 1 is uniformly heated via the substrate holder 4, so that the generation of thermal stress that may cause the destruction of the Schottky electrode 2 is suppressed, and the reverse breakdown voltage of the diode deteriorates. The alloying heat treatment of the ohmic electrode 3 can be performed without causing such a defect.
第３図は本発明の半導体装置の電極形成方法に使用さ
れる基板保持体の第２実施例を示す断面図であって、11
はSi基板11aからなる基板保持体、12はSi基板11aの上表
面に形成されたAu蒸着層である。FIG. 3 is a sectional view showing a second embodiment of the substrate holder used in the method for forming an electrode of a semiconductor device according to the present invention.
Denotes a substrate holder made of a Si substrate 11a, and 12 denotes an Au vapor-deposited layer formed on the upper surface of the Si substrate 11a.
同図において、半導体基板１のオーミック電極３を基
板保持体11のAu蒸着層12の上に載置している。In FIG. 1, the ohmic electrode 3 of the semiconductor substrate 1 is placed on the Au vapor deposition layer 12 of the substrate holder 11.
第４図は本発明の半導体装置の電極形成方法に使用さ
れる製造装置の第２実施例を示す断面図であって、13は
石英管、14は基板保持体11を複数載置可能な多段構造の
ボードである。FIG. 4 is a cross-sectional view showing a second embodiment of the manufacturing apparatus used in the method for forming an electrode of a semiconductor device according to the present invention. It is a structure board.
同図において、基板保持体11を、熱伝導性の良いSi製
の基板11aの表面に、熱伝導率が高いAuの蒸着層12を形
成して構成することにより、熱の伝導性をさらに向上さ
せている。In the same figure, the heat conductivity is further improved by forming the substrate holder 11 on the surface of a substrate 11a made of Si having good heat conductivity by forming a deposited layer 12 of Au having high heat conductivity. Let me.
なお上記のAu蒸着層12はAuのメッキ層に代えてもよ
い。The above-mentioned Au vapor-deposited layer 12 may be replaced with an Au plating layer.
第５図（ａ），（ｂ）は本発明の第２実施例と従来の
方法とで、第６図の構成の可変容量ダイオードのオーミ
ック電極の合金化熱処理を行った際の２インチ基板の逆
方向耐圧VRの面内分布｛（第５図（ａ））ただし、Ｏは
面内のセンタ位置であり、面内位置とはセンタ位置から
側方へ離れる位置である｝、および逆方向耐圧VRと熱処
理時間との関係（第５図（ｂ））を示した説明図であ
り、400℃ではオーミック電極を得るためには10分程度
の熱処理が必要であるが、第５図（ｂ）に示すように従
来の方法では耐圧劣化が発生していたのに対して、本発
明の第２実施例では耐圧劣化を誘発しないと共に、２イ
ンチ基板の面内でも全面にわたって耐圧劣化が発生して
いない。FIGS. 5 (a) and 5 (b) show the results of the second embodiment of the present invention and the conventional method, in which the alloying heat treatment of the ohmic electrode of the variable capacitance diode having the structure of FIG. In-plane distribution of reverse breakdown voltage V R第 (FIG. 5 (a)), where O is the center position in the plane, and the in-plane position is a position away from the center position to the side, and the reverse direction is an explanatory view showing relationship between the breakdown voltage V R and the heat treatment time (FIG. 5 (b)), and although in order to obtain an ohmic electrode at 400 ° C. are required heat treatment at 10 minutes, 5 ( As shown in FIG. 2B, the conventional method causes the withstand voltage deterioration, whereas the second embodiment of the present invention does not induce the withstand voltage deterioration, and the withstand voltage deterioration occurs over the entire surface of the 2-inch substrate. I haven't.
（発明の効果） 本発明によれば、オーミック電極の合金化熱処理中の
半導体基板への熱伝導が均一になるので、先に形成され
たショットキー電極の熱応力による破壊を引き起こさ
ず、ショットキー特性の良好な半導体装置を再現性よく
得ることが可能で、歩留りの向上が図れる半導体装置の
電極形成方法を提供できる。(Effects of the Invention) According to the present invention, the heat conduction to the semiconductor substrate during the alloying heat treatment of the ohmic electrode becomes uniform, so that the Schottky electrode formed earlier does not break due to thermal stress, A semiconductor device with good characteristics can be obtained with good reproducibility, and a method for forming an electrode of a semiconductor device that can improve the yield can be provided.
第１図は本発明による半導体装置の電極形成方法に使用
される基板保持体の第１実施例を示す斜視図、第２図は
第１図の基板保持体を使用する製造装置の第１実施例を
示す断面図、第３図は基板保持体の第２実施例を示す断
面図、第４図は第３図の基板保持体を使用する製造装置
の第２実施例を示す断面図、第５図（ａ）は逆方向耐圧
の面内分布を示す説明図、第５図（ｂ）は逆方向耐圧と
熱処理時間との関係を示す説明図、第６図は従来のGaAs
可変容量ダイオードの断面図、第７図はGaAs可変容量ダ
イオードの製造工程を示すフローチャート、第８図はオ
ーミック電極の熱処理工程に使用される製造装置を示す
構成図である。 1,21……半導体基板、2,25……ショットキー電極、3,27
……オーミック電極、4,11……基板保持体、6,14……ボ
ード、８……石英管、12……Au蒸着層。FIG. 1 is a perspective view showing a first embodiment of a substrate holder used in the method for forming electrodes of a semiconductor device according to the present invention, and FIG. 2 is a first embodiment of a manufacturing apparatus using the substrate holder of FIG. FIG. 3 is a cross-sectional view showing a second embodiment of the substrate holder, FIG. 4 is a cross-sectional view showing a second embodiment of a manufacturing apparatus using the substrate holder of FIG. 5 (a) is an explanatory diagram showing the in-plane distribution of the reverse breakdown voltage, FIG. 5 (b) is an explanatory diagram showing the relationship between the reverse breakdown voltage and the heat treatment time, and FIG. 6 is a conventional GaAs.
FIG. 7 is a cross-sectional view of a variable capacitance diode, FIG. 7 is a flowchart showing a manufacturing process of a GaAs variable capacitance diode, and FIG. 8 is a configuration diagram showing a manufacturing apparatus used for a heat treatment process of an ohmic electrode. 1,21 …… Semiconductor substrate, 2,25 …… Schottky electrode, 3,27
... ohmic electrode, 4,11 ... substrate holder, 6,14 ... board, 8 ... quartz tube, 12 ... Au vapor deposition layer.
Claims (2)
ック電極形成工程の合金化熱処理が行われる半導体装置
の電極形成方法において、半導体基板より大面積で熱伝
導性がよく、かつ均一な材質からなる基板保持体に、半
導体基板をすきまなく接触させて載置し、さらに前記基
板保持体をボードに載置して前記合金化熱処理を行うこ
とを特徴とする半導体装置の電極形成方法。1. An electrode forming method for a semiconductor device in which an alloying heat treatment in an ohmic electrode forming step is performed after a Schottky electrode forming step, wherein the electrode is formed of a uniform material having a larger area than a semiconductor substrate, having better thermal conductivity. A method for forming an electrode of a semiconductor device, comprising: placing a semiconductor substrate in contact with a substrate holder without any gap; and placing the substrate holder on a board and performing the alloying heat treatment.
Auメッキ、あるいはAu蒸着を施して、保持された半導体
基板への熱伝導を均一にしたことを特徴とする請求項
（１）記載の半導体装置の電極形成方法。2. The semiconductor device according to claim 1, wherein said substrate holding member has a contact surface with a semiconductor substrate.
2. The method for forming an electrode of a semiconductor device according to claim 1, wherein the heat conduction to the held semiconductor substrate is made uniform by applying Au plating or Au vapor deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1269182A JP2585106B2 (en) | 1989-10-18 | 1989-10-18 | Method for forming electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1269182A JP2585106B2 (en) | 1989-10-18 | 1989-10-18 | Method for forming electrode of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03132020A JPH03132020A (en) | 1991-06-05 |
| JP2585106B2 true JP2585106B2 (en) | 1997-02-26 |
Family
ID=17468825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1269182A Expired - Fee Related JP2585106B2 (en) | 1989-10-18 | 1989-10-18 | Method for forming electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2585106B2 (en) |
-
1989
- 1989-10-18 JP JP1269182A patent/JP2585106B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03132020A (en) | 1991-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20020098297A1 (en) | Method of crystallizing amorphous silicon layer and crystallizing apparatus thereof | |
| US3148085A (en) | Method and apparatus for fabricating semiconductor devices | |
| US10727060B2 (en) | Doping system, doping method and method for manufacturing silicon carbide semiconductor device | |
| US3927225A (en) | Schottky barrier contacts and methods of making same | |
| US5238849A (en) | Method of fabricating semiconductor device | |
| JP2585106B2 (en) | Method for forming electrode of semiconductor device | |
| US5126805A (en) | Junction field effect transistor with SiGe contact regions | |
| JPH11135450A (en) | Manufacture of silicon carbide semiconductor device | |
| KR101571138B1 (en) | Deposition method for passivation of silicon wafers | |
| KR910009315B1 (en) | Manufacturing method of semiconductor device | |
| JPS58102521A (en) | Manufacture of semiconductor device | |
| JP4225097B2 (en) | Semiconductor wafer holding jig and semiconductor device manufacturing method | |
| US3066053A (en) | Method for producing semiconductor devices | |
| JP2719690B2 (en) | Doping equipment | |
| JP3939383B2 (en) | Method for manufacturing semiconductor device | |
| JPH05175232A (en) | Thin film transistor and its manufacture | |
| TW497133B (en) | Device and method for preventing over-thick film deposition on the edge of a wafer | |
| JPS63173321A (en) | Manufacture of compound semiconductor device | |
| JPH0447970B2 (en) | ||
| JPH09115922A (en) | Manufacture of semiconductor device | |
| JPH034024Y2 (en) | ||
| JPH08293467A (en) | Manufacture of semiconductor | |
| JPH08255893A (en) | Ohmic electrode | |
| JPH0198268A (en) | Semiconductor radioactive detector | |
| JPH01108781A (en) | Manufacture of semiconductor radiation detector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |