JP2579954B2 - MOS transistor - Google Patents
MOS transistorInfo
- Publication number
- JP2579954B2 JP2579954B2 JP62241411A JP24141187A JP2579954B2 JP 2579954 B2 JP2579954 B2 JP 2579954B2 JP 62241411 A JP62241411 A JP 62241411A JP 24141187 A JP24141187 A JP 24141187A JP 2579954 B2 JP2579954 B2 JP 2579954B2
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- channel
- grooves
- substrate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 21
- 239000010410 layer Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、MOSトランジスタの構造に係わり、特にチ
ャネル領域に溝を設けたMOSトランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to a structure of a MOS transistor, and more particularly to a MOS transistor having a groove in a channel region.
（従来の技術） 近年、各種半導体装置の基本要素として絶縁ゲート型
電界効果トランジスタ、即ちMOSトランジスタが用いら
れている。このMOSトランジスタは、半導体基板の表面
層にソース・ドレイン領域を離間して設けると共に、ソ
ース・ドレイン領域間のチャネル領域上にゲート絶縁膜
を介してゲート電極を形成したもので、簡単な製造プロ
セスで実現でき、高い集積密度が得られる等の利点を持
つ。(Prior Art) In recent years, insulated gate field effect transistors, ie, MOS transistors, have been used as basic elements of various semiconductor devices. This MOS transistor has a source / drain region separated from the surface layer of a semiconductor substrate and a gate electrode formed on a channel region between the source / drain region via a gate insulating film. And has advantages such as high integration density.
しかしながら、この種の装置にあっては次のような問
題があった。即ち、MOSトランジスタは、ゲート直下に
形成される100Å程度の非常に薄い反転層が電流のチャ
ネルとなるため、バルク伝導型のデバイスに比べて電流
駆動力は著しく低い。このため、素子の微細化，高集積
化によりデバイス全体の高速化をはかろうとするとき、
増大する寄生容量の素子の電流駆動力とがアンバランス
になり、デバイス動作の遅延を招くと云う問題を生じ
る。従って、今後、素子の微細化によりデバイス動作の
高速化をはかる上で、大きなチャネルコンダクタンスを
有するデバイスを作ることが重要な課題となってくる。However, this type of apparatus has the following problems. That is, since the MOS transistor has a very thin inversion layer of about 100 ° formed immediately below the gate as a current channel, the current driving power is remarkably lower than that of a bulk conduction type device. For this reason, when trying to speed up the entire device by miniaturization and high integration of elements,
The current driving force of the element having the increased parasitic capacitance becomes unbalanced, which causes a problem that the operation of the device is delayed. Therefore, in the future, in order to increase the speed of device operation by miniaturization of elements, it is important to produce a device having a large channel conductance.
（発明が解決しようとする問題点） このように、従来のMOSトランジスタは電流駆動力の
小さいものであり、またこれを微細化する際には電流駆
動力の低下が問題となり、動作速度の高速化をはかるこ
とは困難であった。(Problems to be Solved by the Invention) As described above, the conventional MOS transistor has a small current drivability, and a reduction in the current drivability becomes a problem when miniaturizing the MOS transistor. It was difficult to achieve this.
本発明は上記事情を考慮してなされたもので、その目
的とするところは、電流駆動力を増大させることがで
き、スイッチング特性の高速化等をはかり得るMOSトラ
ンジスタを提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a MOS transistor which can increase a current driving force and can achieve high-speed switching characteristics.
［発明の構成］ （問題点を解決するための手段） 本発明の骨子は、基板表面のみならず基板内部をもチ
ャネルとして用いることにより、実効的なチャネル幅を
拡大して電流駆動力の増大をはかることにある。[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to use not only the substrate surface but also the inside of the substrate as a channel, thereby increasing the effective channel width and increasing the current driving force. To measure.
即ち本発明は、半導体基板上に離間して形成されたソ
ース・ドレイン領域と、ソース・ドレイン領域間のチャ
ネル領域上にゲート絶縁膜を介して形成されたゲート電
極とを具備したMOSトランジスタにおいて、前記基板の
チャネル領域にチャネル長方向に沿って複数の溝を設け
るようにしたものである。That is, the present invention relates to a MOS transistor having a source / drain region formed separately on a semiconductor substrate and a gate electrode formed on a channel region between the source / drain region via a gate insulating film. A plurality of grooves are provided along a channel length direction in a channel region of the substrate.
（作用） 本発明によれば、チャネル長方向に沿って複数の溝を
形成することにより、基板表面に形成される空乏層のチ
ャネル幅方向の長さ、つまり実効的なチャネル幅を広げ
ることができる。このため、微細な素子であっても、電
流駆動力の増大をはかることが可能である。また、複数
の溝の間に形成される凸部をある程度狭く形成すれば、
凸部全体を空乏化することができ、これにより電流駆動
力の大幅な増大をはかることが可能である。(Operation) According to the present invention, the length of the depletion layer formed on the substrate surface in the channel width direction, that is, the effective channel width can be increased by forming a plurality of grooves along the channel length direction. it can. For this reason, it is possible to increase the current driving force even with a fine element. Also, if the protrusion formed between the plurality of grooves is formed to be narrow to some extent,
The entire convex portion can be depleted, thereby making it possible to significantly increase the current driving force.
（実施例） 以下、本発明の詳細を図示の実施例によって説明す
る。第１図（ａ）（ｂ）は本発明の一実施例に係わるMO
Sトランジスタの概略構成を説明するためのもので、
（ａ）平面図、（ｂ）は（ａ）の矢視Ａ−Ａ断面図であ
る。図中11はＰ型Si基板であり、この基板11上のフィー
ルド酸化膜12で囲まれた素子形成領域13には、ソース・
ドレイン領域17,18が形成されると共に、ソース・ドレ
イン領域17,18間のチャネル領域にはゲート酸化膜15を
介してゲート電極16が形成されている。また、チャネル
領域にはチャネル長方向に沿って複数本の溝14が形成さ
れており、これらの溝14の両端はチャネル領域外に延在
している。(Examples) Hereinafter, details of the present invention will be described with reference to the illustrated examples. FIGS. 1A and 1B show an MO according to an embodiment of the present invention.
This is for explaining the schematic configuration of the S transistor.
(A) is a plan view, and (b) is an AA cross-sectional view of (a). In the figure, reference numeral 11 denotes a P-type Si substrate, and an element forming region 13 surrounded by a field oxide film 12 on the substrate 11 has a source
Drain regions 17 and 18 are formed, and a gate electrode 16 is formed via a gate oxide film 15 in a channel region between the source and drain regions 17 and 18. Further, a plurality of grooves 14 are formed in the channel region along the channel length direction, and both ends of these grooves 14 extend outside the channel region.
ここで、溝14の間には凸部が形成されるが、この凸部
のうちの１つを拡大したのが第２図（ａ）である。凸部
の寸法はチャネル領域に反転層が形成されるようにゲー
ト電圧を印加した場合に、凸部の側壁表面から基板内部
方向に伸びる空乏層が該側壁表面に反転層が形成される
よりも以前に対向する側壁表面から伸びる空乏層と接す
る寸法以下に微細化されている。Here, convex portions are formed between the grooves 14, and one of the convex portions is enlarged in FIG. 2 (a). When the gate voltage is applied so that the inversion layer is formed in the channel region, the depletion layer extending from the sidewall surface of the projection toward the inside of the substrate has a larger dimension than the inversion layer is formed on the sidewall surface. Previously, it was miniaturized to a size smaller than the dimension in contact with the depletion layer extending from the opposing side wall surface.
このような構成において、ゲート電圧を印加してチャ
ネル領域に反転層を形成した場合、第２図のAA′方向及
びBB′方向のバンドダイヤグラムは同図（ｂ）（ｃ）に
示す如くなる。即ち、反転領域は第２図（ａ）に斜線で
示すように基板表面部分及び凸部内部となる。従って素
子の駆動力は、基板表面に凸部を設けることで実効的に
チャネル幅が広くなる効果のみならず、凸部内部が反転
領域となる効果によって、従来の表面チャネル伝導型の
デバイスに比べて格段に大きいものとなる。In such a configuration, when an inversion layer is formed in the channel region by applying a gate voltage, the band diagrams in the AA 'direction and BB' direction in FIG. 2 are as shown in FIGS. That is, the inversion area is the substrate surface portion and the inside of the convex portion as shown by oblique lines in FIG. Therefore, the driving force of the element is not only the effect of effectively increasing the channel width by providing the convex portion on the substrate surface, but also the effect that the inside of the convex portion becomes an inversion region, and the driving force of the device is lower than that of the conventional surface channel conduction type device. Will be much larger.
かくして本実施例によれば、基板11のチャネル領域に
複数本の溝14を設けることにより、実効的なチャネル幅
を拡大することができ、電流駆動力の増大をはかること
ができる。さらに、複数の溝14間に形成される凸部の幅
をある程度短くすることにより、凸部内部をも反転領域
とすることができ、これにより電流駆動力のより一層の
増大をはかることができる。従って、素子を微細化した
場合にあっても、十分大きな電流駆動力を得ることがで
き、デバイス動作の高速化をはかる上でも極めて有効で
ある。なお、前記凸部の側壁表面から伸びる空乏層を対
向する側壁表面から伸びる空乏層と接触させるには、本
発明者等の実験によれば通常は凸部の幅を3000Å程度以
下にすればよいことが確認されたが、この寸法は基板不
純物濃度，ゲート酸化膜膜厚等の条件によっても変わ
る。Thus, according to the present embodiment, by providing a plurality of grooves 14 in the channel region of the substrate 11, the effective channel width can be increased, and the current driving force can be increased. Further, by reducing the width of the convex portion formed between the plurality of grooves 14 to some extent, the inside of the convex portion can also be an inversion region, whereby the current driving force can be further increased. . Therefore, even when the element is miniaturized, a sufficiently large current driving force can be obtained, which is extremely effective in increasing the speed of device operation. In order to make the depletion layer extending from the side wall surface of the convex portion contact with the depletion layer extending from the opposing side wall surface, according to experiments performed by the present inventors, the width of the convex portion may be generally set to about 3000 ° or less. It has been confirmed that this dimension varies depending on conditions such as the impurity concentration of the substrate and the thickness of the gate oxide film.
また、ゲート電圧を印加するに従って、基板凸部全体
のポテンシャルは下がっていくので、所謂Ｓ係数（サブ
スレッショルド係数）は小さくなる。さらに、チャネル
領域が形成された場合、基板凸部のチャネル領域内の垂
直電界は従来の表面チャネル伝導型のデバイスに比べて
小さくなるので、モビリティは高くなる。In addition, as the gate voltage is applied, the potential of the entire substrate convex portion decreases, so that the so-called S coefficient (sub-threshold coefficient) decreases. Further, when the channel region is formed, the vertical electric field in the channel region of the substrate convex portion is smaller than that of the conventional surface channel conduction type device, so that the mobility is increased.
第３図（ａ）〜（ｃ）は上記実施例トランジスタの製
造工程を示す断面図である。まず、Ｐ型Si基板（基板不
純物濃度〜１×1016cm-3）11の表面に、周知の選択酸化
でフィールド酸化膜12を形成した。その後、フィールド
酸化膜12で囲まれた素子形成領域13のチャネル形成予定
位置に、電子ビームリソグラフィにより深さ3000Åの溝
14を例えば10本形成した。このとき、隣合う溝14の間隔
ｄは3000Åとした。また、溝14のチャネル長方向の長さ
ｌはゲート長Ｌよりも長くなるようにした。3 (a) to 3 (c) are cross-sectional views showing the steps of manufacturing the transistor of the above embodiment. First, a field oxide film 12 was formed on the surface of a P-type Si substrate (substrate impurity concentration: 1 × 10 16 cm −3 ) 11 by well-known selective oxidation. Thereafter, a groove having a depth of 3000 mm is formed by electron beam lithography at a position where a channel is to be formed in the element forming region 13 surrounded by the field oxide film 12.
For example, ten 14 were formed. At this time, the interval d between adjacent grooves 14 was 3000 °. The length l of the groove 14 in the channel length direction is set to be longer than the gate length L.
次いで、酸素雰囲気中での熱酸化法により、第３図
（ｂ）に示す如く、ゲート酸化膜15を200Åの厚さに形
成した。次いで、通常のｎチャネルMOSトランジスタ形
成工程に従い、第３図（ｃ）に示す如く、全面にn+ポリ
シリコン膜16′を堆積し、これをパターニングすること
により、ゲート電極16を形成した。さらに、このゲート
電極16をマスクとして自己整合的にソース・ドレイン領
域17,18に不純物をイオン注入し（例えばＰイオンを１
×1020cm-3）、950℃で熱処理して拡散することによりM
OSトランジスタを作成した。Next, as shown in FIG. 3B, a gate oxide film 15 was formed to a thickness of 200 ° by a thermal oxidation method in an oxygen atmosphere. Then, according to a normal n-channel MOS transistor formation process, as shown in FIG. 3C, an n + polysilicon film 16 ′ was deposited on the entire surface and patterned to form a gate electrode 16. Using the gate electrode 16 as a mask, impurities are ion-implanted into the source / drain regions 17 and 18 in a self-aligned manner (for example, P
× 10 20 cm −3 ), heat treated at 950 ° C.
OS transistor was created.
かくして得られたMOSトランジスタの電流駆動力は、
同じチャネル幅を有する従来素子に比べて4.3倍（実効
的なチャネル幅で規格化しても2.1倍）向上していた。
また、溝14を形成する工程を付加するのみで、従来工程
を大幅に変えることなく、簡易に製作することができ
た。The current driving power of the MOS transistor thus obtained is
This was 4.3 times (2.1 times even if standardized with an effective channel width) compared to the conventional device having the same channel width.
Further, only by adding the step of forming the groove 14, it was possible to easily manufacture without greatly changing the conventional step.
なお、本発明は上述した実施例に限定されるものでは
ない。例えば、前記溝の数，長さｌ及び幅等の条件は、
仕様に応じて適宜変更可能であり、特に溝の長さはチャ
ネル長と同等若しくはそれ以上であればよい。さらに、
溝間に形成される凸部の幅ｄは、前述したように側壁表
面からの空乏層が互いに接するように3000Å以下にする
のが望ましいが、電流駆動力の大幅な増大を必要としな
い場合はそれ以上としてもよい。また、実施例ではバル
ク基板を例にとり説明したが、本発明はSOIやSOS構造に
も適用することが可能である。さらに、Ｎチャネルに限
らず、ＰチャネルMOSトランジスタに適用できるのも勿
論のことである。その他、本発明の要旨を逸脱しない範
囲で、種々変形して実施することができる。The present invention is not limited to the embodiments described above. For example, conditions such as the number, length 1 and width of the grooves are as follows:
It can be changed as appropriate according to the specifications. In particular, the length of the groove may be equal to or longer than the channel length. further,
The width d of the convex portion formed between the grooves is desirably set to 3000 ° or less so that the depletion layers from the side wall surface are in contact with each other as described above. However, when a large increase in current driving force is not required, It may be more. In the embodiments, the bulk substrate is described as an example, but the present invention can also be applied to SOI or SOS structures. Furthermore, it is needless to say that the present invention can be applied not only to the N-channel but also to the P-channel MOS transistor. In addition, various modifications can be made without departing from the scope of the present invention.
［発明の効果］ 以上詳述したように本発明によれば、チャネル領域に
複数の溝を形成し実効的なチャネル幅を拡大しているの
で、素子の微細化にも拘らず、電流駆動力が高くスイッ
チング特性の良好な高速トランジスタを容易に実現する
ことができる。[Effects of the Invention] As described in detail above, according to the present invention, a plurality of grooves are formed in the channel region to increase the effective channel width. A high-speed transistor with high switching characteristics and good switching characteristics can be easily realized.
第１図は本発明の一実施例に係わるMOSトランジスタの
概略構成を示す平面図及び断面図、第２図は上記トラン
ジスタの作用を説明するための模式図、第３図は上記ト
ランジスタの製造工程を示す断面図である。 11……Si基板、12……フィールド酸化膜、13……素子形
成領域、14……溝、15……ゲート酸化膜、16……ゲート
電極、17,18……ソース・ドレイン領域。FIG. 1 is a plan view and a sectional view showing a schematic configuration of a MOS transistor according to an embodiment of the present invention, FIG. 2 is a schematic diagram for explaining the operation of the transistor, and FIG. FIG. 11 ... Si substrate, 12 ... Field oxide film, 13 ... Device formation region, 14 ... Groove, 15 ... Gate oxide film, 16 ... Gate electrode, 17,18 ... Source / drain region.
Claims (3)
ソース・ドレイン領域と、ソース・ドレイン領域間のチ
ャネル領域上にゲート絶縁膜を介して形成されたゲート
電極とを具備したMOSトランジスタにおいて、 前記基板のチャネル領域にチャネル長方向に沿って複数
の溝を設けてなり、該溝の間に形成される凸部は、該凸
部の側壁表面から伸びる空乏層が対向する側壁表面から
伸びる空乏層と接するように、その幅を規定されたもの
であることを特徴とするMOSトランジスタ。1. A MOS transistor comprising: a source / drain region formed separately from a surface layer of a semiconductor substrate; and a gate electrode formed on a channel region between the source / drain region via a gate insulating film. In the above, a plurality of grooves are provided along a channel length direction in a channel region of the substrate, and a protrusion formed between the grooves is formed from a side wall surface facing a depletion layer extending from a side wall surface of the protrusion. A MOS transistor whose width is defined so as to be in contact with an extending depletion layer.
れ以上に長いことを特徴とする特許請求の範囲第１項記
載のMOSトランジスタ。2. The MOS transistor according to claim 1, wherein said plurality of grooves are longer than or equal to a channel length.
の幅が3000Å以下であることを特徴とする特許請求の範
囲第１項記載のMOSトランジスタ。3. The MOS transistor according to claim 1, wherein said projection formed between said plurality of grooves has a width of 3000 ° or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62241411A JP2579954B2 (en) | 1987-09-25 | 1987-09-25 | MOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62241411A JP2579954B2 (en) | 1987-09-25 | 1987-09-25 | MOS transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6482672A JPS6482672A (en) | 1989-03-28 |
| JP2579954B2 true JP2579954B2 (en) | 1997-02-12 |
Family
ID=17073889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62241411A Expired - Lifetime JP2579954B2 (en) | 1987-09-25 | 1987-09-25 | MOS transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2579954B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7199425B2 (en) | 2003-05-26 | 2007-04-03 | Kabushiki Kaisha Toshiba | Non-volatile memory cells |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2994670B2 (en) | 1989-12-02 | 1999-12-27 | 忠弘 大見 | Semiconductor device and manufacturing method thereof |
| US5675164A (en) * | 1995-06-07 | 1997-10-07 | International Business Machines Corporation | High performance multi-mesa field effect transistor |
| CN104752502A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Metal-oxide -semiconductor (MOS) transistor and forming method thereof |
| CN104952785A (en) * | 2014-03-31 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| JP2018073971A (en) | 2016-10-28 | 2018-05-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
| WO2022165817A1 (en) * | 2021-02-07 | 2022-08-11 | 深圳市汇顶科技股份有限公司 | Field-effect transistor and manufacturing method therefor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5671974A (en) * | 1979-11-16 | 1981-06-15 | Fujitsu Ltd | Insulating gate type electric field effect transistor |
| JPS5710973A (en) * | 1980-06-24 | 1982-01-20 | Agency Of Ind Science & Technol | Semiconductor device |
-
1987
- 1987-09-25 JP JP62241411A patent/JP2579954B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7199425B2 (en) | 2003-05-26 | 2007-04-03 | Kabushiki Kaisha Toshiba | Non-volatile memory cells |
| US7391076B2 (en) | 2003-05-26 | 2008-06-24 | Kabushiki Kaisha Toshiba | Non-volatile memory cells |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6482672A (en) | 1989-03-28 |
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