JP2552103B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2552103B2 JP2552103B2 JP58251198A JP25119883A JP2552103B2 JP 2552103 B2 JP2552103 B2 JP 2552103B2 JP 58251198 A JP58251198 A JP 58251198A JP 25119883 A JP25119883 A JP 25119883A JP 2552103 B2 JP2552103 B2 JP 2552103B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- signal
- input
- stage
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔技術分野〕 本発明はマイクロコンピュータ等の半導体集積回路の
テストモード設定の改良に関する。TECHNICAL FIELD The present invention relates to improvement of test mode setting of a semiconductor integrated circuit such as a microcomputer.
マイクロコンピュータ等のように内部にROM,RAM,デコ
ーダ回路等を含む半導体集積回路は通常動作を行う通常
動作モードの他に内部回路のテストを行うためのテスト
モードが必要である。テストモードを設定するために
は、電源端子を含む本来の入出力端子以外にテストモー
ドを決定するためのテスト用端子が従来必要であった。
このテスト端子はウエハーのテスト段階のみ使用され、
組立実装後は外部に出さないこともあるがこのような場
合には、最終段階における完全なテストは困難になると
いう問題点が残る。またテスト端子を外部に出す実装を
する場合には、テストは最終段階まで完全に行うことが
できるものの、本来、その集積回路の機能を果す上で必
要ないテスト端子が実装後の貴重なピンを専有し、特に
14ピン,16ピンなどの少数の実装パッケージでは、限ら
れたピン数をテスト端子のために全ピン有効に利用する
ことができない欠点があった。A semiconductor integrated circuit including a ROM, a RAM, a decoder circuit and the like such as a microcomputer requires a test mode for testing the internal circuit in addition to a normal operation mode for performing a normal operation. In order to set the test mode, in addition to the original input / output terminals including the power supply terminal, a test terminal for determining the test mode has been conventionally required.
This test terminal is used only at the wafer test stage,
After assembly and mounting, it may not be released to the outside, but in such a case, the problem remains that complete testing in the final stage becomes difficult. In addition, when mounting the test terminals to the outside, the test can be completed completely up to the final stage, but the test terminals that are originally not necessary to fulfill the functions of the integrated circuit are valuable pins after mounting. Monopoly, especially
With a small number of mounting packages such as 14-pin and 16-pin, there was a drawback that the limited number of pins could not be effectively used for all pins for test terminals.
本発明はこのような問題点を解決するもので、その目的
は、専用のテスト端子に設けずにテストモードを決定で
きる半導体集積回路を提供することにある。The present invention solves such a problem, and an object thereof is to provide a semiconductor integrated circuit capable of determining a test mode without providing a dedicated test terminal.
本発明による半導体集積回路は、外部より与えられる
信号に応じて通常動作モードとテストモードとを選択す
る半導体集積回路において、前記半導体集積回路を初期
化するリセット信号が入力されるリセット端子と、前記
半導体集積回路の動作用クロック信号が入力されるクロ
ック入力端子と、前記リセット端子から入力された信号
を各段のクロック入力部に接続し、前記クロック入力端
子から入力された信号を初段のデータ入力部に接続し、
各段の出力を順次次段のデータ入力部に接続した複数段
のシフトレジスタと、前記複数段のシフトレジスタの各
段の出力をそれぞれ入力し、前記シフトレジスタ各段の
出力があらかじめ決められた出力値となった時に前記テ
ストモードを選択する信号を発生する論理回路を有する
ことを特徴とする。A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit that selects a normal operation mode or a test mode according to a signal supplied from the outside, and a reset terminal to which a reset signal for initializing the semiconductor integrated circuit is input, A clock input terminal to which a clock signal for operating the semiconductor integrated circuit is input, and a signal input from the reset terminal is connected to a clock input section of each stage, and a signal input from the clock input terminal is input to the first stage of data. Connect to the
The output of each stage of the shift register is predetermined by inputting the output of each stage of the shift register of the plurality of stages and the shift register of the plurality of stages in which the output of each stage is sequentially connected to the data input section of the next stage. It is characterized by having a logic circuit for generating a signal for selecting the test mode when the output value is obtained.
以下、本発明について実施例に基づき詳細に説明す
る。Hereinafter, the present invention will be described in detail based on examples.
第1図は本発明の一実施例である。同図において1は
半導体集積回路、2はクロック入力端子でここに加えら
れた信号は2段のインバータで構成されたゲート回路6
を経由して集積回路内部にクロック信号9として供給さ
れるとともに、本発明の構成要素の一部であるシフトレ
ジスタ4の初段のデータ入力部に接続される。一方、3
のリセット入力端子の信号はゲート回路7を経由して集
積回路内部を初期化するリセット信号10として供給され
るとともに、前記シフトレジスタ4の各段のクロック入
力部に接続される。この例ではシフトレジスタは4段で
あり各段の出力及びリセット信号10は本発明の構成要素
であるテストモードを決定する論理回路5の入力に接続
される。この例では論理回路は5入力のNAND回路とイン
バータで構成されている。論理回路5の出力8はシフト
レジスタ4の状態によって一義的に定まり、ここではシ
フトレジスタのコードが(0,1,1,0)でリセット信号9
が1のとき、論理回路5の出力8は1となりテストモー
ドとなる。第2図のタイミング図はテストモードを選択
せずに通常動作モードで半導体集積回路を初期化する場
合のリセット入力信号3とクロック入力信号2のタイミ
ングを示したものであり、クロック入力信号2は常にあ
る周期で1,0を繰返しており、リセット入力信号3はあ
る期間1のレベルを保った後0のレベルに戻り集積回路
は動作を開始する。FIG. 1 shows an embodiment of the present invention. In the figure, reference numeral 1 is a semiconductor integrated circuit, 2 is a clock input terminal, and a signal applied thereto is a gate circuit 6 composed of two stages of inverters.
Is supplied to the inside of the integrated circuit as a clock signal 9 and is connected to the first stage data input section of the shift register 4, which is a part of the constituent elements of the present invention. On the other hand, 3
The signal at the reset input terminal is supplied as a reset signal 10 for initializing the inside of the integrated circuit via the gate circuit 7, and is also connected to the clock input section of each stage of the shift register 4. In this example, the shift register has four stages, and the output of each stage and the reset signal 10 are connected to the input of the logic circuit 5 which determines the test mode, which is a component of the present invention. In this example, the logic circuit is composed of a 5-input NAND circuit and an inverter. The output 8 of the logic circuit 5 is uniquely determined by the state of the shift register 4, and here the code of the shift register is (0,1,1,0) and the reset signal 9
Is 1, the output 8 of the logic circuit 5 becomes 1 to enter the test mode. The timing diagram of FIG. 2 shows the timing of the reset input signal 3 and the clock input signal 2 when the semiconductor integrated circuit is initialized in the normal operation mode without selecting the test mode. 1 and 0 are always repeated in a certain cycle, the reset input signal 3 maintains the level of 1 for a certain period of time and then returns to the level of 0, and the integrated circuit starts the operation.
このときシフトレジスタの状態は不定であるが、リセッ
ト入力信号3が0のレベルの通常動作の間はテストモー
ド信号8は1のレベルになり得ず決っしてテストモード
には入らない。At this time, the state of the shift register is indefinite, but during the normal operation in which the reset input signal 3 is at the level of 0, the test mode signal 8 cannot be at the level of 1, and the test mode signal 8 is not entered into the test mode.
第3図のタイミング図は本発明の構成によりテストモ
ードに入るための各波形を示す。クロック入力信号2は
シフトレジスタ4の入力データとなり、リセット信号3
は同シフトレジスタのクロック入力となるため同図のタ
イミングで波形を加えることによりシフトレジスタの状
態は(0,1,1,0)となりリセット信号3が1であれば論
理回路5の出力8は1のレベルとなりテストモードに入
る。The timing diagram of FIG. 3 shows the waveforms for entering the test mode with the arrangement of the present invention. The clock input signal 2 becomes the input data of the shift register 4, and the reset signal 3
Becomes the clock input of the same shift register, and the waveform of the shift register causes the state of the shift register to become (0,1,1,0). If the reset signal 3 is 1, the output 8 of the logic circuit 5 is It becomes level 1 and enters the test mode.
以上のように、複数段のシフトレジスタとシフトレジ
スタの各段の出力を入力とする論理回路を構成要素と
し、半導体集積回路に通常用いられるクロック入力をシ
フトレジスタのデータ入力部に接続し、リセット入力を
同シフトレジスタのクロック入力に接続する構成によ
り、従来必要としたテスト入力端子を設けることなく集
積回路のテストが可能となり、実装品の全ピンを本来の
機能を果すための端子として使用することができるとい
う効果が得られた。As described above, the shift register having a plurality of stages and the logic circuit having the outputs of the respective stages of the shift register as inputs are used as components, and the clock input normally used in the semiconductor integrated circuit is connected to the data input section of the shift register to reset. By connecting the input to the clock input of the same shift register, it is possible to test the integrated circuit without providing the conventionally required test input terminals, and all pins of the mounted product are used as terminals to perform the original functions. The effect of being able to do was obtained.
第1図は本発明の一実施例を示す回路図面。 第2図は第1図の実施例において本来の使われ方を示す
タイミング図。 第3図は第1図の実施例において効果を得るためのタイ
ミング図。 1……半導体集積回路 2……クロック入力端子 3……リセット入力端子 4……シフトレジスタ 5……論理回路 6……クロック入力用ゲート回路 7……リセット入力用ゲート回路 8……テストモード出力 9……内部クロック信号 10……内部リセット信号FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a timing chart showing the original usage in the embodiment of FIG. FIG. 3 is a timing chart for obtaining the effect in the embodiment of FIG. 1 ... Semiconductor integrated circuit 2 ... Clock input terminal 3 ... Reset input terminal 4 ... Shift register 5 ... Logic circuit 6 ... Clock input gate circuit 7 ... Reset input gate circuit 8 ... Test mode output 9: Internal clock signal 10: Internal reset signal
Claims (1)
モードとテストモードとを選択する半導体集積回路にお
いて、 前記半導体集積回路を初期化するリセット信号が入力さ
れるリセット端子と、 前記半導体集積回路の動作用クロック信号が入力される
クロック入力端子と、 前記リセット端子から入力された信号を各段のクロック
入力部に接続し、前記クロック入力端子から入力された
信号を初段のデータ入力部に接続し、各段の出力を順次
次段のデータ入力部に接続した複数段のシフトレジスタ
と、 前記複数段のシフトレジスタの各段の出力をそれぞれ入
力し、前記シフトレジスタ各段の出力があらかじめ決め
られた出力値となった時に前記テストモードを選択する
信号を発生する論理回路を有することを特徴とする半導
体集積回路。1. A semiconductor integrated circuit that selects a normal operation mode or a test mode according to a signal supplied from the outside, a reset terminal to which a reset signal for initializing the semiconductor integrated circuit is input, and the semiconductor integrated circuit. A clock input terminal to which the operation clock signal is input, and a signal input from the reset terminal is connected to the clock input section of each stage, and a signal input from the clock input terminal is connected to the data input section of the first stage. However, the output of each stage of the shift register is determined in advance by inputting the output of each stage of the shift register of the plurality of stages and the shift register of the plurality of stages in which the output of each stage is sequentially connected to the data input section of the next stage. A semiconductor integrated circuit having a logic circuit for generating a signal for selecting the test mode when the output value reaches a predetermined value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58251198A JP2552103B2 (en) | 1983-12-28 | 1983-12-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58251198A JP2552103B2 (en) | 1983-12-28 | 1983-12-28 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60142282A JPS60142282A (en) | 1985-07-27 |
JP2552103B2 true JP2552103B2 (en) | 1996-11-06 |
Family
ID=17219138
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58251198A Expired - Lifetime JP2552103B2 (en) | 1983-12-28 | 1983-12-28 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2552103B2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0545988Y2 (en) * | 1985-11-19 | 1993-11-30 | ||
JPS6438674A (en) * | 1987-08-04 | 1989-02-08 | Nippon Electric Ic Microcomput | Semiconductor integrated circuit |
JPH06118143A (en) * | 1992-10-01 | 1994-04-28 | Matsushita Electron Corp | Circuit and method for setting test mode |
JP2003515747A (en) * | 1999-11-29 | 2003-05-07 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method and integrated circuit for providing a test pattern to a single pin of a circuit |
JP2006332456A (en) * | 2005-05-27 | 2006-12-07 | Fujitsu Ltd | Semiconductor device and testing mode setting method |
JP7094119B2 (en) * | 2018-03-08 | 2022-07-01 | 三菱電機株式会社 | Test mode setting circuit |
-
1983
- 1983-12-28 JP JP58251198A patent/JP2552103B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS60142282A (en) | 1985-07-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |