JP2021530101A - 選択的二重層誘電体再成長を用いた完全な自己整合ビア - Google Patents
選択的二重層誘電体再成長を用いた完全な自己整合ビア Download PDFInfo
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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Abstract
Description
本出願は、2018年6月27日に出願された米国仮特許出願第62/690,838号明細書の利益を主張するものであり、この仮特許出願の内容全体が参照により本明細書に組み込まれる。
Claims (20)
- 基板を処理するための方法であって、
基板を提供するステップであって、前記基板は第1の誘電体層を含み、前記第1の誘電体層内には複数の導電性構造が形成され、前記第1の誘電体層の上面は前記導電性構造の上面と同じ高さである、ステップと、
前記導電性構造の上に導電性キャップ層を形成するステップであって、前記導電性キャップ層は、上面及び側壁を有して、前記導電性構造の上に選択的に配置される、ステップと、
前記第1の誘電体層の上に第2の誘電体層を形成するステップであって、前記第2の誘電体層は、前記導電性キャップ層の前記上面が覆われていない状態になり、前記導電性キャップ層の前記側壁が前記第2の誘電体層によって取り囲まれるように、前記第1の誘電体層の上に選択的に配置される、ステップと、
前記第2の誘電体層の上に第3の誘電体層を形成するステップであって、前記第3の誘電体層は、前記導電性キャップ層の前記上面が覆われていない状態になり、且つ前記第3の誘電体層の上面よりも低くなるように、前記第2の誘電体層の上に選択的に配置される、ステップと、
前記複数の導電性構造及び前記第3の誘電体層の上に第4の誘電体層を形成するステップと、
前記第4の誘電体層の内部に相互接続構造を形成するステップであって、前記相互接続構造はビア構造を含み、前記ビア構造は第1の部分及び第2の部分を有し、前記第1の部分は、前記導電性キャップ層の上に配置され、前記第1の部分の側壁は前記第3の誘電体層によって取り囲まれ、前記第2の部分は、前記第1の部分及び前記第3の誘電体層の上に配置される、ステップと
を含む方法。 - 前記導電性キャップ層は、前記第2の誘電体層が形成された後で、前記複数の導電性構造の上に選択的に堆積される、請求項1に記載の方法。
- 前記ビア構造の前記第2の部分は、トレンチ構造と前記ビア構造の前記第1の部分との間に配置され、前記ビア構造のビア抵抗を低減するように、前記ビア構造の前記第1の部分よりも大きな限界寸法を有する、請求項1に記載の方法。
- 前記導電性キャップ層は、ルテニウム、タングステン、ニッケル、又はコバルトのうちの少なくとも1つを含む、請求項1に記載の方法。
- 前記第2の誘電体層の高さは、前記第3の誘電体層の高さの少なくとも2倍である、請求項1に記載の方法。
- 前記第3の誘電体層は金属含有誘電体材料でできている、請求項1に記載の方法。
- 前記第2の誘電体層及び前記第3の誘電体層の両方が同じ堆積チャンバ内で形成される、請求項1に記載の方法。
- 前記導電性キャップ層、前記第2及び前記第3の誘電体層は、共通の処理ツールを使用することにより形成され、前記共通の処理ツールは、前記導電性キャップ層、前記第2の誘電体層、及び前記第3の誘電体層をそれぞれ形成するように構成されている1つ又は複数のチャンバを含む、請求項1に記載の方法。
- 前記第4の誘電体層の内部に前記相互接続構造を形成するステップは、更に、
エッチングプロセスを通じて前記第4の誘電体層内に相互接続開口部を形成するステップであって、前記相互接続開口部は、トレンチ開口部、及び前記トレンチ開口部の下に配置され、前記複数の導電性構造のうちの1つを露出させるビア開口部を含む、ステップと、
バリア層を形成して、前記相互接続開口部、及び前記複数の導電性構造のうちの前記覆われていない1つを覆うステップと、
導電層を前記バリア層の上に形成して前記相互接続開口部を充填するステップであって、前記導電層は、前記第4の誘電体層の上面を更に覆う、ステップと、
表面平坦化処理を実施して、前記第4の誘電体層の前記上面上の過剰な導電層を除去するステップと、を含む、請求項1に記載の方法。 - 前記第3の誘電体層は、前記相互接続開口部が前記第4の誘電体層内に形成されるときに、エッチング処理から前記第2の誘電体層を保護するように構成されている、請求項9に記載の方法。
- 前記第2の誘電体層が、前記導電性構造と前記相互接続構造との間の電気的短絡を防止するように、前記第2の誘電体層の高さは3nm〜15nmの範囲内である、請求項5に記載の方法。
- 半導体デバイスであって、
第1の誘電体層内に形成される複数の導電性構造であって、前記複数の導電性構造の上面及び前記第1の誘電体層の上面は、同一平面上にある、複数の導電性構造と、
上面及び側壁を有して、前記導電性構造の上に選択的に配置される導電性キャップ層と、
第2の誘電体層であって、前記導電性キャップ層の前記側壁が前記第2の誘電体層によって取り囲まれるように、前記第1の誘電体層の上に選択的に配置される、第2の誘電体層と、
第3の誘電体層であって、前記導電性キャップ層の上面が、前記第3の誘電体層の上面よりも低くなるように、前記第2の誘電体層の上に選択的に配置される、第3の誘電体層と、
前記複数の導電性構造及び前記第3の誘電体層の上に配置された第4の誘電体層と、
前記第4の誘電体層内に形成される相互接続構造であって、前記相互接続構造はトレンチ構造、及び前記トレンチ構造の下に配置され前記トレンチ構造に接続されるビア構造を含み、前記ビア構造は第1の部分及び第2の部分を有し、前記第1の部分は前記導電性キャップ層の上に配置され、前記第1の部分の側壁は前記第3の誘電体層によって取り囲まれ、前記第2の部分は前記第1の部分及び前記第3の誘電体層の上に配置される、相互接続構造と
を含む半導体デバイス。 - 前記ビア構造の前記第2の部分は、前記トレンチ構造と前記ビア構造の前記第1の部分との間に配置され、前記ビア構造のビア抵抗を低減するように、前記ビア構造の前記第1の部分よりも大きな限界寸法を有する、請求項12に記載の半導体デバイス。
- 前記ビア構造の前記第1の部分は、前記複数の導電性構造のうちの前記1つに電気的に結合されている、請求項12に記載の半導体デバイス。
- 前記導電性キャップ層は、ルテニウム、タングステン、ニッケル、又はコバルトのうちの少なくとも1つを含む、請求項12に記載の半導体デバイス。
- 前記第2の誘電体層の高さは、前記第3の誘電体層の高さの少なくとも2倍である、請求項12に記載の半導体デバイス。
- 前記第3の誘電体層は金属含有誘電体材料でできている、請求項12に記載の半導体デバイス。
- 半導体デバイスであって、
第1の誘電体層内に形成される第1の導電性構造であって、前記第1の導電性構造は、前記第1の誘電体層の上面から前記第1の誘電体層の中へと延びる、第1の導電性構造と、
上面及び側壁を有して、前記第1の導電性構造の上に選択的に配置される、導電性キャップ層と、
前記第1の誘電体層の上に選択的に配置される誘電体スタックであって、前記導電性キャップ層の前記側壁は前記誘電体スタックによって取り囲まれ、前記誘電体スタックの上面は前記導電性キャップ層の前記上面よりも高い、誘電体スタックと、
前記第1の導電性構造の上に形成される第2の導電性構造であって、前記第2の導電性構造は第1の部分及び第2の部分を有し、前記第1の部分は前記導電性キャップ層の上に配置され、前記第1の部分の側壁は前記誘電体スタックによって取り囲まれ、前記第2の部分は前記第1の部分及び前記誘電体スタックの上に配置され、前記第2の導電性構造の前記第2の部分は、前記第2の導電性構造の抵抗を低減するように、前記第2の導電性構造の前記第1の部分よりも大きな限界寸法を有する、第2の導電性構造と
を含む半導体デバイス。 - 前記誘電体スタックは、前記第1の誘電体層の上に配置された第2の誘電体層と、前記第2の誘電体層の上に配置された第3の誘電体層と、を含む、請求項18に記載の半導体デバイス。
- 前記第2の誘電体層の高さは、前記第3の誘電体層の高さの少なくとも2倍である、請求項19に記載の半導体デバイス。
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