JP2021521629A - トランジスタを製造する方法 - Google Patents
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- 239000001301 oxygen Substances 0.000 claims description 6
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- 238000001020 plasma etching Methods 0.000 claims description 5
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- 238000002955 isolation Methods 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
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- 229910052786 argon Inorganic materials 0.000 claims description 2
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- 239000012159 carrier gas Substances 0.000 claims description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
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- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
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Abstract
Description
Claims (20)
- トランジスタを製造する方法であって、
半導体基板上に第1の誘電体層を形成すること、
前記第1の誘電体層上に障壁層を堆積すること、
前記障壁層上に反射防止コーティングを堆積すること、
フォトレジスト層を堆積すること、
前記フォトレジスト層におけるパターンを放射に曝すこと、
前記フォトレジスト層に開口を提供するために、前記パターンに従って前記フォトレジスト層をエッチングすること、
前記フォトレジスト層における前記開口の下の反射防止コーティングの一部をエッチングすること、
前記第1の誘電体層の一部を露出させるため、前記開口の下の前記障壁層の一部をエッチングすること、
酸化物領域を成長させるため、前記開口の下の前記障壁層の前記一部をエッチした後、雰囲気酸化剤を提供すること、
前記雰囲気酸化剤を提供した後、前記障壁層を除去すること、
前記障壁層を取り除いた後、前記半導体基板内にドーパントを注入すること、
前記半導体基板にドーパントを注入した後、前記第1の誘電体層を除去すること、
前記第1の誘電体層を除去した後、第2の誘電体層を形成することであって、前記酸化物領域が前記第2の誘電体層より厚くなるように成長されること、
を含む、方法。 - 請求項1の方法であって、
シャロートレンチアイソレーション(STI)領域を形成すること、及び
前記第2の誘電体層よりもより厚い、第3の誘電体層を形成すること、
を更に含む、方法。 - 請求項1の方法であって、
前記第2の誘電体層上に第2のフォトレジスト層を堆積すること、
前記第2のフォトレジスト層における第2のパターンを放射に曝すこと、
前記第2のフォトレジスト層に開口を提供するため、前記第2のパターンに従って前記第2のフォトレジスト層をエッチングすること、
前記第2のフォトレジスト層の前記開口を介して、第2の誘電体層上に導電性材料を堆積すること、
を更に含む、方法。 - 請求項3に記載の方法であって、前記半導体基板上に前記第1の誘電体層を形成する前に、更に、前記半導体基板上にエピタキシャル層を成長させることを含む、方法。
- 請求項4に記載の方法であって、前記エピタキシャル層を成長させる前に、更に、前記半導体基板にドーパントを注入してn型埋め込み層を形成することを含む、方法。
- 請求項5に記載の方法であって、前記半導体基板にドーパントを注入することが前記半導体基板にドレイン領域を形成する、方法。
- 請求項1の方法であって、前記雰囲気酸化剤を提供することが、約900℃で前記半導体基板を前記雰囲気酸化剤に曝すことを含む、方法。
- 請求項1の方法であって、前記酸化剤が酸素又は蒸気を含む、方法。
- 請求項1の方法であって、前記第1及び第2の誘電体層がそれぞれ二酸化シリコンを含む、方法。
- 請求項1の方法であって、前記雰囲気酸化剤を提供することが、前記酸化物領域を、前記半導体基板の中及び上に、少なくとも400オングストロームの厚みまで成長させることを含む、方法。
- 請求項1の方法であって、前記前記障壁層が、300オングストローム〜1000オングストロームの厚みを有する、方法。
- 請求項1の方法であって、前記前記障壁層がシリコン窒化物を含む、方法。
- 請求項1の方法であって、前記開口の下の前記反射防止コーティング及び前記前記障壁層の部分をエッチングすることが、プラズマ反応性イオンエッチング(RIE)を含む、方法。
- 請求項13の方法であって、前記プラズマRIEが、酸素(O2)、キャリア気体、又は、x=1又は2、y=0、1、2、3、又は4、及び、z=1、2、3、又は4の化学量論CxHyFzを有する炭素(C)、水素(H)、及びフッ素(F)を含むフッ化炭素の気体混合物を用いることを含む、方法。
- 請求項14に記載の方法であって、前記気体がアルゴン及び酸素を含む、方法。
- 請求項15に記載の方法であって、前記前記障壁層が、300オングストローム〜1000オングストロームの厚みを有するシリコン窒化物を含む、方法。
- 請求項1に記載の方法であって、前記雰囲気酸化剤を提供することが、前記酸化物領域を前記半導体基板の中及び上に成長させることを含み、前記酸化物領域が少なくとも400オングストロームの厚みを有する、方法。
- トランジスタを製造する方法であって、
半導体基板上に犠牲酸化物層を形成すること、
前記犠牲酸化物層上にシリコン窒化物層を堆積すること、
前記シリコン窒化物層上に反射防止コーティングを堆積すること、
フォトレジスト層を堆積すること、
前記フォトレジスト層におけるパターンを放射に曝すこと、
前記フォトレジスト層内に開口を提供するため、前記パターンに従って前記フォトレジスト層をエッチングすること、
前記開口の下の前記反射性防止コーティングの一部をエッチングすること、
前記犠牲酸化物層の一部を露出させるため、前記開口の下の前記シリコン窒化物層の一部をエッチングすること、
前記犠牲酸化物層の前記露出された部分上に酸化物領域を成長させること、
前記酸化物領域を成長させた後、前記シリコン窒化物層を取り除くこと、
前記シリコン窒化物層を除去した後、前記半導体基板にドーパントを注入すること、
前記半導体基板にドーパントを注入した後、前記犠牲酸化物層を取り除くこと、及び
前記犠牲酸化物層を除去した後に前記半導体基板上にゲート酸化物層を形成することであって、前記酸化物領域が、前記ゲート酸化物層の厚みよりも厚く成長されること、
を含む、方法。 - 請求項18に記載の方法であって、前記犠牲酸化物層の前記露出された部分上に前記酸化物領域を成長させることが、前記酸化物領域を少なくとも400オングストロームの厚みまで成長させることを含む、方法。
- トランジスタを製造する方法であって、
半導体基板上に犠牲酸化物層を形成すること、
前記犠牲酸化物層上にシリコン窒化物層を堆積すること、
フォトレジスト層を堆積すること、
前記フォトレジスト層内におけるパターンを放射に曝すこと、
前記フォトレジスト層に開口を提供するため、前記パターンに従って前記フォトレジスト層をエッチングすること、
前記犠牲酸化物層の一部を露出させるため、前記開口の下の前記シリコン窒化物層の一部をエッチングすること、
前記犠牲酸化物層の前記露出された部分上に少なくとも400オングストロームの厚さの酸化物領域を成長させること、
前記酸化物領域を成長させた後、前記シリコン窒化物層を取り除くこと、
前記半導体基板内にドレイン領域を形成するため、前記シリコン窒化物層を除去した後に半導体基板内にドーパントを注入すること、
前記半導体基板にドーパントを注入した後に前記犠牲酸化物層を除去すること、及び
前記犠牲酸化物層を除去した後に半導体基板上にゲート酸化物層を形成すること、
を含み、
前記ゲート酸化物層が400オングストローム未満の厚みを有する、
方法。
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US15/944,550 US10566200B2 (en) | 2018-04-03 | 2018-04-03 | Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings |
PCT/US2019/025599 WO2019195435A1 (en) | 2018-04-03 | 2019-04-03 | Method of fabricating transistors |
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CN112074932A (zh) | 2020-12-11 |
US10566200B2 (en) | 2020-02-18 |
WO2019195435A1 (en) | 2019-10-10 |
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