JP2020148916A - 電気光学装置および電子機器 - Google Patents
電気光学装置および電子機器 Download PDFInfo
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- JP2020148916A JP2020148916A JP2019046677A JP2019046677A JP2020148916A JP 2020148916 A JP2020148916 A JP 2020148916A JP 2019046677 A JP2019046677 A JP 2019046677A JP 2019046677 A JP2019046677 A JP 2019046677A JP 2020148916 A JP2020148916 A JP 2020148916A
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Abstract
Description
本発明の電気光学装置の一例として、アクティブマトリックス方式の液晶装置を例に説明する。
図1は、本実施形態における電気光学装置100の平面図である。図2は、本実施形態における電気光学装置100の断面図であって、図1中のA−A線断面図である。なお、以下では、説明の便宜上、図1および図2のそれぞれに示す互いに直交するx軸、y軸、およびz軸を適宜用いて説明する。以下では、各軸の方向を示す矢印の先端側を「+側」、基端側を「−側」という。また、x軸のうち矢印の指す方向を+x方向、その反対方向を−x方向とする。なお、y軸およびz軸についても同様である。本実施形態では、「第1方向」は+y方向であり、「第1方向」と交差する「第2方向」は−x方向である。また、後述する第1基体21と画素電極28とが重なる「第3方向」は−z方向である。また、−z方向から見ることを単に「平面視」と言う。
図3は、本実施形態における素子基板2の電気的な構成を示す等価回路図である。図3に示すように、素子基板2には、n本の走査線244と、m本のデータ線246と、n本の容量線としての第1定電位線245と、が設けられる。nおよびmはそれぞれ2以上の整数である。
図4は、本実施形態における画素回路部20が有する各種配線の一部を示す分解斜視図である。図4では、1つの画素Pに関わる各種配線が図示される。図4に示すように、画素回路部20は、遮光体241、トランジスター23、ソース配線242、ドレイン配線243、走査線244、第1定電位線245、蓄積容量256、データ線246、接続配線247および第2定電位線248を有する。トランジスター23、走査線244、第1定電位線245、蓄積容量256、データ線246および第2定電位線248は、この順に遮光体241から画素電極28に向かって配置される。また、遮光体241、トランジスター23、ソース配線242、ドレイン配線243、蓄積容量256および接続配線247は、前述の画素Pごとに設けられる。つまり、これらは、画素電極28ごとに設けられる。
以上に例示した各形態は多様に変形され得る。前述の各形態に適用され得る具体的な変形の態様を以下に例示する。以下の例示から任意に選択された2以上の態様は、相互に矛盾しない範囲で適宜に併合され得る。
前述の実施形態では、接続部280がコンタクト部281およびコンタクト部282で構成されるが、接続部280の構成はこれに限定されない。図7は、第1変形例における素子基板2Aの一部を模式的に示す断面図である。素子基板2Aが有する画素回路部20Aは、接続部280Aを有する。接続部280Aは、第1定電位線245と第2定電位線248とを直接的に接続する。つまり、接続部280Aは、第1定電位線245と第2定電位線248とを電極262を介さずに電気的に接続する。かかる構成によれば、第1定電位線245および第2定電位線248の低抵抗化を図ることができる。また、図7に示すように、素子基板2Aは、第2定電位線248と電極262とを電気的に接続するコンタクト部284を備える。コンタクト部284を設けることで、第2定電位線248を容量線として好適に用いることができる。
図8は、第2変形例における素子基板2Bの一部を模式的に示す断面図である。素子基板2Bが有する画素回路部20Bは、接続部280Bを有する。接続部280Bは、コンタクト部282Bとコンタクト部277を含み、第1定電位線245と第2定電位線248との間を電気的に接続するコンタクト部277は、第1定電位線245と電極251とを電気的に接続する。コンタクト部282Bは、第2定電位線248と電極251とを電気的に接続する。図8に示す例では、コンタクト部277が、第1定電位線245と電極251を接続する「第1接続部」に相当する。コンタクト部282Bが、第2定電位線248と電極251とを接続する「第2接続部」に相当する。また、電極251が「第1電極」に相当し、電極252が「第2電極」に相当し、「誘電体」が誘電体層253に相当する。
前述の実施形態では、全ての画素Pにおいて、接続部280が設けられるが、全ての画素Pのうちの、いくつかの任意の画素Pにのみ接続部280が設けられていてもよい。ただし、すべての画素Pにおいて接続部280が設けられていることで、表示ムラを特に効果的に低減することができる。
前述の実施形態では、第1容量25および第2容量26は、第1定電位線245と第2定電位線248との間の層に配置されるが、第1容量25および第2容量26の各配置は、これに限定されず任意である。例えば、第2容量26は、第2定電位線248と画素電極28との間の層に配置されてもよい。また、蓄積容量256は、第1容量25と第2容量26を有するが、蓄積容量256は、1つの容量で構成されてもよい。
前述の実施形態では、第1定電位線245および第2定電位線248は、それぞれ容量線として機能するが、これら双方またはいずれか一方は、容量線として機能しなくてもよい。なお、双方が容量線として機能しない場合には容量線を別途用いる必要があるため、少なくとも一方が容量線として機能することが好ましい。少なくとも一方が容量線として機能することで、容量線を別途用いる場合に比べ、素子基板2の厚さを薄くすることができ、光学特性の低下を抑制することができる。
前述の実施形態では、第1定電位線245は、走査線244よりも+z軸側に配置されるが、各種配線の配置等によって、第1定電位線245は走査線244よりも−z軸側に配置されてもよい。同様に、前述の実施形態では、第2定電位線248は、データ線246よりも+z軸側に配置されるが、各種配線の配置等によって、第2定電位線248は、データ線246より−z軸側に配置されてもよい。
前述の実施形態では、第1定電位線245は、平面視で走査線244と重なっていなくてもよい。同様に、第2定電位線248は、平面視でデータ線246と重なっていなくてもよい。
前述の実施形態では、「トランジスター」がTFTである場合を例に説明したが、「トランジスター」は、これに限定されず、例えば、MOSFET(metal-oxide-semiconductor field-effect transistor)等であってもよい。
電気光学装置100は、各種電子機器に用いることができる。
Claims (6)
- 基板と、
前記基板上に配置される画素電極と、
前記基板と前記画素電極との間に配置される画素回路部と、を備え、
前記画素回路部は、
第1方向に沿って配置される走査線と、
前記第1方向と交差する第2方向に沿って配置されるデータ線と、
前記走査線に沿って配置される第1定電位線と、
前記データ線に沿って配置される第2定電位線と、
前記走査線と前記データ線との交差位置に対応して配置され、前記走査線に電気的に接続されるゲート電極、前記データ線に電気的に接続されるソース領域、および前記画素電極に電気的に接続されるドレイン領域を含むトランジスターと、
前記交差位置に対応して配置され、前記第1定電位線と前記第2定電位線とを電気的に接続する接続部と、を備えることを特徴とする電気光学装置。 - 第1電極と、前記ドレイン領域に電気的に接続される第2電極と、前記第1電極と前記第2電極との間に配置される誘電体とを有する蓄積容量を、さらに備え、
前記接続部は、
前記第1定電位線と前記第1電極とを接続する第1接続部と、
前記第2定電位線と前記第1電極とを接続する第2接続部と、を有する請求項1に記載の電気光学装置。 - 前記蓄積容量は、前記第1定電位線と前記第2定電位線との間の層に配置される請求項2に記載の電気光学装置。
- 前記第1定電位線は、前記走査線と前記蓄積容量との間の層に配置され、
前記第2定電位線は、前記データ線と前記画素電極との間の層に配置される請求項2または3に記載の電気光学装置。 - 前記第1定電位線は、前記基板と前記画素電極とが重なる第3方向から見て、前記走査線と重なり、
前記第2定電位線は、前記第3方向から見て、前記データ線と重なる請求項1ないし4のいずれか1項に記載の電気光学装置。 - 請求項1ないし5のいずれか1項に記載の電気光学装置を備えることを特徴とする電子機器。
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