JP2020011878A - 炭化珪素ウェハを含む半導体ウェハおよびSiC半導体装置の製造方法 - Google Patents
炭化珪素ウェハを含む半導体ウェハおよびSiC半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 111
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 111
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000011156 evaluation Methods 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims description 30
- 238000012545 processing Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000000059 patterning Methods 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 description 138
- 239000010410 layer Substances 0.000 description 60
- 238000005259 measurement Methods 0.000 description 60
- 238000012937 correction Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 238000005286 illumination Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000012286 potassium permanganate Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
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Abstract
Description
第1実施形態について説明する。ここでは、ステッパを用いたSiC半導体装置の製造方法について説明する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
2 ウェハステージ
4 露光光源
7 投光部
8 受光部
9 制御部
10 半導体ウェハ
10a SiCウェハ
10b エピ層
11 レジスト
Claims (6)
- 炭化珪素ウェハ(10a)の表面に炭化珪素にて構成されたエピタキシャル層(10b)を備えた半導体ウェハであって、
前記エピタキシャル層の表面の平坦度の評価を行う表面形状測定装置にて、評価エリア内において前記エピタキシャル層の複数点での高さ測定を行うと共に、該測定した高さに基づく最小二乗法での演算を行うことで表面基準面を決定し、前記評価エリアと中心位置が同じとされ、かつ、前記評価エリアと異なる範囲とされた露光エリア内において、前記表面基準面を基準として最も高い位置の高さをα、最も低い位置の高さをβとし、うねり値を|α|+|β|としたときに、前記うねり値が1μm以下の条件を満たしている半導体ウェハ。 - 前記炭化珪素ウェハのうちの外縁の5μmを含む領域を無効エリア、該無効エリアを除いた領域を有効エリアとして、前記有効エリア内において、複数の前記露光エリアが設定され、複数の前記露光エリアのうちの90%以上において、前記うねり値が1μm以下の条件を満たしている請求項1に記載の半導体ウェハ。
- 炭化珪素ウェハ(10a、21)の表面に炭化珪素にて構成されたエピタキシャル層(10b、22)を備えた半導体ウェハ(10)を用いて半導体素子(21〜32)の形成を行う炭化珪素半導体装置の製造方法であって、
前記炭化珪素ウェハを用意することと、
前記炭化珪素ウェハの表面に前記エピタキシャル層をエピタキシャル成長させることと、
表面形状測定装置にて、前記エピタキシャル層の表面の平坦度の評価を行うことと、
前記平坦度の評価後の前記半導体ウェハを用いて、前記半導体素子の形成を行うことと、を含み、
前記平坦度の評価を行うことは、前記表面形状測定装置により、評価エリア内において、前記エピタキシャル層の複数点での高さ測定を行った後、該測定した高さに基づく最小二乗法での演算を行うことで表面基準面を決定し、さらに、前記評価エリアと中心位置が同じとされ、かつ、前記評価エリアと異なる範囲とされた露光エリア内において、前記表面基準面を基準として最も高い位置の高さをα、最も低い位置の高さをβとし、うねり値を|α|+|β|として、前記露光エリア毎の前記うねり値を求め、該うねり値が1μm以下の条件を満たしている前記半導体ウェハを得る炭化珪素半導体装置の製造方法。 - 前記平坦度の評価を行うことは、前記炭化珪素ウェハのうちの外縁の5μmを含む領域を無効エリア、該無効エリアを除いた領域を有効エリアとして、前記有効エリア内において、複数の前記露光エリアを設定し、複数の前記露光エリアのうちの90%以上において、前記うねり値が1μm以下の条件を満たしている前記半導体ウェハを得る請求項3に記載の炭化珪素半導体装置の製造方法。
- 前記半導体素子の形成を行うことでは、該半導体素子の構成要素の最小加工寸法が0.3〜0.8μmとされている請求項3または4に記載の炭化珪素半導体装置の製造方法。
- 前記半導体素子の形成を行うことでは、前記半導体素子として縦型MOSFETを形成する請求項3ないし5のいずれか1つに記載の炭化珪素半導体装置の製造方法。
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JP2018136668A JP7135531B2 (ja) | 2018-07-20 | 2018-07-20 | 炭化珪素半導体装置の製造方法 |
PCT/JP2019/028317 WO2020017601A1 (ja) | 2018-07-20 | 2019-07-18 | 炭化珪素ウェハを含む半導体ウェハおよびSiC半導体装置の製造方法 |
CN201980047401.3A CN112424402B (zh) | 2018-07-20 | 2019-07-18 | 包含碳化硅晶片的半导体晶片以及SiC半导体装置的制造方法 |
US17/151,821 US11348844B2 (en) | 2018-07-20 | 2021-01-19 | Semiconductor wafer including silicon carbide wafer and method for manufacturing silicon carbide semiconductor device |
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JP2021128949A (ja) * | 2020-02-10 | 2021-09-02 | 株式会社デンソー | ワイドバンドギャップ半導体装置の製造方法 |
WO2023218809A1 (ja) * | 2022-05-11 | 2023-11-16 | 住友電気工業株式会社 | 炭化珪素基板、炭化珪素エピタキシャル基板、炭化珪素基板の製造方法および炭化珪素半導体装置の製造方法 |
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JP2016501809A (ja) * | 2012-10-26 | 2016-01-21 | ダウ コーニング コーポレーションDow Corning Corporation | 平坦なSiC半導体基板 |
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JP5542325B2 (ja) | 2008-12-02 | 2014-07-09 | 昭和電工株式会社 | 半導体デバイスの製造方法 |
CN107532327B (zh) * | 2015-05-11 | 2019-12-17 | 住友电气工业株式会社 | 碳化硅单晶衬底、碳化硅半导体器件以及制造碳化硅半导体器件的方法 |
JP6260603B2 (ja) * | 2015-11-05 | 2018-01-17 | 住友電気工業株式会社 | 炭化珪素単結晶基板、炭化珪素エピタキシャル基板およびこれらの製造方法 |
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JP2021128949A (ja) * | 2020-02-10 | 2021-09-02 | 株式会社デンソー | ワイドバンドギャップ半導体装置の製造方法 |
JP7287304B2 (ja) | 2020-02-10 | 2023-06-06 | 株式会社デンソー | ワイドバンドギャップ半導体装置の製造方法 |
WO2023218809A1 (ja) * | 2022-05-11 | 2023-11-16 | 住友電気工業株式会社 | 炭化珪素基板、炭化珪素エピタキシャル基板、炭化珪素基板の製造方法および炭化珪素半導体装置の製造方法 |
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JP7135531B2 (ja) | 2022-09-13 |
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US20210143070A1 (en) | 2021-05-13 |
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