JP2019169609A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2019169609A JP2019169609A JP2018056220A JP2018056220A JP2019169609A JP 2019169609 A JP2019169609 A JP 2019169609A JP 2018056220 A JP2018056220 A JP 2018056220A JP 2018056220 A JP2018056220 A JP 2018056220A JP 2019169609 A JP2019169609 A JP 2019169609A
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Abstract
Description
第1の実施形態の半導体装置は、枠体と、枠体の中に設けられた基板と、基板の上に設けられ、第1の上部電極と、第1の下部電極と、第1のゲート電極と、を有する第1の半導体チップと、枠体の外に第1の方向に設けられた第1の第一極端子と、枠体の外に第1の方向と反対方向の第2の方向に設けられた第2の第一極端子を有し、一部が枠体の中に設けられた板状の第一極電極と、枠体の外に第1の方向に設けられた第1の第二極端子と、枠体の外に第2の方向に設けられた第2の第二極端子を有し、一部が枠体の中に設けられ、第一極電極に対向して設けられた板状の第二極電極と、を備える。
第2の実施形態の半導体装置は、第一極電極が、枠体の第1の方向と垂直な第3の方向に設けられた第3の第一極端子と、枠体の外に第3の方向と反対方向の第4の方向に設けられた第4の第一極端子を有し、第二極電極が、枠体の第1の方向と垂直な第3の方向に設けられた第3の第二極端子と、枠体の外に第3の方向と反対方向の第4の方向に設けられた第4の第二極端子を有する点で、第1の実施形態と異なっている。以下、第1の実施形態と重複する内容については、記述を省略する。
第3の実施形態の半導体装置は、第一極電極及び第二極電極の少なくともいずれか一方が、ストライプパターン又はメッシュパターンを有する点で、第1の実施形態と異なっている。以下、第1の実施形態と重複する内容については、記述を省略する。
第4の実施形態の半導体装置は、第一極電極と第二極電極との間に、シリコーンゲルよりも誘電率の高い絶縁層が設けられる点で、第1の実施形態と異なっている。以下、第1の実施形態と重複する内容については、記述を省略する。
第5の実施形態の半導体装置は、枠体が、第1の方向に凸部、第2の方向に凹部を有し、第1の第一極端子及び第1の第二極端子が凸部に設けられ、第2の第一極端子及び第2の第二極端子が凹部に設けられる点で、第1の実施形態と異なっている。以下、第1の実施形態と重複する内容については、記述を省略する。
10a 凸部
10b 凹部
14 N電極(第一極電極)
14a 第1のN端子(第1の第一極端子)
14b 第2のN端子(第2の第一極端子)
14c 第3のN端子(第3の第一極端子)
14d 第4のN端子(第4の第一極端子)
16 P電極(第二極電極)
16a 第1のP端子(第1の第二極端子)
16b 第2のP端子(第2の第二極端子)
16c 第3のP端子(第3の第二極端子)
16d 第4のP端子(第4の第二極端子)
18a 第1のAC出力端子(出力端子)
24 絶縁基板(基板)
38 MOSFET(第1の半導体チップ)
38a ソース電極(第1の上部電極)
38b ドレイン電極(第1の下部電極)
38c ゲート電極(第1のゲート電極)
40 MOSFET(第2の半導体チップ)
40a ソース電極(第2の上部電極)
40b ドレイン電極(第2の下部電極)
40c ゲート電極(第2のゲート電極)
44 シリコーンゲル
60 絶縁層
100 パワー半導体モジュール(半導体装置)
200 パワー半導体モジュール(半導体装置)
300 パワー半導体モジュール(半導体装置)
400 パワー半導体モジュール(半導体装置)
500 パワー半導体モジュール(半導体装置)
P1 平面
P2 平面
P3 平面
P4 平面
Claims (8)
- 枠体と、
前記枠体の中に設けられた基板と、
前記基板の上に設けられ、第1の上部電極と、第1の下部電極と、第1のゲート電極と、を有する第1の半導体チップと、
前記枠体の外に第1の方向に設けられた第1の第一極端子と、前記枠体の外に前記第1の方向と反対方向の第2の方向に設けられた第2の第一極端子を有し、一部が前記枠体の中に設けられた板状の第一極電極と、
前記枠体の外に前記第1の方向に設けられた第1の第二極端子と、前記枠体の外に前記第2の方向に設けられた第2の第二極端子を有し、一部が前記枠体の中に設けられ、前記第一極電極に対向して設けられた板状の第二極電極と、
を備えた半導体装置。 - 前記基板の上に設けられ、第2の上部電極と、第2の下部電極と、第2のゲート電極と、を有する第2の半導体チップと、
前記枠体の外に設けられた出力端子を、更に備え、
前記第一極電極が前記第1の上部電極に電気的に接続され、
前記第二極電極が前記第2の下部電極に電気的に接続され、
前記出力端子が前記第1の下部電極及び前記第2の上部電極に電気的に接続された請求項1記載の半導体装置。 - 前記第一極電極が、前記枠体の前記第1の方向と垂直な第3の方向に設けられた第3の第一極端子と、前記枠体の外に前記第3の方向と反対方向の第4の方向に設けられた第4の第一極端子を有し、
前記第二極電極が、前記枠体の前記第3の方向に設けられた第3の第二極端子と、前記枠体の外に前記第4の方向に設けられた第4の第二極端子を有する請求項1又は請求項2記載の半導体装置。 - 前記第一極電極及び前記第二極電極の少なくともいずれか一方が、ストライプパターン又はメッシュパターンを有する請求項1ないし請求項3いずれか一項記載の半導体装置。
- 前記第一極電極と前記第二極電極との間に、シリコーンゲルよりも誘電率の高い絶縁層が設けられた請求項1ないし請求項4いずれか一項記載の半導体装置。
- 前記枠体が、前記第1の方向に凸部、前記第2の方向に凹部を有し、前記第1の第一極端子及び前記第1の第二極端子が前記凸部に設けられ、前記第2の第一極端子及び前記第2の第二極端子が前記凹部に設けられた請求項1ないし請求項5いずれか一項記載の半導体装置。
- 前記第1の第一極端子と前記第2の第一極端子は、前記基板の法線を法線とする異なる2つの平面内に存在し、前記第1の第二極端子と前記第2の第二極端子は、前記基板の法線を法線とする異なる2つの平面内に存在する請求項1ないし請求項6いずれか一項記載の半導体装置。
- 前記枠体の中にシリコーンゲルが充填された請求項1ないし請求項7いずれか一項記載の半導体装置。
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