JP2018182316A - 異種コンタクトを具備する集積回路、及びそれを含む半導体装置 - Google Patents
異種コンタクトを具備する集積回路、及びそれを含む半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title abstract description 25
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 12
- 238000013461 design Methods 0.000 claims description 11
- 101100382340 Arabidopsis thaliana CAM2 gene Proteins 0.000 description 16
- 101100494530 Brassica oleracea var. botrytis CAL-A gene Proteins 0.000 description 16
- 101100165913 Brassica oleracea var. italica CAL gene Proteins 0.000 description 16
- 101150118283 CAL1 gene Proteins 0.000 description 16
- 101100029577 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CDC43 gene Proteins 0.000 description 16
- 101100439683 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CHS3 gene Proteins 0.000 description 16
- 101150014174 calm gene Proteins 0.000 description 16
- 101150041156 CBL1 gene Proteins 0.000 description 13
- 101150052795 cbh-1 gene Proteins 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 10
- 101000861263 Homo sapiens Steroid 21-hydroxylase Proteins 0.000 description 9
- 102100027545 Steroid 21-hydroxylase Human genes 0.000 description 9
- 230000006870 function Effects 0.000 description 9
- 101100229939 Mus musculus Gpsm1 gene Proteins 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000003786 synthesis reaction Methods 0.000 description 4
- 102100021849 Calretinin Human genes 0.000 description 3
- 101000898072 Homo sapiens Calretinin Proteins 0.000 description 3
- 101100006352 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CHS5 gene Proteins 0.000 description 3
- 229910010041 TiAlC Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 101150114858 cbh2 gene Proteins 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- CIWBSHSKHKDKBQ-JLAZNSOCSA-N Ascorbic acid Chemical compound OC[C@H](O)[C@H]1OC(=O)C(O)=C1O CIWBSHSKHKDKBQ-JLAZNSOCSA-N 0.000 description 1
- 229910052692 Dysprosium Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910052771 Terbium Inorganic materials 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- 230000004323 axial length Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Abstract
Description
100 SoC
110 システムバス
120 モデム
130 ディスプレイコントローラ
140 メモリ
150 外部メモリコントローラ
160 CPU
170 トランザクションユニット
180 PMIC
190 GPU
AC1 第1活性領域
AC2 第2活性領域
CAL1ないしCAL6 下部ソース/ドレインコンタクト
CO4,CO5,CO6 標準セル
GL1ないしGL4 ゲートライン
W1ないしW7 導電ライン
Claims (20)
- 基板上において、第1水平方向に延在される第1活性領域と、
前記第1活性領域上において、前記第1水平方向と交差する第2水平方向に延在されるゲートラインと、
前記第1活性領域上において、前記ゲートラインの一側に形成されたソース/ドレイン領域と、
前記ゲートライン上に離隔された平面上において、前記第1水平方向に延在された複数本の導電ラインであって、第1導電ライン及び第2導電ラインを含む複数本の導電ラインと、
前記ソース/ドレイン領域に接続された下面を有し、垂直方向に相互接続された下部ソース/ドレインコンタクト及び上部ソース/ドレインコンタクトを含むソース/ドレインコンタクトと、
前記ゲートラインに接続された下面を有し、垂直方向に延在されるゲートコンタクトと、を含み、
前記上部ソース/ドレインコンタクトは、前記第1導電ラインの下に位置し、
前記ゲートコンタクトは、前記第2導電ラインの下に位置することを特徴とする集積回路。 - 前記ゲートコンタクトは、垂直方向に相互接続された下部ゲートコンタクト及び上部ゲートコンタクトを含むことを特徴とする請求項1に記載の集積回路。
- 前記上部ソース/ドレインコンタクトは、前記第1導電ラインに接続され、
前記ゲートコンタクトは、前記第2導電ラインに接続されたことを特徴とする請求項1または2に記載の集積回路。 - 前記上部ソース/ドレインコンタクトと前記第1導電ラインとを接続する第1ビアと、
前記ゲートコンタクトと前記第2導電ラインとを接続する第2ビアと、をさらに含むことを特徴とする請求項1乃至3のいずれか一項に記載の集積回路。 - 前記第2導電ラインは、前記第1活性領域上に位置することを特徴とする請求項1乃至4のいずれか一項に記載の集積回路。
- 前記基板上において、前記第1水平方向に延在され、前記第1活性領域の第1導電型と異なる第2導電型を有し、前記ゲートラインと交差する第2活性領域をさらに含み、
前記第1活性領域及び第2活性領域は、前記基板上において、設計規則による活性領域間最小距離だけ離隔されたこと特徴とする請求項1乃至5のいずれか一項に記載の集積回路。 - 前記第2導電ラインは、前記第1活性領域及び第2活性領域の間の領域上に位置することを特徴とする請求項6に記載の集積回路。
- 前記複数本の導電ラインは、前記第2導電ラインに隣接し、前記第1活性領域及び第2活性領域の間に位置する第3導電ラインを含み、
前記ゲートライン、または他のゲートラインと、前記第3導電ラインとが交差する地点に配置されるゲートコンタクトをさらに含むことを特徴とする請求項7に記載の集積回路。 - 前記下部ソース/ドレインコンタクトの上面は、前記上部ソース/ドレインコンタクトの下面より広いことを特徴とする請求項1乃至8のいずれか一項に記載の集積回路。
- 基板上において、第1水平方向に相互平行に延在され、異なる導電型を有する第1活性領域及び第2活性領域と、
前記第1活性領域及び第2活性領域上において、前記第1水平方向と交差する第2水平方向に延在される複数本のゲートラインと、
前記第1活性領域及び第2活性領域の上において、前記複数本のゲートラインそれぞれの間に形成された複数のソース/ドレイン領域と、
前記複数本のゲートライン上に離隔された平面上において、前記第1水平方向に相互平行に延在された複数本の導電ラインと、
前記複数のソース/ドレイン領域のうち一つに接続された下面をそれぞれ有し、垂直方向にそれぞれ延在される複数のソース/ドレインコンタクトと、
前記複数本のゲートラインのうち1本に接続された下面をそれぞれ有し、垂直方向に相互接続された下部ゲートコンタクト及び上部ゲートコンタクトをそれぞれ含む複数のゲートコンタクトと、を含み、
前記ソース/ドレインコンタクト及び前記ゲートコンタクトの上部ゲートコンタクトは、前記複数本の導電ラインの下にそれぞれ位置することを特徴とする集積回路。 - 前記ソース/ドレインコンタクトは、垂直方向に相互接続された下部ソース/ドレインコンタクト及び上部ソース/ドレインコンタクトをそれぞれ含むことを特徴とする請求項10に記載の集積回路。
- 前記ソース/ドレインコンタクト及び前記ゲートコンタクトの上部ゲートコンタクトそれぞれは、前記複数本の導電ラインのうち少なくとも1本に接続されることを特徴とする請求項10または11に記載の集積回路。
- 前記ソース/ドレインコンタクトそれぞれを、前記複数本の導電ラインのうち少なくとも1本に接続する複数の第1ビアと、
前記ゲートコンタクトの上部ゲートコンタクトそれぞれを、前記複数本の導電ラインのうち少なくとも1本に接続する複数の第2ビアと、をさらに含むことを特徴とする請求項10乃至12のいずれか一項に記載の集積回路。 - 前記上部ゲートコンタクトのうち少なくとも一つは、前記第1活性領域上に位置することを特徴とする請求項10乃至13のいずれか一項に記載の集積回路。
- 前記基板上において、前記第2活性領域と隣接し、前記第1水平方向に延在され、前記第2活性領域と異なる導電型を有する第3活性領域をさらに含み、
前記基板上において、前記第1活性領域及び第2活性領域の間の距離は、前記第2活性領域及び第3活性領域の間の距離と同一であることを特徴とする請求項10乃至14のいずれか一項に記載の集積回路。 - 前記ゲートコンタクトのうち少なくとも1つの下部ゲートコンタクトは、前記第1水平方向に延在され、前記複数本のゲートラインのうち少なくとも2本を接続することを特徴とする請求項10乃至15のいずれか一項に記載の集積回路。
- 前記下部ゲートコンタクトの上面は、前記上部ゲートコンタクトの下面より広いことを特徴とする請求項10乃至16のいずれか一項に記載の集積回路。
- 基板上において、第1水平方向に相互平行に延在され、異なる導電型を有する第1活性領域及び第2活性領域と、
前記第1活性領域及び第2活性領域の上において、前記第1水平方向と交差する第2水平方向に延在される複数本のゲートラインと、
前記第1活性領域及び第2活性領域の上において、前記複数本のゲートラインそれぞれの間に形成された複数のソース/ドレイン領域と、
前記複数本のゲートライン上に離隔された平面上において、前記第1水平方向に相互平行に延在された複数本の導電ラインと、
前記複数のソース/ドレイン領域のうち一つに接続された下面をそれぞれ有し、垂直方向にそれぞれ延在される複数のソース/ドレインコンタクトと、
前記複数本のゲートラインのうち1本に接続された下面をそれぞれ有し、垂直方向にそれぞれ延在される複数のゲートコンタクトと、を含み、
前記複数のゲートコンタクトは、前記垂直方向に接続された下部ゲートコンタクト及び上部ゲートコンタクトを含むゲートコンタクトを含み、あるいは
前記複数のソース/ドレインコンタクトは、前記垂直方向に接続された下部ソース/ドレインコンタクト及び上部ソース/ドレインコンタクトを含む、
ことを特徴とする集積回路。 - 前記下部ソース/ドレインコンタクトの上面は、前記上部ソース/ドレインコンタクトの下面より広いことを特徴とする請求項18に記載の集積回路。
- 前記下部ゲートコンタクトの上面は、前記上部ゲートコンタクトの下面より広いことを特徴とする請求項18に記載の集積回路。
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