JP2017223953A - Stage and organic electric field light emitting display device using the same - Google Patents

Stage and organic electric field light emitting display device using the same Download PDF

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JP2017223953A
JP2017223953A JP2017117652A JP2017117652A JP2017223953A JP 2017223953 A JP2017223953 A JP 2017223953A JP 2017117652 A JP2017117652 A JP 2017117652A JP 2017117652 A JP2017117652 A JP 2017117652A JP 2017223953 A JP2017223953 A JP 2017223953A
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node
input terminal
voltage
transistor
supplied
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JP7025137B2 (en
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承 珪 李
Seung-Kyu Lee
承 珪 李
承 智 車
Seung Ji Cha
承 智 車
智 鉉 賈
Ji-Hyun Ka
智 鉉 賈
泰 勳 權
Tae-Hoon Kwon
泰 勳 權
敏 九 李
Min Ku Lee
敏 九 李
鎭 泰 鄭
Jin-Te Jeong
鎭 泰 鄭
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Samsung Display Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Shift Register Type Memory (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a stage that makes it possible to supply a light emitting control signal.SOLUTION: A stage comprises: an output unit for supplying voltages of a first power source or second power source in accordance with voltages of a first node and second node to an output terminal; an input unit for controlling the voltages of a third node and fourth node in accordance with signals to be supplied to a first input terminal and second input terminal; a first signal processing unit for controlling the voltage of the first node in accordance with the voltage of the second node; a second signal processing unit being connected to a fifth node and for controlling the voltage of the first node in accordance with a signal to be supplied to the third input terminal; a third signal processing unit for controlling the voltage of the fourth node in accordance with the voltage of the third node and a signal to be supplied to the third input terminal; and a first stabilization unit being connected to between the second signal processing unit and the input unit and for limiting a falling width of the voltages of the third node and fourth node.SELECTED DRAWING: Figure 4

Description

本発明は、ステージ及びこれを用いた有機電界発光表示装置に関する。特に、発光制御信号を供給することができるステージ及びこれを用いた有機電界発光表示装置に関する。 The present invention relates to a stage and an organic light emitting display device using the stage. In particular, the present invention relates to a stage that can supply a light emission control signal and an organic light emitting display using the same.

情報化技術が発達するにつれて、ユーザーと情報の間の接続媒体である表示装置の重要性が浮き彫りになっている。これに応じて、液晶表示装置（Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ Ｄｉｓｐｌａｙ Ｄｅｖｉｃｅ）及び有機電界発光表示装置（Ｏｒｇａｎｉｃ Ｌｉｇｈｔ Ｅｍｉｔｔｉｎｇ Ｄｉｓｐｌａｙ Ｄｅｖｉｃｅ）などの表示装置（Ｄｉｓｐｌａｙ Ｄｅｖｉｃｅ）の使用が増えている。 As information technology develops, the importance of display devices, which are connection media between users and information, is highlighted. Accordingly, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

平板表示装置のうち有機電界発光表示装置は、電子と正孔の再結合により光を発生させる有機発光ダイオード（Ｏｒｇａｎｉｃ Ｌｉｇｈｔ Ｅｍｉｔｔｉｎｇ Ｄｉｏｄｅ）を用いて映像を表示する。このような有機電界発光表示装置は、速い応答速度を有するとともに低い消費電力で駆動されるという利点がある。 Among the flat panel display devices, an organic light emitting display device displays an image using an organic light emitting diode that generates light by recombination of electrons and holes. Such an organic light emitting display device has an advantage that it has a high response speed and is driven with low power consumption.

有機電界発光表示装置は、データ線にデータ信号を供給するためのデータ駆動部と、走査線に走査信号を供給するための走査駆動部と、発光制御線に発光制御信号を供給するための発光駆動部と、データ線、走査線及び発光制御線に接続するように配置される画素と、を備える。 An organic light emitting display includes a data driver for supplying a data signal to a data line, a scan driver for supplying a scan signal to a scan line, and light emission for supplying a light emission control signal to a light emission control line. A driving unit; and a pixel arranged to be connected to the data line, the scanning line, and the light emission control line.

画素は、走査線に走査信号が供給されるときに選択され、データ線からデータ信号の供給を受ける。データ信号の供給を受けた画素は、データ信号に応じて所定の輝度の光を生成しながら映像を実現する。ここで、画素の発光時間は発光駆動部から供給される発光制御信号によって制御される。 A pixel is selected when a scanning signal is supplied to the scanning line, and receives a data signal from the data line. The pixels that are supplied with the data signal realize an image while generating light with a predetermined luminance in accordance with the data signal. Here, the light emission time of the pixel is controlled by a light emission control signal supplied from the light emission driver.

このため、発光駆動部は発光制御線のそれぞれと接続されるステージを備える。ステージは複数のクロック信号に応じて発光制御信号を生成し、生成された発光制御信号を発光制御線に供給する。 For this reason, the light emission driving unit includes a stage connected to each of the light emission control lines. The stage generates a light emission control signal according to a plurality of clock signals, and supplies the generated light emission control signal to the light emission control line.

上述のように、ステージは発光時間を制御する発光制御信号を生成する。ここで、発光制御信号が不安定な場合、望まない地点の画素が発光する恐れがある。したがって、安定的に発光制御信号を生成することができるステージが求められている。 As described above, the stage generates a light emission control signal for controlling the light emission time. Here, when the light emission control signal is unstable, a pixel at an undesired point may emit light. Accordingly, there is a need for a stage that can stably generate a light emission control signal.

韓国公開特許第１０−２０１４−００２５１４９号公報Korean Published Patent No. 10-2014-0025149

したがって、本発明は、安定的に発光制御信号を生成することができるステージ及びこれを用いた有機電界発光表示装置を提供するものである。 Accordingly, the present invention provides a stage capable of stably generating a light emission control signal and an organic light emitting display using the same.

本発明の一実施形態によるステージは、第１ノード及び第２ノードの電圧に応じて第１電源または第２電源の電圧を出力端子に供給するための出力部と、第１入力端子及び第２入力端子に供給される信号に応じて第３ノード及び第４ノードの電圧を制御するための入力部と、上記第２ノードの電圧に応じて上記第１ノードの電圧を制御するための第１信号処理部と、第５ノードに接続され、第３入力端子に供給される信号に応じて上記第１ノードの電圧を制御するための第２信号処理部と、上記第３ノードの電圧及び上記第３入力端子に供給される信号に応じて上記第４ノードの電圧を制御するための第３信号処理部と、上記第２信号処理部と上記入力部の間に接続され、上記第３ノード及び第４ノードの電圧の下降幅を制限するための第１安定化部と、を備える。 The stage according to an embodiment of the present invention includes an output unit for supplying a voltage of the first power source or the second power source to the output terminal according to the voltages of the first node and the second node, and the first input terminal and the second node. An input unit for controlling the voltages of the third node and the fourth node according to a signal supplied to the input terminal, and a first for controlling the voltage of the first node according to the voltage of the second node A signal processing unit; a second signal processing unit connected to the fifth node for controlling the voltage of the first node according to a signal supplied to the third input terminal; the voltage of the third node; A third signal processing unit for controlling a voltage of the fourth node according to a signal supplied to a third input terminal; and connected between the second signal processing unit and the input unit; And a first for limiting the voltage drop of the fourth node. It includes a Joka unit.

また、上記第１電源はゲートオフ電圧に設定され、上記第２電源はゲートオン電圧に設定されてもよい。 The first power source may be set to a gate-off voltage, and the second power source may be set to a gate-on voltage.

また、上記第１入力端子は、前段のステージの出力信号またはスタートパルスの供給を受けてもよい。 The first input terminal may receive an output signal or a start pulse from the previous stage.

また、上記第１入力端子に供給される前段のステージの出力信号またはスタートパルスは、上記第２入力端子に供給されるクロック信号と少なくとも一度重なってもよい。 The output signal or start pulse of the preceding stage supplied to the first input terminal may overlap at least once with the clock signal supplied to the second input terminal.

また、上記第２入力端子は第１クロック信号の供給を受け、第３入力端子は第２クロック信号の供給を受けてもよい。 The second input terminal may be supplied with a first clock signal, and the third input terminal may be supplied with a second clock signal.

また、上記第１クロック信号及び第２クロック信号は同じ周期を有し、上記第２クロック信号は上記第１クロック信号から半周期分だけシフトされた信号に設定されてもよい。 The first clock signal and the second clock signal may have the same period, and the second clock signal may be set to a signal shifted from the first clock signal by a half period.

また、上記第１安定化部は、上記第３ノードと上記第５ノードの間に接続され、ゲート電極が上記第２電源に接続される第１トランジスタと、上記第２ノードと上記第４ノードの間に接続され、ゲート電極が上記第２電源に接続される第２トランジスタと、を備えてもよい。 The first stabilization unit is connected between the third node and the fifth node, a first transistor having a gate electrode connected to the second power source, the second node, and the fourth node. And a second transistor having a gate electrode connected to the second power source.

また、上記入力部は、上記第１入力端子と上記第４ノードの間に接続され、ゲート電極が上記第２入力端子に接続される第７トランジスタと、上記第３ノードと上記第２入力端子の間に接続され、ゲート電極が上記第４ノードに接続される第８トランジスタと、上記第３ノードと上記第２電源の間に接続され、ゲート電極が上記第２入力端子に接続される第９トランジスタと、を備えてもよい。 The input unit is connected between the first input terminal and the fourth node, a seventh transistor having a gate electrode connected to the second input terminal, the third node, and the second input terminal. And an eighth transistor having a gate electrode connected to the fourth node, connected between the third node and the second power source, and having a gate electrode connected to the second input terminal. And 9 transistors.

また、上記出力部は、上記第１電源と上記出力端子の間に接続され、ゲート電極が上記第１ノードに接続される第１０トランジスタと、上記第２電源と上記出力端子の間に接続され、ゲート電極が上記第２ノードに接続される第１１トランジスタと、を備えてもよい。 The output unit is connected between the first power supply and the output terminal, and a gate electrode is connected between the second power supply and the output terminal. The tenth transistor has a gate electrode connected to the first node. And an eleventh transistor having a gate electrode connected to the second node.

また、上記第１信号処理部は、上記第１電源と上記第１ノードの間に接続され、ゲート電極が上記第２ノードに接続される第１２トランジスタと、上記第１電源と上記第１ノードの間に接続される第３キャパシタと、を備えてもよい。 The first signal processing unit is connected between the first power source and the first node, a twelfth transistor having a gate electrode connected to the second node, the first power source and the first node. A third capacitor connected between the first and second capacitors.

また、上記第２信号処理部は、上記第２ノードと上記第３入力端子の間に接続される第１キャパシタと、第１端子が上記第５ノードに接続される第２キャパシタと、上記第２キャパシタの第２端子と上記第１ノードの間に接続され、ゲート電極が上記第３入力端子に接続される第５トランジスタと、上記第２キャパシタの第２端子と上記第３入力端子の間に接続され、ゲート電極が上記第５ノードに接続される第６トランジスタと、を備えてもよい。 The second signal processing unit includes a first capacitor connected between the second node and the third input terminal, a second capacitor having a first terminal connected to the fifth node, and the second capacitor. A fifth transistor connected between the second terminal of the two capacitors and the first node and having a gate electrode connected to the third input terminal; and between the second terminal and the third input terminal of the second capacitor. And a sixth transistor having a gate electrode connected to the fifth node.

また、上記第３信号処理部は、第１電源と上記第４ノードの間に直列接続される第１３トランジスタ及び第１４トランジスタを備え、上記第１３トランジスタのゲート電極は上記第３ノードに接続され、上記第１４トランジスタのゲート電極は上記第３入力端子に接続されてもよい。 The third signal processing unit includes a thirteenth transistor and a fourteenth transistor connected in series between a first power source and the fourth node, and a gate electrode of the thirteenth transistor is connected to the third node. The gate electrode of the fourteenth transistor may be connected to the third input terminal.

また、上記第１電源、上記第１ノード、及び上記第３入力端子に接続され、上記出力端子に上記第１電源の電圧が出力される間上記第２ノードの電圧を一定に保持するための第２安定化部をさらに備えてもよい。 The second power supply is connected to the first power supply, the first node, and the third input terminal, and holds the voltage of the second node constant while the voltage of the first power supply is output to the output terminal. You may further provide a 2nd stabilization part.

また、上記第２安定化部は、上記第１電源と第６ノードの間に接続され、ゲート電極が上記第１ノードに接続される第３トランジスタと、上記第６ノードと上記第３入力端子の間に接続され、ゲート電極が上記第２ノードに接続される第４トランジスタと、上記第２ノードと上記第６ノードの間に接続される第１キャパシタと、を備えてもよい。 The second stabilizing unit is connected between the first power source and the sixth node, and a third transistor having a gate electrode connected to the first node, the sixth node, and the third input terminal. And a fourth transistor having a gate electrode connected to the second node, and a first capacitor connected between the second node and the sixth node.

また、上記第２信号処理部は、第１端子が上記第５ノードに接続される第２キャパシタと、上記第２キャパシタの第２端子と上記第１ノードの間に接続され、ゲート電極が上記第３入力端子に接続される第５トランジスタと、上記第２キャパシタの第２端子と上記第３入力端子の間に接続され、ゲート電極が上記第５ノードに接続される第６トランジスタと、を備えてもよい。 The second signal processing unit is connected between the second capacitor whose first terminal is connected to the fifth node, the second terminal of the second capacitor and the first node, and the gate electrode is A fifth transistor connected to the third input terminal; a sixth transistor connected between the second terminal of the second capacitor and the third input terminal and having a gate electrode connected to the fifth node; You may prepare.

本発明の一実施形態による有機電界発光表示装置は、走査線、データ線及び発光制御線と接続される画素と、上記走査線に走査信号を供給するための走査駆動部と、上記データ線にデータ信号を供給するためのデータ駆動部と、上記発光制御線に発光制御信号を供給するために複数のステージを含む発光駆動部と、を備え、上記ステージのそれぞれは、第１ノード及び第２ノードの電圧に応じて第１電源または第２電源の電圧を出力端子に供給するための出力部と、第１入力端子及び第２入力端子に供給される信号に応じて第３ノード及び第４ノードの電圧を制御するための入力部と、上記第２ノードの電圧に応じて上記第１ノードの電圧を制御するための第１信号処理部と、第５ノードに接続され、第３入力端子に供給される信号に応じて上記第１ノードの電圧を制御するための第２信号処理部と、上記第３ノード及び上記第３入力端子に供給される信号に応じて上記第４ノードの電圧を制御するための第３信号処理部と、上記第２信号処理部と上記入力部の間に接続され、上記第３ノード及び第４ノードの電圧の下降幅を制限するための第１安定化部と、を備える。 An organic light emitting display according to an embodiment of the present invention includes a pixel connected to a scan line, a data line, and a light emission control line, a scan driver for supplying a scan signal to the scan line, and a data line. A data driver for supplying a data signal; and a light emission driver including a plurality of stages for supplying a light emission control signal to the light emission control line, wherein each of the stages includes a first node and a second node. An output unit for supplying the voltage of the first power supply or the second power supply to the output terminal according to the voltage of the node, and the third node and the fourth according to the signal supplied to the first input terminal and the second input terminal An input unit for controlling the voltage of the node, a first signal processing unit for controlling the voltage of the first node according to the voltage of the second node, and a third input terminal connected to the fifth node According to the signal supplied to A second signal processing unit for controlling the voltage of the first node, and a third signal for controlling the voltage of the fourth node according to signals supplied to the third node and the third input terminal A processing unit; and a first stabilization unit that is connected between the second signal processing unit and the input unit and limits a voltage drop width of the third node and the fourth node.

また、上記第１電源はゲートオフ電圧に設定され、上記第２電源はゲートオン電圧に設定され、上記出力端子に供給される上記第１電源の電圧が発光制御信号として使用されてもよい。 The first power source may be set to a gate-off voltage, the second power source may be set to a gate-on voltage, and the voltage of the first power source supplied to the output terminal may be used as a light emission control signal.

また、上記第１入力端子は、前段のステージの出力信号またはスタートパルスの供給を受け、ｊ（ｊは奇数または偶数）番目のステージの上記第２入力端子は第１クロック信号、上記第３入力端子は第２クロック信号の供給を受け、ｊ＋１番目のステージの上記第２入力端子は第２クロック信号、上記第３入力端子は第１クロック信号の供給を受けてもよい。 The first input terminal is supplied with the output signal or start pulse of the preceding stage, and the second input terminal of the jth stage (j is an odd number or even number) is the first clock signal and the third input. The terminal may be supplied with a second clock signal, the second input terminal of the (j + 1) th stage may be supplied with a second clock signal, and the third input terminal may be supplied with a first clock signal.

また、上記第１安定化部は、上記第３ノードと上記第５のノードの間に接続され、ゲート電極が上記第２電源に接続される第１トランジスタと、上記第２ノードと上記第４ノードの間に接続され、ゲート電極が上記第２電源に接続される第２トランジスタと、を備えてもよい。 The first stabilizing unit is connected between the third node and the fifth node, a first transistor having a gate electrode connected to the second power source, the second node, and the fourth node. And a second transistor connected between the nodes and having a gate electrode connected to the second power supply.

また、上記第１電源、上記第１ノード、及び上記第３入力端子に接続され、上記出力端子に上記第１電源の電圧が出力される間上記第２ノードの電圧を一定に保持するための第２安定化部をさらに備え、上記第２安定化部は、上記第１電源と第６ノードの間に接続され、ゲート電極が上記第１ノードに接続される第３トランジスタと、上記第６ノードと上記第３入力端子の間に接続され、ゲート電極が上記第２ノードに接続される第４トランジスタと、上記第２ノードと上記第６ノードの間に接続される第１キャパシタと、を備えてもよい。 The second power supply is connected to the first power supply, the first node, and the third input terminal, and holds the voltage of the second node constant while the voltage of the first power supply is output to the output terminal. The second stabilization unit further includes a third transistor connected between the first power source and the sixth node, and having a gate electrode connected to the first node, and the sixth transistor. A fourth transistor connected between the node and the third input terminal and having a gate electrode connected to the second node; and a first capacitor connected between the second node and the sixth node. You may prepare.

本発明の一実施形態に係るステージ及びこれを用いた有機電界発光表示装置によれば、キャパシタを利用してトランジスタのゲート電極の電圧を周期的に下降することにより、トランジスタの駆動特性を向上することができる。 According to the stage and the organic light emitting display using the same according to an embodiment of the present invention, the voltage of the gate electrode of the transistor is periodically decreased using the capacitor, thereby improving the driving characteristics of the transistor. be able to.

また、本発明の一実施形態では、上記キャパシタにより下げられた電圧によって、特定トランジスタのソース電極及びドレイン電極の電圧差が大きくなることを防止することができ、これにより、特定トランジスタの特性が変化することを防止することができる。また、本発明の一実施形態では、発光制御信号が供給される間、特定ノードの電圧を一定に保持することによって駆動の信頼性を確保することができる。 Further, in one embodiment of the present invention, it is possible to prevent the voltage difference between the source electrode and the drain electrode of the specific transistor from increasing due to the voltage lowered by the capacitor, thereby changing the characteristics of the specific transistor. Can be prevented. In one embodiment of the present invention, driving reliability can be ensured by holding the voltage of a specific node constant while the light emission control signal is supplied.

本発明の一実施形態による有機電界発光表示装置を示す図である。1 is a view illustrating an organic light emitting display according to an embodiment of the present invention. 図１に示した画素の一実施形態を示す図である。It is a figure which shows one Embodiment of the pixel shown in FIG. 図１に示した発光駆動部の一実施形態を示す図である。It is a figure which shows one Embodiment of the light emission drive part shown in FIG. 図３に示したステージの一実施形態を示す図である。It is a figure which shows one Embodiment of the stage shown in FIG. 図４に示したステージの駆動方法の一実施形態を示す波形図である。FIG. 5 is a waveform diagram showing an embodiment of a method for driving the stage shown in FIG. 4. 図３に示したステージの他の実施形態を示す図である。It is a figure which shows other embodiment of the stage shown in FIG. 図３に示したステージのさらに他の実施形態を示す図である。It is a figure which shows other embodiment of the stage shown in FIG.

以下では、添付の図面を参照して本発明の実施形態及びその他に当業者が本発明の内容を容易に理解するために必要な事項について詳細に記載する。ただし、本発明は、請求の範囲に記載された範囲内で様々な異なる形態で実現されることができるため、以下に説明する実施形態は、表現有無に関わらず、例示的なものに過ぎない。 Hereinafter, embodiments of the present invention and other matters necessary for those skilled in the art to easily understand the contents of the present invention will be described in detail with reference to the accompanying drawings. However, since the present invention can be realized in various different forms within the scope of the claims, the embodiment described below is merely an example regardless of whether or not it is expressed. .

即ち、本発明は、以下に開示される実施形態に限定されるものではなく、異なる多様な形態で実現されてもよい。以下の説明において、ある部分が他の部分と接続されているというときは、直接接続されている場合だけでなく、その中間に他の素子を挟んで電気的に接続されている場合も含む。また、図面における同じ構成要素に対しては、たとえ他の図面上に示されているとしても、できる限り同じ参照番号及び符号で示していることに留意すべきである。 That is, the present invention is not limited to the embodiments disclosed below, and may be implemented in various different forms. In the following description, a part connected to another part includes not only a direct connection but also a case where the part is electrically connected with another element interposed therebetween. It should also be noted that the same components in the drawings are denoted by the same reference numerals and symbols as much as possible even if they are shown in other drawings.

図１は、本発明の一実施形態による有機電界発光表示装置を示す図である。 FIG. 1 illustrates an organic light emitting display according to an embodiment of the present invention.

図１を参照すると、本発明の一実施形態による有機電界発光表示装置は、走査駆動部１０、データ駆動部２０、発光駆動部３０、画素部４０、及びタイミング制御部６０を備える。 Referring to FIG. 1, the organic light emitting display according to an embodiment of the present invention includes a scan driving unit 10, a data driving unit 20, a light emitting driving unit 30, a pixel unit 40, and a timing control unit 60.

タイミング制御部６０は、外部から供給される同期信号に応じて、データ駆動制御信号ＤＣＳ、走査駆動制御信号ＳＣＳ及び発光駆動制御信号ＥＣＳを生成する。タイミング制御部６０で生成されたデータ駆動制御信号ＤＣＳはデータ駆動部２０に供給され、走査駆動制御信号ＳＣＳは走査駆動部１０に供給され、発光駆動制御信号ＥＣＳは発光駆動部３０に供給される。 The timing controller 60 generates a data drive control signal DCS, a scan drive control signal SCS, and a light emission drive control signal ECS according to a synchronization signal supplied from the outside. The data drive control signal DCS generated by the timing controller 60 is supplied to the data driver 20, the scan drive control signal SCS is supplied to the scan driver 10, and the light emission drive control signal ECS is supplied to the light emission driver 30. .

走査駆動制御信号ＳＣＳにはスタートパルス及びクロック信号が含まれる。スタートパルスは走査信号の最初のタイミングを制御する。クロック信号はスタートパルスをシフトさせるために用いられる。 The scan drive control signal SCS includes a start pulse and a clock signal. The start pulse controls the initial timing of the scanning signal. The clock signal is used to shift the start pulse.

発光駆動制御信号ＥＣＳにはスタートパルス及びクロック信号が含まれる。スタートパルスは発光制御信号の最初のタイミングを制御する。クロック信号はスタートパルスをシフトさせるために用いられる。 The light emission drive control signal ECS includes a start pulse and a clock signal. The start pulse controls the initial timing of the light emission control signal. The clock signal is used to shift the start pulse.

データ駆動制御信号ＤＣＳにはソーススタートパルス及びクロック信号が含まれる。ソーススタートパルスはデータのサンプリングの開始時点を制御する。クロック信号はサンプリング動作を制御するために用いられる。 The data drive control signal DCS includes a source start pulse and a clock signal. The source start pulse controls the start point of data sampling. The clock signal is used to control the sampling operation.

走査駆動部１０は、タイミング制御部６０から走査駆動制御信号ＳＣＳの供給を受ける。走査駆動制御信号ＳＣＳの供給を受けた走査駆動部１０は、走査線Ｓ１〜Ｓｎに走査信号を供給する。例えば、走査駆動部１０は、走査線Ｓ１〜Ｓｎに走査信号を順に供給することができる。走査線Ｓ１〜Ｓｎに走査信号が順に供給されると、画素５０が水平ライン単位で選択される。 The scan driver 10 receives the scan drive control signal SCS from the timing controller 60. The scan driver 10 that has received the scan drive control signal SCS supplies scan signals to the scan lines S1 to Sn. For example, the scan driver 10 can sequentially supply scan signals to the scan lines S1 to Sn. When scanning signals are sequentially supplied to the scanning lines S1 to Sn, the pixels 50 are selected in units of horizontal lines.

発光駆動部３０は、タイミング制御部６０から発光駆動制御信号ＥＣＳの供給を受ける。発光駆動制御信号ＥＣＳの供給を受けた発光駆動部３０は、発光制御線Ｅ１〜Ｅｎに発光制御信号を供給する。例えば、発光駆動部３０は発光制御線Ｅ１〜Ｅｎに発光制御信号を順に供給することができる。このような発光制御信号は画素５０の発光時間を制御するために用いられる。例えば、発光制御信号の供給を受ける特定の画素５０は、発光制御信号が供給される期間は非発光状態に設定され、それ以外の期間は発光状態に設定されてもよい。 The light emission drive unit 30 receives a light emission drive control signal ECS from the timing control unit 60. Receiving the light emission drive control signal ECS, the light emission drive unit 30 supplies the light emission control signal to the light emission control lines E1 to En. For example, the light emission driving unit 30 can sequentially supply light emission control signals to the light emission control lines E1 to En. Such a light emission control signal is used to control the light emission time of the pixel 50. For example, the specific pixel 50 that is supplied with the light emission control signal may be set to a non-light emission state during a period during which the light emission control signal is supplied, and may be set to a light emission state during other periods.

また、発光制御信号は、画素５０に含まれたトランジスタがターンオフできるゲートオフ電圧（例えば、ハイ電圧）に設定され、走査信号は、画素５０に含まれたトランジスタがターンオンできるゲートオン電圧（例えば、ロー電圧）に設定されてもよい。 Further, the light emission control signal is set to a gate-off voltage (for example, a high voltage) at which a transistor included in the pixel 50 can be turned off, and the scanning signal is a gate-on voltage (for example, a low voltage) at which the transistor included in the pixel 50 can be turned on. ) May be set.

データ駆動部２０はタイミング制御部６０からデータ駆動制御信号ＤＣＳの供給を受ける。データ駆動制御信号ＤＣＳの供給を受けたデータ駆動部２０は、データ線Ｄ１〜Ｄｍにデータ信号を供給する。データ線Ｄ１〜Ｄｍに供給されたデータ信号は、走査信号により選択された画素５０に供給される。このため、データ駆動部２０は、走査信号と同期するようにデータ線Ｄ１〜Ｄｍにデータ信号を供給することができる。 The data driver 20 receives a data drive control signal DCS from the timing controller 60. The data driver 20 that has received the data drive control signal DCS supplies data signals to the data lines D1 to Dm. The data signal supplied to the data lines D1 to Dm is supplied to the pixel 50 selected by the scanning signal. Therefore, the data driver 20 can supply a data signal to the data lines D1 to Dm so as to be synchronized with the scanning signal.

画素部４０は、走査線Ｓ１〜Ｓｎ、データ線Ｄ１〜Ｄｍ、及び発光制御線Ｅ１〜Ｅｎと接続される画素５０を備える。画素部４０は、外部から第１駆動電源ＥＬＶＤＤ及び第２駆動電源ＥＬＶＳＳの供給を受ける。 The pixel unit 40 includes pixels 50 connected to the scanning lines S1 to Sn, the data lines D1 to Dm, and the light emission control lines E1 to En. The pixel unit 40 is supplied with the first drive power ELVDD and the second drive power ELVSS from the outside.

図には示さなかったが、画素５０のそれぞれは、駆動トランジスタ及び有機発光ダイオードを備える。駆動トランジスタは、データ信号に応じて、第１駆動電源ＥＬＶＤＤから有機発光ダイオードを経由して第２駆動電源ＥＬＶＳＳに流れる電流量を制御する。 Although not shown in the drawing, each of the pixels 50 includes a driving transistor and an organic light emitting diode. The driving transistor controls the amount of current flowing from the first driving power supply ELVDD to the second driving power supply ELVSS via the organic light emitting diode according to the data signal.

一方、図１には、ｎ個の走査線Ｓ１〜Ｓｎ及びｎ個の発光制御線Ｅ１〜Ｅｎが示されているが、本願の発明はこれに限定されない。例えば、画素５０の回路構造に応じて、画素部４０には１つ以上のダミー走査線及びダミー発光制御線がさらに形成されてもよい。 On the other hand, FIG. 1 shows n scanning lines S1 to Sn and n light emission control lines E1 to En, but the present invention is not limited to this. For example, one or more dummy scanning lines and dummy light emission control lines may be further formed in the pixel unit 40 according to the circuit structure of the pixel 50.

図２は図１に示した画素の一実施形態を示す図である。図２では、説明の便宜上、第ｎ走査線Ｓｎ及び第ｍデータ線Ｄｍと接続された画素を図示する。 FIG. 2 is a diagram showing an embodiment of the pixel shown in FIG. FIG. 2 illustrates pixels connected to the nth scan line Sn and the mth data line Dm for convenience of explanation.

図２を参照すると、本発明の一実施形態による画素５０は、有機発光ダイオードＯＬＥＤ、第１トランジスタ（駆動トランジスタ）Ｔ１、第２トランジスタＴ２、第３トランジスタＴ３、及びストレージキャパシタＣｓｔを備える。 Referring to FIG. 2, a pixel 50 according to an embodiment of the present invention includes an organic light emitting diode OLED, a first transistor (driving transistor) T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

有機発光ダイオードＯＬＥＤのアノード電極は第３トランジスタＴ３の第２電極に接続され、有機発光ダイオードＯＬＥＤのカソード電極は第２駆動電源ＥＬＶＳＳに接続される。このような有機発光ダイオードＯＬＥＤは、第１トランジスタＴ１から供給される電流量に応じて所定輝度の光を生成する。 The anode electrode of the organic light emitting diode OLED is connected to the second electrode of the third transistor T3, and the cathode electrode of the organic light emitting diode OLED is connected to the second drive power source ELVSS. Such an organic light emitting diode OLED generates light having a predetermined luminance according to the amount of current supplied from the first transistor T1.

第１トランジスタＴ１の第１電極は第１駆動電源ＥＬＶＤＤに接続され、第１トランジスタＴ１の第２電極は第３トランジスタＴ３の第１電極に接続される。また、第１トランジスタＴ１のゲート電極は第１０ノードＮ１０に接続される。この第１トランジスタＴ１は、第１０ノードＮ１０の電圧に応じて、第１駆動電源ＥＬＶＤＤから第３トランジスタＴ３及び有機発光ダイオードＯＬＥＤを経由して第２駆動電源ＥＬＶＳＳに供給される電流量を制御する。 The first electrode of the first transistor T1 is connected to the first drive power supply ELVDD, and the second electrode of the first transistor T1 is connected to the first electrode of the third transistor T3. The gate electrode of the first transistor T1 is connected to the tenth node N10. The first transistor T1 controls the amount of current supplied from the first driving power supply ELVDD to the second driving power supply ELVSS via the third transistor T3 and the organic light emitting diode OLED according to the voltage of the tenth node N10. .

第２トランジスタＴ２の第１電極はデータ線Ｄｍに接続され、第２トランジスタＴ２の第２電極は第１０ノードＮ１０に接続される。また、第２トランジスタＴ２のゲート電極は走査線Ｓｎに接続される。この第２トランジスタＴ２は、走査線Ｓｎに走査信号が供給されるときターンオンし、データ線Ｄｍからのデータ信号を第１０ノードＮ１０に供給する。 The first electrode of the second transistor T2 is connected to the data line Dm, and the second electrode of the second transistor T2 is connected to the tenth node N10. The gate electrode of the second transistor T2 is connected to the scanning line Sn. The second transistor T2 is turned on when a scanning signal is supplied to the scanning line Sn, and supplies the data signal from the data line Dm to the tenth node N10.

第３トランジスタＴ３の第１電極は第１トランジスタＴ１の第２電極に接続され、第３トランジスタＴ３の第２電極は有機発光ダイオードＯＬＥＤのアノード電極に接続される。また、第３トランジスタＴ３のゲート電極は発光制御線Ｅｎに接続される。この第３トランジスタＴ３は、発光制御線Ｅｎに発光制御信号が供給されるときにターンオフし、発光制御信号が供給されないときにはターンオンする。 The first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, and the second electrode of the third transistor T3 is connected to the anode electrode of the organic light emitting diode OLED. The gate electrode of the third transistor T3 is connected to the light emission control line En. The third transistor T3 is turned off when the light emission control signal is supplied to the light emission control line En, and is turned on when the light emission control signal is not supplied.

第３トランジスタＴ３がターンオフすると、第１トランジスタＴ１と有機発光ダイオードＯＬＥＤが電気的に遮断されるため、画素５０が非発光状態に設定される。第３トランジスタＴ３がターンオンすると、第１トランジスタＴ１と有機発光ダイオードＯＬＥＤが電気的に接続されるため、画素５０は発光可能な状態に設定される。 When the third transistor T3 is turned off, the first transistor T1 and the organic light emitting diode OLED are electrically disconnected, so that the pixel 50 is set in a non-light emitting state. When the third transistor T3 is turned on, the first transistor T1 and the organic light emitting diode OLED are electrically connected, so that the pixel 50 is set in a state capable of emitting light.

ストレージキャパシタＣｓｔは第１駆動電源ＥＬＶＤＤと第１０ノードＮ１０の間に接続される。このようなストレージキャパシタＣｓｔは第１０ノードＮ１０の電圧を充電する。 The storage capacitor Cst is connected between the first drive power supply ELVDD and the tenth node N10. Such a storage capacitor Cst charges the voltage of the tenth node N10.

一方、本発明の一実施形態における画素５０は図２に限定されない。例えば、本発明における画素５０は、発光制御信号によって発光期間が制御できる様々な形態の回路で実現されてもよい。 On the other hand, the pixel 50 in one embodiment of the present invention is not limited to FIG. For example, the pixel 50 in the present invention may be realized by various types of circuits in which the light emission period can be controlled by the light emission control signal.

図３は図１に示した発光駆動部の一実施形態を示す図である。図３では、説明の便宜上、４個のステージを図示する。 FIG. 3 is a diagram showing an embodiment of the light emission driving unit shown in FIG. In FIG. 3, four stages are shown for convenience of explanation.

図３を参照すると、本発明の一実施形態による発光駆動部３０は複数のステージＳＴ１〜ＳＴ４を備える。ステージＳＴ１〜ＳＴ４は発光制御線Ｅ１〜Ｅ４のいずれか１つと接続され、クロック信号ＣＬＫ１、ＣＬＫ２に応じて駆動される。ここで、ステージＳＴ１〜ＳＴ４は同じ回路で実現されてもよい。 Referring to FIG. 3, the light emission driving unit 30 according to an embodiment of the present invention includes a plurality of stages ST1 to ST4. The stages ST1 to ST4 are connected to any one of the light emission control lines E1 to E4 and are driven according to the clock signals CLK1 and CLK2. Here, the stages ST1 to ST4 may be realized by the same circuit.

ステージＳＴ１〜ＳＴ４のそれぞれは、第１入力端子１０１、第２入力端子１０２、第３入力端子１０３、及び出力端子１０４を備える。 Each of the stages ST1 to ST4 includes a first input terminal 101, a second input terminal 102, a third input terminal 103, and an output terminal 104.

第１入力端子１０１は、前段のステージの出力信号（即ち、発光制御信号）またはスタートパルスＳＳＰの供給を受ける。例えば、最初のステージＳＴ１の第１入力端子１０１はスタートパルスＳＳＰの供給を受け、残りのステージＳＴ２〜ＳＴ４の第１入力端子１０１は前段のステージの出力信号の供給を受けることができる。 The first input terminal 101 is supplied with an output signal (that is, a light emission control signal) or a start pulse SSP from the preceding stage. For example, the first input terminal 101 of the first stage ST1 can be supplied with the start pulse SSP, and the first input terminals 101 of the remaining stages ST2 to ST4 can be supplied with the output signal of the previous stage.

ｊ（ｊは奇数または偶数）番目のステージＳＴｊの第２入力端子１０２は第１クロック信号ＣＬＫ１の供給を受け、第３入力端子１０３は第２クロック信号ＣＬＫ２の供給を受ける。そして、ｊ＋１番目のステージ（ＳＴｊ＋１）の第２入力端子１０２は第２クロック信号ＣＬＫ２の供給を受け、第３入力端子１０３は第１クロック信号ＣＬＫ１の供給を受ける。 The second input terminal 102 of the j-th stage STj (j is an odd or even number) is supplied with the first clock signal CLK1, and the third input terminal 103 is supplied with the second clock signal CLK2. The second input terminal 102 of the (j + 1) th stage (STj + 1) receives supply of the second clock signal CLK2, and the third input terminal 103 receives supply of the first clock signal CLK1.

第１クロック信号ＣＬＫ１及び第２クロック信号ＣＬＫ２は同じ周期を有し、位相が重ならない。例えば、第２クロック信号ＣＬＫ２は第１クロック信号ＣＬＫ１から半周期分だけシフトした信号に設定されてもよい。 The first clock signal CLK1 and the second clock signal CLK2 have the same period and do not overlap in phase. For example, the second clock signal CLK2 may be set to a signal shifted from the first clock signal CLK1 by a half cycle.

さらに、ステージＳＴ１〜ＳＴ４は第１電源ＶＤＤ及び第２電源ＶＳＳの供給を受ける。第１電源ＶＤＤはゲートオフ電圧に設定され、第２電源ＶＳＳはゲートオン電圧に設定されてもよい。この場合、出力端子１０４に供給された第１電源ＶＤＤが発光制御信号に用いられる。 Further, the stages ST1 to ST4 are supplied with the first power supply VDD and the second power supply VSS. The first power supply VDD may be set to a gate-off voltage, and the second power supply VSS may be set to a gate-on voltage. In this case, the first power supply VDD supplied to the output terminal 104 is used for the light emission control signal.

図４は図３に示したステージの一実施形態を示す図である。図４では、説明の便宜上、第１ステージＳＴ１及び第２ステージＳＴ２を図示する。 FIG. 4 is a diagram showing an embodiment of the stage shown in FIG. FIG. 4 shows the first stage ST1 and the second stage ST2 for convenience of explanation.

図４を参照すると、本発明の一実施形態による第１ステージＳＴ１は、入力部２１０、出力部２２０、第１信号処理部２３０、第２信号処理部２４０、第３信号処理部２５０、及び第１安定化部２６０を備える。 Referring to FIG. 4, the first stage ST1 according to an embodiment of the present invention includes an input unit 210, an output unit 220, a first signal processing unit 230, a second signal processing unit 240, a third signal processing unit 250, and a first stage. 1 stabilization part 260 is provided.

出力部２２０は、第１ノードＮ１及び第２ノードＮ２の電圧に応じて、第１電源ＶＤＤまたは第２電源ＶＳＳの電圧を出力端子１０４に供給する。このため、出力部２２０は第１０トランジスタＭ１０及び第１１トランジスタＭ１１を備える。 The output unit 220 supplies the voltage of the first power supply VDD or the second power supply VSS to the output terminal 104 according to the voltages of the first node N1 and the second node N2. Therefore, the output unit 220 includes a tenth transistor M10 and an eleventh transistor M11.

第１０トランジスタＭ１０は第１電源ＶＤＤと出力端子１０４の間に接続される。また、第１０トランジスタＭ１０のゲート電極は第１ノードＮ１に接続される。この第１０トランジスタＭ１０は、第１ノードＮ１の電圧に応じてターンオンまたはターンオフする。ここで、第１０トランジスタＭ１０がターンオンするとき出力端子１０４に供給される第１電源ＶＤＤの電圧は、第１発光制御線Ｅ１の発光制御信号に用いられる。 The tenth transistor M10 is connected between the first power supply VDD and the output terminal 104. The gate electrode of the tenth transistor M10 is connected to the first node N1. The tenth transistor M10 is turned on or turned off according to the voltage of the first node N1. Here, the voltage of the first power supply VDD supplied to the output terminal 104 when the tenth transistor M10 is turned on is used as a light emission control signal of the first light emission control line E1.

第１１トランジスタＭ１１は出力端子１０４と第２電源ＶＳＳの間に接続される。また、第１１トランジスタＭ１１のゲート電極は第２ノードＮ２に接続される。この第１１トランジスタＭ１１は第２ノードＮ２の電圧に応じてターンオンまたはターンオフする。 The eleventh transistor M11 is connected between the output terminal 104 and the second power supply VSS. The gate electrode of the eleventh transistor M11 is connected to the second node N2. The eleventh transistor M11 is turned on or turned off according to the voltage of the second node N2.

入力部２１０は、第１入力端子１０１及び第２入力端子１０２に供給される信号に応じて、第３ノードＮ３及び第４ノードＮ４の電圧を制御する。このため、入力部２１０は第７トランジスタＭ７〜第９トランジスタＭ９を備える。 The input unit 210 controls the voltages at the third node N3 and the fourth node N4 according to signals supplied to the first input terminal 101 and the second input terminal 102. Therefore, the input unit 210 includes a seventh transistor M7 to a ninth transistor M9.

第７トランジスタＭ７は第１入力端子１０１と第４ノードＮ４の間に接続される。また、第７トランジスタＭ７のゲート電極は第２入力端子１０２に接続される。この第７トランジスタＭ７は、第２入力端子１０２に第１クロック信号ＣＬＫ１が供給されるときターンオンし、第１入力端子１０１と第４ノードＮ４を電気的に接続する。 The seventh transistor M7 is connected between the first input terminal 101 and the fourth node N4. The gate electrode of the seventh transistor M7 is connected to the second input terminal 102. The seventh transistor M7 is turned on when the first clock signal CLK1 is supplied to the second input terminal 102, and electrically connects the first input terminal 101 and the fourth node N4.

第８トランジスタＭ８は第３ノードＮ３と第２入力端子１０２の間に接続される。また、第８トランジスタＭ８のゲート電極は第４ノードＮ４に接続される。この第８トランジスタＭ８は第４ノードＮ４の電圧に応じてターンオンまたはターンオフする。 The eighth transistor M8 is connected between the third node N3 and the second input terminal 102. The gate electrode of the eighth transistor M8 is connected to the fourth node N4. The eighth transistor M8 is turned on or turned off according to the voltage of the fourth node N4.

第９トランジスタＭ９は第３ノードＮ３と第２電源ＶＳＳの間に接続される。また、第９トランジスタＭ９のゲート電極は第２入力端子１０２に接続される。この第９トランジスタＭ９は、第２入力端子１０２に第１クロック信号ＣＬＫ１が供給されるときターンオンし、第３ノードＮ３に第２電源ＶＳＳの電圧を供給する。 The ninth transistor M9 is connected between the third node N3 and the second power supply VSS. The gate electrode of the ninth transistor M9 is connected to the second input terminal 102. The ninth transistor M9 is turned on when the first clock signal CLK1 is supplied to the second input terminal 102, and supplies the voltage of the second power source VSS to the third node N3.

第１信号処理部２３０は、第２ノードＮ２の電圧に応じて第１ノードＮ１の電圧を制御する。このため、第１信号処理部２３０は第１２トランジスタＭ１２及び第３キャパシタＣ３を備える。 The first signal processing unit 230 controls the voltage of the first node N1 according to the voltage of the second node N2. Therefore, the first signal processing unit 230 includes a twelfth transistor M12 and a third capacitor C3.

第１２トランジスタＭ１２は第１電源ＶＤＤと第１ノードＮ１の間に接続される。また、第１２トランジスタＭ１２のゲート電極は第２ノードＮ２に接続される。この第１２トランジスタＭ１２は、第２ノードＮ２の電圧に応じてターンオンまたはターンオフする。 The twelfth transistor M12 is connected between the first power supply VDD and the first node N1. The gate electrode of the twelfth transistor M12 is connected to the second node N2. The twelfth transistor M12 is turned on or turned off according to the voltage of the second node N2.

第３キャパシタＣ３は第１電源ＶＤＤと第１ノードＮ１の間に接続される。この第３キャパシタＣ３は第１ノードＮ１に印加される電圧を充電する。また、第３キャパシタＣ３は第１ノードＮ１の電圧を安定的に保持する。 The third capacitor C3 is connected between the first power supply VDD and the first node N1. The third capacitor C3 charges a voltage applied to the first node N1. The third capacitor C3 stably holds the voltage of the first node N1.

第２信号処理部２４０は第５ノードＮ５に接続され、第３入力端子１０３に供給される信号に応じて第１ノードＮ１の電圧を制御する。このため、第２信号処理部２４０は、第５トランジスタＭ５、第６トランジスタＭ６、第１キャパシタＣ１、及び第２キャパシタＣ２を備える。 The second signal processing unit 240 is connected to the fifth node N5 and controls the voltage of the first node N1 according to a signal supplied to the third input terminal 103. Therefore, the second signal processing unit 240 includes a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2.

第１キャパシタＣ１は第２ノードＮ２と第３入力端子１０３の間に接続される。この第１キャパシタＣ１は第２ノードＮ２に印加される電圧を充電する。また、第１キャパシタＣ１は、第３入力端子１０３に供給される第２クロック信号ＣＬＫ２に応じて第２ノードＮ２の電圧を制御する。 The first capacitor C1 is connected between the second node N2 and the third input terminal 103. The first capacitor C1 charges a voltage applied to the second node N2. The first capacitor C1 controls the voltage of the second node N2 according to the second clock signal CLK2 supplied to the third input terminal 103.

第２キャパシタＣ２の第１端子は第５ノードＮ５に接続され、第２端子は第５トランジスタＭ５に接続される。 The first terminal of the second capacitor C2 is connected to the fifth node N5, and the second terminal is connected to the fifth transistor M5.

第５トランジスタＭ５は第２キャパシタＣ２の第２端子と第１ノードＮ１の間に接続される。また、第５トランジスタＭ５のゲート電極は第３入力端子１０３に接続される。この第５トランジスタＭ５は、第３入力端子１０３に第２クロック信号ＣＬＫ２が供給されるときターンオンし、第２キャパシタＣ２の第２端子と第１ノードＮ１を電気的に接続する。 The fifth transistor M5 is connected between the second terminal of the second capacitor C2 and the first node N1. The gate electrode of the fifth transistor M5 is connected to the third input terminal 103. The fifth transistor M5 is turned on when the second clock signal CLK2 is supplied to the third input terminal 103, and electrically connects the second terminal of the second capacitor C2 and the first node N1.

第６トランジスタＭ６は第２キャパシタＣ２の第２端子と第３入力端子１０３の間に接続される。また、第６トランジスタＭ６のゲート電極は第５ノードＮ５に接続される。この第６トランジスタＭ６は、第５ノードＮ５の電圧に応じてターンオンまたはターンオフする。 The sixth transistor M6 is connected between the second terminal of the second capacitor C2 and the third input terminal 103. The gate electrode of the sixth transistor M6 is connected to the fifth node N5. The sixth transistor M6 is turned on or turned off according to the voltage of the fifth node N5.

第３信号処理部２５０は、第３ノードＮ３の電圧及び第３入力端子１０３に供給される信号に応じて第４ノードＮ４の電圧を制御する。このため、第３信号処理部２５０は、第１３トランジスタＭ１３及び第１４トランジスタＭ１４を備える。 The third signal processing unit 250 controls the voltage of the fourth node N4 according to the voltage of the third node N3 and the signal supplied to the third input terminal 103. For this reason, the third signal processing unit 250 includes a thirteenth transistor M13 and a fourteenth transistor M14.

第１３トランジスタＭ１３及び第１４トランジスタＭ１４は、第１電源ＶＤＤと第４ノードＮ４の間に直列接続される。また、第１３トランジスタＭ１３のゲート電極は第３ノードＮ３に接続される。この第１３トランジスタＭ１３は、第３ノードＮ３の電圧に応じてターンオンまたはターンオフする。 The thirteenth transistor M13 and the fourteenth transistor M14 are connected in series between the first power supply VDD and the fourth node N4. The gate electrode of the thirteenth transistor M13 is connected to the third node N3. The thirteenth transistor M13 is turned on or turned off according to the voltage of the third node N3.

また、第１４トランジスタＭ１４のゲート電極は第３入力端子１０３に接続される。この第１４トランジスタＭ１４は、第３入力端子１０３に第２クロック信号ＣＬＫ２が供給されるときターンオンする。 The gate electrode of the fourteenth transistor M14 is connected to the third input terminal 103. The fourteenth transistor M14 is turned on when the second clock signal CLK2 is supplied to the third input terminal 103.

第１安定化部２６０は第２信号処理部２４０と入力部２１０の間に接続される。この第１安定化部２６０は第３ノードＮ３及び第４ノードＮ４の電圧の下降幅を制限する。このため、第１安定化部２６０は、第１トランジスタＭ１及び第２トランジスタＭ２を備える。 The first stabilization unit 260 is connected between the second signal processing unit 240 and the input unit 210. The first stabilizing unit 260 limits the voltage drop width of the third node N3 and the fourth node N4. For this reason, the first stabilization unit 260 includes a first transistor M1 and a second transistor M2.

第１トランジスタＭ１は第３ノードＮ３と第５ノードＮ５の間に接続される。また、第１トランジスタＭ１のゲート電極は第２電源ＶＳＳに接続される。この第１トランジスタＭ１はターンオン状態に設定される。 The first transistor M1 is connected between the third node N3 and the fifth node N5. The gate electrode of the first transistor M1 is connected to the second power supply VSS. The first transistor M1 is set to a turn-on state.

第２トランジスタＭ２は第２ノードＮ２と第４ノードＮ４の間に接続される。また、第２トランジスタＭ２のゲート電極は第２電源ＶＳＳに接続される。この第２トランジスタＭ２はターンオン状態に設定される。 The second transistor M2 is connected between the second node N2 and the fourth node N4. The gate electrode of the second transistor M2 is connected to the second power supply VSS. The second transistor M2 is set in a turn-on state.

一方、第２ステージＳＴ２は、第１入力端子１０１〜第３入力端子１０３に供給される信号を除いた構成が第１ステージＳＴ１と同様である。したがって、第２ステージＳＴ２に関する詳細な説明は省略する。 On the other hand, the configuration of the second stage ST2 is the same as that of the first stage ST1 except for the signals supplied to the first input terminal 101 to the third input terminal 103. Therefore, detailed description regarding the second stage ST2 is omitted.

図５は図４に示したステージの駆動方法の一実施形態を示す波形図である。図５では、説明の便宜上、第１ステージＳＴ１を参照して動作過程を説明する。 FIG. 5 is a waveform diagram showing an embodiment of a method for driving the stage shown in FIG. In FIG. 5, for convenience of explanation, the operation process will be described with reference to the first stage ST1.

図５を参照すると、第１クロック信号ＣＬＫ１及び第２クロック信号ＣＬＫ２は２水平期間２Ｈの周期を有し、異なる水平期間に供給される。即ち、第２クロック信号ＣＬＫ２は、第１クロック信号ＣＬＫ１から半周期（即ち、１水平期間１Ｈ）分だけシフトされた信号に設定される。 Referring to FIG. 5, the first clock signal CLK1 and the second clock signal CLK2 have a period of 2 horizontal periods 2H and are supplied in different horizontal periods. That is, the second clock signal CLK2 is set to a signal shifted from the first clock signal CLK1 by a half cycle (that is, one horizontal period 1H).

スタートパルスＳＳＰが供給されるとき、第１入力端子１０１は第１電源ＶＤＤの電圧に設定され、スタートパルスＳＳＰが供給されないとき、第１入力端子１０１は第２電源ＶＳＳの電圧に設定されてもよい。 When the start pulse SSP is supplied, the first input terminal 101 is set to the voltage of the first power supply VDD, and when the start pulse SSP is not supplied, the first input terminal 101 is set to the voltage of the second power supply VSS. Good.

クロック信号ＣＬＫ１、ＣＬＫ２が供給されるとき、第２入力端子１０２及び第３入力端子１０３は第２電源ＶＳＳの電圧に設定され、クロック信号ＣＬＫ１、ＣＬＫ２が供給されないとき、第２入力端子１０２及び第３入力端子１０３は第１電源ＶＤＤの電圧に設定されてもよい。 When the clock signals CLK1 and CLK2 are supplied, the second input terminal 102 and the third input terminal 103 are set to the voltage of the second power supply VSS. When the clock signals CLK1 and CLK2 are not supplied, the second input terminal 102 and the second input terminal 102 are set. The three input terminals 103 may be set to the voltage of the first power supply VDD.

また、第１入力端子１０１に供給されるスタートパルスＳＳＰは、第２入力端子１０２に供給される第１クロック信号ＣＬＫ１と少なくとも一度重なるように設定される。このため、スタートパルスＳＳＰは第１クロック信号ＣＬＫ１より広い幅、例えば、４水平期間４Ｈの間供給されることができる。この場合、第２ステージＳＴ２の第１入力端子１０１に供給される最初の発光制御信号も、第２ステージＳＴ２の第２入力端子１０２に供給される第２クロック信号ＣＬＫ２と少なくとも一度重なる。 The start pulse SSP supplied to the first input terminal 101 is set so as to overlap at least once with the first clock signal CLK1 supplied to the second input terminal 102. Therefore, the start pulse SSP can be supplied for a wider width than the first clock signal CLK1, for example, for 4 horizontal periods 4H. In this case, the first light emission control signal supplied to the first input terminal 101 of the second stage ST2 also overlaps at least once with the second clock signal CLK2 supplied to the second input terminal 102 of the second stage ST2.

動作過程を説明すると、まず、第１時点ｔ１に第２入力端子１０２に第１クロック信号ＣＬＫ１が供給される。第２入力端子１０２に第１クロック信号ＣＬＫ１が供給されると、第７トランジスタＭ７及び第９トランジスタＭ９がターンオンする。 The operation process will be described. First, the first clock signal CLK1 is supplied to the second input terminal 102 at the first time point t1. When the first clock signal CLK1 is supplied to the second input terminal 102, the seventh transistor M7 and the ninth transistor M9 are turned on.

第７トランジスタＭ７がターンオンすると、第１入力端子１０１と第４ノードＮ４が電気的に接続される。ここで、第２トランジスタＭ２がターンオン状態を保持するために、第１入力端子１０１は第４ノードＮ４を経由して第２ノードＮ２とも電気的に接続される。このとき、第１時点ｔ１の間、第１入力端子１０１にはスタートパルスＳＳＰが供給されず、これにより、第４ノードＮ４及び第２ノードＮ２にロー電圧（例えば、ＶＳＳ）が供給される。 When the seventh transistor M7 is turned on, the first input terminal 101 and the fourth node N4 are electrically connected. Here, in order to maintain the second transistor M2 in a turn-on state, the first input terminal 101 is also electrically connected to the second node N2 via the fourth node N4. At this time, during the first time point t1, the start pulse SSP is not supplied to the first input terminal 101, whereby a low voltage (for example, VSS) is supplied to the fourth node N4 and the second node N2.

第２ノードＮ２及び第４ノードＮ４にロー電圧が供給されると、第８トランジスタＭ８、第１１トランジスタＭ１１、及び第１２トランジスタＭ１２がターンオンする。 When the low voltage is supplied to the second node N2 and the fourth node N4, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned on.

第１２トランジスタＭ１２がターンオンすると、第１ノードＮ１に第１電源ＶＤＤの電圧が供給され、これにより、第１０トランジスタＭ１０がターンオフする。このとき、第３キャパシタＣ３には、第１０トランジスタＭ１０のターンオフに対応する電圧が充電される。 When the twelfth transistor M12 is turned on, the voltage of the first power supply VDD is supplied to the first node N1, whereby the tenth transistor M10 is turned off. At this time, the third capacitor C3 is charged with a voltage corresponding to the turn-off of the tenth transistor M10.

第１１トランジスタＭ１１がターンオンすると、第２電源ＶＳＳの電圧が出力端子１０４に供給される。したがって、第１時点ｔ１の間、第１発光制御線Ｅ１に発光制御信号が供給されない。 When the eleventh transistor M11 is turned on, the voltage of the second power supply VSS is supplied to the output terminal 104. Therefore, the light emission control signal is not supplied to the first light emission control line E1 during the first time point t1.

第８トランジスタＭ８がターンオンすると、第３ノードＮ３に第１クロック信号ＣＬＫ１が供給される。ここで、第１トランジスタＭ１がターンオン状態を保持するため、第１クロック信号ＣＬＫ１は第３ノードＮ３を経由して第５ノードＮ５にも供給される。 When the eighth transistor M8 is turned on, the first clock signal CLK1 is supplied to the third node N3. Here, since the first transistor M1 is kept turned on, the first clock signal CLK1 is also supplied to the fifth node N5 via the third node N3.

一方、第９トランジスタＭ９がターンオンすると、第２電源ＶＳＳの電圧が第３ノードＮ３及び第５ノードＮ５に供給される。ここで、第１クロック信号ＣＬＫ１は第２電源ＶＳＳの電圧に設定され、これにより、第３ノードＮ３及び第５ノードＮ５は安定的に第２電源ＶＳＳの電圧に設定される。 On the other hand, when the ninth transistor M9 is turned on, the voltage of the second power source VSS is supplied to the third node N3 and the fifth node N5. Here, the first clock signal CLK1 is set to the voltage of the second power supply VSS, whereby the third node N3 and the fifth node N5 are stably set to the voltage of the second power supply VSS.

第３ノードＮ３及び第５ノードＮ５が第２電源ＶＳＳの電圧に設定されると、第１３トランジスタＭ１３及び第６トランジスタＭ６がターンオンする。 When the third node N3 and the fifth node N5 are set to the voltage of the second power supply VSS, the thirteenth transistor M13 and the sixth transistor M6 are turned on.

第６トランジスタＭ６がターンオンすると、第３入力端子１０３からのハイ電圧（例えば、ＶＤＤ）が第２キャパシタＣ２の第２端子に供給される。このとき、第５トランジスタＭ５がターンオフ状態に設定されるため、第１ノードＮ１は、第５ノードＮ５及び第２キャパシタＣ２の第２端子電圧とは関係なく第３電源ＶＤＤの電圧を保持する。 When the sixth transistor M6 is turned on, a high voltage (for example, VDD) from the third input terminal 103 is supplied to the second terminal of the second capacitor C2. At this time, since the fifth transistor M5 is set in a turn-off state, the first node N1 holds the voltage of the third power supply VDD regardless of the second terminal voltages of the fifth node N5 and the second capacitor C2.

第１３トランジスタＭ１３がターンオンすると、第１電源ＶＤＤの電圧が第１４トランジスタＭ１４に供給される。このとき、第１４トランジスタＭ１４はターンオフ状態に設定され、これにより、第４ノードＮ４はロー電圧を保持する。 When the thirteenth transistor M13 is turned on, the voltage of the first power supply VDD is supplied to the fourteenth transistor M14. At this time, the fourteenth transistor M14 is set in a turn-off state, and thereby the fourth node N4 holds a low voltage.

第２時点ｔ２では、第２入力端子１０２への第１クロック信号ＣＬＫ１の供給が中断される。第１クロック信号ＣＬＫ１の供給が中断されると、第７トランジスタＭ７及び第９トランジスタＭ９がターンオフする。このとき、第１キャパシタＣ１及び第３キャパシタＣ３により第２ノードＮ２及び第１ノードＮ１は前期間の電圧を保持する。 At the second time point t2, the supply of the first clock signal CLK1 to the second input terminal 102 is interrupted. When the supply of the first clock signal CLK1 is interrupted, the seventh transistor M7 and the ninth transistor M9 are turned off. At this time, the second node N2 and the first node N1 hold the voltage of the previous period by the first capacitor C1 and the third capacitor C3.

第２ノードＮ２がロー電圧を保持する場合、第８トランジスタＭ８、第１１トランジスタＭ１１、及び第１２トランジスタＭ１２がターンオンする。 When the second node N2 holds the low voltage, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned on.

第８トランジスタＭ８がターンオンすると、第２入力端子１０２からのハイ電圧が第３ノードＮ３及び第５ノードＮ５に供給される。そうすると、第１３トランジスタＭ１３及び第６トランジスタＭ６がターンオフ状態に設定される。 When the eighth transistor M8 is turned on, the high voltage from the second input terminal 102 is supplied to the third node N3 and the fifth node N5. Then, the thirteenth transistor M13 and the sixth transistor M6 are set in a turn-off state.

第１２トランジスタＭ１２がターンオンすると、第１ノードＮ１に第１電源ＶＤＤの電圧が供給され、これにより、第１０トランジスタＭ１０はターンオフ状態を保持する。 When the twelfth transistor M12 is turned on, the voltage of the first power supply VDD is supplied to the first node N1, and thus the tenth transistor M10 is kept turned off.

第１１トランジスタＭ１１がターンオンすると、出力端子１０４は第２電源ＶＳＳの電圧の供給を受ける。 When the eleventh transistor M11 is turned on, the output terminal 104 is supplied with the voltage of the second power source VSS.

第３時点ｔ３では、第３入力端子１０３に第２クロック信号ＣＬＫ２が供給される。第３入力端子１０３に第２クロック信号ＣＬＫ２が供給されると、第１４トランジスタＭ１４及び第５トランジスタＭ５がターンオンする。 At the third time point t3, the second clock signal CLK2 is supplied to the third input terminal 103. When the second clock signal CLK2 is supplied to the third input terminal 103, the fourteenth transistor M14 and the fifth transistor M5 are turned on.

第５トランジスタＭ５がターンオンすると、第２キャパシタＣ２の第２端子と第１ノードＮ１が電気的に接続される。このとき、第１ノードＮ１は第１電源ＶＤＤの電圧を保持する。 When the fifth transistor M5 is turned on, the second terminal of the second capacitor C2 and the first node N1 are electrically connected. At this time, the first node N1 holds the voltage of the first power supply VDD.

第１４トランジスタＭ１４がターンオンすると、第１３トランジスタＭ１３の第２電極と第２ノードＮ２が電気的に接続される。このとき、第１３トランジスタＭ１３がターンオフ状態に設定されるため、第１電源ＶＤＤの電圧は第４ノードＮ４及び第２ノードＮ２に供給されない。 When the fourteenth transistor M14 is turned on, the second electrode of the thirteenth transistor M13 and the second node N2 are electrically connected. At this time, since the thirteenth transistor M13 is set in a turn-off state, the voltage of the first power supply VDD is not supplied to the fourth node N4 and the second node N2.

また、第３入力端子１０３に第２クロック信号ＣＬＫ２が供給されると、第１キャパシタＣ１のカップリングにより、第２ノードＮ２は第２電源ＶＳＳより低い電圧に下降する。そうすると、第１１トランジスタＭ１１及び第１２トランジスタＭ１２のゲート電極に印加される電圧が第２電源ＶＳＳより低い電圧に下降するため、トランジスタの駆動特性が向上することができる。 When the second clock signal CLK2 is supplied to the third input terminal 103, the second node N2 drops to a voltage lower than the second power supply VSS due to the coupling of the first capacitor C1. Then, the voltage applied to the gate electrodes of the eleventh transistor M11 and the twelfth transistor M12 drops to a voltage lower than the second power supply VSS, so that the transistor drive characteristics can be improved.

一方、第４ノードＮ４は、第２トランジスタＭ２により、第２ノードＮ２の電圧の下降とは関係なくほぼ第２電源ＶＳＳの電圧を保持する。即ち、第２トランジスタＭ２のゲート電極に第２電源ＶＳＳの電圧が印加されるため、第２ノードＮ２の電圧の下降とは関係なく第４ノードＮ４はほぼ第２電源ＶＳＳの電圧を保持する。この場合、第７トランジスタＭ７の第１電極及び第２電極の電圧差、即ち、ソース電極とドレイン電極の電圧差が最小化し、第７トランジスタＭ７の特性が変化することを防止することができる。 On the other hand, the fourth node N4 substantially holds the voltage of the second power supply VSS by the second transistor M2 regardless of the voltage drop of the second node N2. That is, since the voltage of the second power supply VSS is applied to the gate electrode of the second transistor M2, the fourth node N4 substantially holds the voltage of the second power supply VSS regardless of the decrease in the voltage of the second node N2. In this case, it is possible to minimize the voltage difference between the first electrode and the second electrode of the seventh transistor M7, that is, the voltage difference between the source electrode and the drain electrode, and prevent the characteristics of the seventh transistor M7 from changing.

第４時点ｔ４では、第１入力端子１０１にスタートパルスＳＳＰが供給され、第２入力端子１０２に第１クロック信号ＣＬＫ１が供給される。 At the fourth time point t4, the start pulse SSP is supplied to the first input terminal 101, and the first clock signal CLK1 is supplied to the second input terminal 102.

第２入力端子１０２に第１クロック信号ＣＬＫ１が供給されると、第７トランジスタＭ７及び第９トランジスタＭ９がターンオンする。 When the first clock signal CLK1 is supplied to the second input terminal 102, the seventh transistor M7 and the ninth transistor M9 are turned on.

第７トランジスタＭ７がターンオンすると、第１入力端子１０１と第４ノードＮ４及び第２ノードＮ２が電気的に接続される。そうすると、第２入力端子１０２に供給されたスタートパルスＳＳＰによって、第４ノードＮ４及び第２ノードＮ２がハイ電圧に設定される。第４ノードＮ４及び第２ノードＮ２がハイ電圧に設定されると、第８トランジスタＭ８、第１１トランジスタＭ１１、及び第１２トランジスタＭ１２がターンオフする。 When the seventh transistor M7 is turned on, the first input terminal 101 is electrically connected to the fourth node N4 and the second node N2. Then, the fourth node N4 and the second node N2 are set to a high voltage by the start pulse SSP supplied to the second input terminal 102. When the fourth node N4 and the second node N2 are set to a high voltage, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off.

第９トランジスタＭ９がターンオンすると、第３ノードＮ３及び第５ノードＮ５に第２電源ＶＳＳの電圧が供給される。第３ノードＮ３及び第５ノードＮ５に第２電源ＶＳＳの電圧が供給されると、第１３トランジスタＭ１３及び第６トランジスタＭ６がターンオンする。 When the ninth transistor M9 is turned on, the voltage of the second power supply VSS is supplied to the third node N3 and the fifth node N5. When the voltage of the second power supply VSS is supplied to the third node N3 and the fifth node N5, the thirteenth transistor M13 and the sixth transistor M6 are turned on.

このとき、第１３トランジスタＭ１３がターンオンしても第１４トランジスタＭ１４がターンオフ状態に設定されるため、第４ノードＮ４の電圧は変わらない。 At this time, even if the thirteenth transistor M13 is turned on, the fourteenth transistor M14 is set in a turn-off state, and thus the voltage at the fourth node N4 does not change.

第６トランジスタＭ６がターンオンすると、第２キャパシタＣ２の第２端子と第３入力端子１０３が電気的に接続される。このとき、第５トランジスタＭ５がターンオフ状態に設定されるため、第１ノードＮ１はハイ電圧を保持する。 When the sixth transistor M6 is turned on, the second terminal of the second capacitor C2 and the third input terminal 103 are electrically connected. At this time, since the fifth transistor M5 is set in a turn-off state, the first node N1 holds a high voltage.

第５時点ｔ５では、第３入力端子１０３に第２クロック信号ＣＬＫ２が供給される。第３入力端子１０３に第２クロック信号ＣＬＫ２が供給されると、第１４トランジスタＭ１４及び第５トランジスタＭ５がターンオンする。また、第５時点ｔ５では第３ノードＮ３及び第５ノードＮ５が第２電源ＶＳＳの電圧に設定されるため、第１３トランジスタＭ１３及び第６トランジスタＭ６がターンオン状態を保持する。 At the fifth time point t5, the second clock signal CLK2 is supplied to the third input terminal 103. When the second clock signal CLK2 is supplied to the third input terminal 103, the fourteenth transistor M14 and the fifth transistor M5 are turned on. In addition, at the fifth time point t5, the third node N3 and the fifth node N5 are set to the voltage of the second power source VSS, so that the thirteenth transistor M13 and the sixth transistor M6 hold the turn-on state.

第５トランジスタＭ５及び第６トランジスタＭ６がターンオンすると、第２クロック信号ＣＬＫ２が第１ノードＮ１に供給される。第１ノードＮ１に第２クロック信号ＣＬＫ２が供給されると、第１０トランジスタＭ１０がターンオンする。第１０トランジスタＭ１０がターンオンすると、第１電源ＶＤＤの電圧が出力端子１０４に供給される。出力端子１０４に供給された第１電源ＶＤＤの電圧は、発光制御信号として第１発光制御線Ｅ１に供給される。 When the fifth transistor M5 and the sixth transistor M6 are turned on, the second clock signal CLK2 is supplied to the first node N1. When the second clock signal CLK2 is supplied to the first node N1, the tenth transistor M10 is turned on. When the tenth transistor M10 is turned on, the voltage of the first power supply VDD is supplied to the output terminal 104. The voltage of the first power supply VDD supplied to the output terminal 104 is supplied to the first light emission control line E1 as a light emission control signal.

第１３トランジスタＭ１３及び第１４トランジスタＭ１４がターンオンすると、第４ノードＮ４及び第２ノードＮ２に第２電源ＶＤＤの電圧が供給される。そうすると、第８トランジスタＭ８及び第１１トランジスタＭ１１は安定的にターンオフ状態を保持する。 When the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, the voltage of the second power supply VDD is supplied to the fourth node N4 and the second node N2. Then, the eighth transistor M8 and the eleventh transistor M11 stably maintain the turn-off state.

一方、第２キャパシタＣ２の第２端子に第２クロック信号ＣＬＫ２が供給されると、第２キャパシタＣ２のカップリングにより、第５ノードＮ５の電圧が第２電源ＶＳＳより低い電圧に下降する。そうすると、第６トランジスタＭ６のゲート電極に印加される電圧が第２電源ＶＳＳより低い電圧に下降するため、第６トランジスタＭ６の駆動特性が向上することができる。 On the other hand, when the second clock signal CLK2 is supplied to the second terminal of the second capacitor C2, the voltage of the fifth node N5 falls to a voltage lower than the second power supply VSS due to the coupling of the second capacitor C2. Then, the voltage applied to the gate electrode of the sixth transistor M6 falls to a voltage lower than the second power supply VSS, so that the driving characteristics of the sixth transistor M6 can be improved.

また、第１トランジスタＭ１により、第５ノードＮ５の電圧とは関係なく第３ノードＮ３の電圧はほぼ第２電源ＶＳＳの電圧を保持する。即ち、第１トランジスタＭ１のゲート電極には第２電源ＶＳＳの電圧が印加されるため、第５ノードＮ５の電圧の下降とは関係なく第３ノードＮ３はほぼ第２電源ＶＳＳの電圧を保持する。この場合、第８トランジスタＭ８のソース電極とドレイン電極の電圧差が最小化し、第８トランジスタＭ８の特性が変化することを防止することができる。 In addition, the first transistor M1 maintains the voltage of the second power supply VSS almost at the voltage of the third node N3 regardless of the voltage of the fifth node N5. That is, since the voltage of the second power supply VSS is applied to the gate electrode of the first transistor M1, the third node N3 substantially holds the voltage of the second power supply VSS regardless of the decrease in the voltage of the fifth node N5. . In this case, it is possible to minimize the voltage difference between the source electrode and the drain electrode of the eighth transistor M8 and prevent the characteristics of the eighth transistor M8 from changing.

第６時点ｔ６では、第２入力端子１０２に第１クロック信号ＣＬＫ１が供給される。第２入力端子１０２に第１クロック信号ＣＬＫ１が供給されると、第７トランジスタＭ７及び第９トランジスタＭ９がターンオンする。 At the sixth time point t6, the first clock signal CLK1 is supplied to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the seventh transistor M7 and the ninth transistor M9 are turned on.

第７トランジスタＭ７がターンオンすると、第４ノードＮ４及び第２ノードＮ２が第１入力端子１０１と電気的に接続され、これにより、第１入力端子１０１からのロー電圧が第４ノードＮ４及び第２ノードＮ２に供給される。第４ノードＮ４及び第２ノードＮ２がロー電圧に設定されると、第８トランジスタＭ８、第１１トランジスタＭ１１及び第１２トランジスタＭ１２がターンオンする。 When the seventh transistor M7 is turned on, the fourth node N4 and the second node N2 are electrically connected to the first input terminal 101, whereby the low voltage from the first input terminal 101 is changed to the fourth node N4 and the second node N2. It is supplied to the node N2. When the fourth node N4 and the second node N2 are set to a low voltage, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned on.

第８トランジスタＭ８がターンオンすると、第３ノードＮ３及び第５ノードＮ５に第１クロック信号ＣＬＫ１が供給される。 When the eighth transistor M8 is turned on, the first clock signal CLK1 is supplied to the third node N3 and the fifth node N5.

第１２トランジスタＭ１２がターンオンすると、第１ノードＮ１に第１電源ＶＤＤの電圧が供給され、これにより、第１０トランジスタＭ１０がターンオフする。第１１トランジスタＭ１１がターンオンすると、出力端子１０４に第２電源ＶＳＳの電圧が供給される。出力端子１０４に供給された第２電源ＶＳＳの電圧は第１発光制御線Ｅ１に供給され、これにより、第１発光制御線Ｅ１への発光制御信号の供給が中断される。 When the twelfth transistor M12 is turned on, the voltage of the first power supply VDD is supplied to the first node N1, whereby the tenth transistor M10 is turned off. When the eleventh transistor M11 is turned on, the voltage of the second power supply VSS is supplied to the output terminal 104. The voltage of the second power supply VSS supplied to the output terminal 104 is supplied to the first light emission control line E1, whereby the supply of the light emission control signal to the first light emission control line E1 is interrupted.

一方、第１ステージＳＴ１の出力端子１０４から発光制御信号の供給を受ける第２ステージＳＴ２も、上述した過程を繰り返しながら第２発光制御線Ｅ２に発光制御信号を供給する。即ち、本発明の一実施形態による発光ステージＳＴは、上述した過程を繰り返しながら発光制御線Ｅ１〜Ｅｎに発光制御信号を順に供給することができる。 On the other hand, the second stage ST2, which receives supply of the light emission control signal from the output terminal 104 of the first stage ST1, also supplies the light emission control signal to the second light emission control line E2 while repeating the above-described process. That is, the light emission stage ST according to the embodiment of the present invention can sequentially supply light emission control signals to the light emission control lines E1 to En while repeating the above-described process.

図６は図３に示したステージの他の一実施形態を示す図である。図６を説明するにあたって、図４と同じ構成に対しては同じ図面符号を付し、詳細な説明は省略する。 FIG. 6 is a diagram showing another embodiment of the stage shown in FIG. In describing FIG. 6, the same components as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

図６を参照すると、本発明の他の一実施形態による第１ステージＳＴ１’は、入力部２１０’、出力部２２０、第１信号処理部２３０、第２信号処理部２４０、第３信号処理部２５０、及び第１安定化部２６０を備える。 Referring to FIG. 6, the first stage ST1 ′ according to another embodiment of the present invention includes an input unit 210 ′, an output unit 220, a first signal processing unit 230, a second signal processing unit 240, and a third signal processing unit. 250 and a first stabilizing unit 260.

入力部２１０’は、第１入力端子１０１及び第２入力端子１０２に供給される信号に応じて、第３ノードＮ３及び第４ノードＮ４の電圧を制御する。このため、入力部２１０は第７トランジスタＭ７〜第９トランジスタＭ９を備える。 The input unit 210 ′ controls the voltages at the third node N <b> 3 and the fourth node N <b> 4 according to signals supplied to the first input terminal 101 and the second input terminal 102. Therefore, the input unit 210 includes a seventh transistor M7 to a ninth transistor M9.

第７トランジスタＭ７は第１入力端子１０１と第４ノードＮ４の間に接続される。また、第７トランジスタＭ７のゲート電極は第２入力端子１０２に接続される。この第７トランジスタＭ７は、第２入力端子１０２に第１クロック信号ＣＬＫ１が供給されるときターンオンし、第１入力端子１０１と第４ノードＮ４を電気的に接続する。 The seventh transistor M7 is connected between the first input terminal 101 and the fourth node N4. The gate electrode of the seventh transistor M7 is connected to the second input terminal 102. The seventh transistor M7 is turned on when the first clock signal CLK1 is supplied to the second input terminal 102, and electrically connects the first input terminal 101 and the fourth node N4.

第３ノードＮ３と第２入力端子１０２の間には複数の第８トランジスタＭ８＿１、Ｍ８＿２が直列接続される。第８トランジスタＭ８＿１、Ｍ８＿２のゲート電極は第４ノードＮ４に接続される。この第８トランジスタＭ８＿１、Ｍ８＿２は、第４ノードＮ４の電圧に応じてターンオンまたはターンオフする。 A plurality of eighth transistors M8_1 and M8_2 are connected in series between the third node N3 and the second input terminal. The gate electrodes of the eighth transistors M8_1 and M8_2 are connected to the fourth node N4. The eighth transistors M8_1 and M8_2 are turned on or off according to the voltage of the fourth node N4.

第９トランジスタＭ９は第３ノードＮ３と第２電源ＶＳＳの間に接続される。また、第９トランジスタＭ９のゲート電極は第２入力端子１０２に接続される。この第９トランジスタＭ９は、第２入力端子１０２に第１クロック信号ＣＬＫ１が供給されるときターンオンして第３ノードＮ３に第２電源ＶＳＳの電圧を供給する。 The ninth transistor M9 is connected between the third node N3 and the second power supply VSS. The gate electrode of the ninth transistor M9 is connected to the second input terminal 102. The ninth transistor M9 is turned on when the first clock signal CLK1 is supplied to the second input terminal 102, and supplies the voltage of the second power source VSS to the third node N3.

このような本発明の他の一実施形態では、リーク電流を最小化するために複数の第８トランジスタＭ８＿１、Ｍ８＿２を形成することを除いた構成は図４と同じである。したがって、動作過程に対する詳細な説明は省略する。なお、第２ステージＳＴ２’も入力端子１０１、１０２、１０３に供給される信号を除いた構成が第１ステージＳＴ１’と同一であるため、詳細な説明は省略する。 In another embodiment of the present invention, the configuration is the same as that of FIG. 4 except that a plurality of eighth transistors M8_1 and M8_2 are formed in order to minimize the leakage current. Therefore, a detailed description of the operation process is omitted. Note that the second stage ST2 'has the same configuration as the first stage ST1' except for the signals supplied to the input terminals 101, 102, and 103, and a detailed description thereof will be omitted.

図７は図３に示したステージのさらに他の一実施形態を示す図である。図７では、説明の便宜上、第１ステージＳＴ１”及び第２ステージＳＴ２”を図示する。また、図７において、図４と同じ構成に対しては同じ図面符号を付し、詳細な説明は省略する。 FIG. 7 is a view showing still another embodiment of the stage shown in FIG. FIG. 7 shows the first stage ST1 ″ and the second stage ST2 ″ for convenience of explanation. In FIG. 7, the same components as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

図７を参照すると、本発明のさらに他の一実施形態による第１ステージＳＴ１”は、入力部２１０、出力部２２０、第１信号処理部２３０、第２信号処理部２４０’、第３信号処理部２５０、第１安定化部２６０、及び第２安定化部２７０を備える。 Referring to FIG. 7, a first stage ST1 ″ according to another embodiment of the present invention includes an input unit 210, an output unit 220, a first signal processing unit 230, a second signal processing unit 240 ′, and a third signal processing. Part 250, first stabilization part 260, and second stabilization part 270.

第２安定化部２７０は、第１電源ＶＤＤ、第１ノードＮ１、及び第３入力端子１０３に接続される。この第２安定化部２７０は、出力端子１０４に発光制御信号が供給される間第２ノードＮ２の電圧を一定に保持する。このため、第２安定化部２７０は、第３トランジスタＭ３、第４トランジスタＭ４、及び第１キャパシタＣ１’を備える。 The second stabilization unit 270 is connected to the first power supply VDD, the first node N1, and the third input terminal 103. The second stabilizing unit 270 keeps the voltage of the second node N2 constant while the light emission control signal is supplied to the output terminal 104. Therefore, the second stabilization unit 270 includes a third transistor M3, a fourth transistor M4, and a first capacitor C1 '.

第３トランジスタＭ３は第１電源ＶＤＤと第６ノードＮ６の間に接続され、ゲート電極が第１ノードＮ１に接続される。この第３トランジスタＭ３は、第１ノードＮ１の電圧に応じてターンオンまたはターンオフする。 The third transistor M3 is connected between the first power supply VDD and the sixth node N6, and the gate electrode is connected to the first node N1. The third transistor M3 is turned on or turned off according to the voltage of the first node N1.

第４トランジスタＭ４は第６ノードＮ６と第３入力端子１０３の間に接続され、ゲート電極が第２ノードＮ２に接続される。この第４トランジスタＭ４は第２ノードＮ２の電圧に応じてターンオンまたはターンオフする。 The fourth transistor M4 is connected between the sixth node N6 and the third input terminal 103, and the gate electrode is connected to the second node N2. The fourth transistor M4 is turned on or turned off according to the voltage of the second node N2.

第１キャパシタＣ１’は第６ノードＮ６と第２ノードＮ２の間に接続される。 The first capacitor C1 'is connected between the sixth node N6 and the second node N2.

第２信号処理部２４０’は第５ノードＮ５に接続され、第３入力端子１０３に供給される信号に応じて第１ノードＮ１の電圧を制御する。このため、第２信号処理部２４０’は第５トランジスタＭ５、第６トランジスタＭ６、及び第２キャパシタＣ２を備える。 The second signal processing unit 240 ′ is connected to the fifth node N <b> 5 and controls the voltage of the first node N <b> 1 according to the signal supplied to the third input terminal 103. Therefore, the second signal processing unit 240 'includes a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.

第２キャパシタＣ２の第１端子は第５ノードＮ５に接続され、第２キャパシタＣ２の第２端子は第５トランジスタＭ５に接続される。 The first terminal of the second capacitor C2 is connected to the fifth node N5, and the second terminal of the second capacitor C2 is connected to the fifth transistor M5.

第５トランジスタＭ５は第２キャパシタＣ２の第２端子と第１ノードＮ１の間に接続される。また、第５トランジスタＭ５のゲート電極は第３入力端子１０３に接続される。この第５トランジスタＭ５は、第３入力端子１０３に第２クロック信号ＣＬＫ２が供給されるときターンオンし、第２キャパシタＣ２の第２端子と第１ノードＮ１を電気的に接続する。 The fifth transistor M5 is connected between the second terminal of the second capacitor C2 and the first node N1. The gate electrode of the fifth transistor M5 is connected to the third input terminal 103. The fifth transistor M5 is turned on when the second clock signal CLK2 is supplied to the third input terminal 103, and electrically connects the second terminal of the second capacitor C2 and the first node N1.

第６トランジスタＭ６は第２キャパシタＣ２の第２端子と第３入力端子１０３の間に接続される。また、第６トランジスタＭ６のゲート電極は第５ノードＮ５に接続される。この第６トランジスタＭ６は、第５ノードＮ５の電圧に応じてターンオンまたはターンオフする。 The sixth transistor M6 is connected between the second terminal of the second capacitor C2 and the third input terminal 103. The gate electrode of the sixth transistor M6 is connected to the fifth node N5. The sixth transistor M6 is turned on or turned off according to the voltage of the fifth node N5.

この第２信号処理部２４０’は、図４と比べて第１キャパシタＣ１がないだけであり、その他の構成は同様である。 The second signal processing unit 240 'has only the first capacitor C1 as compared with FIG. 4, and the other configurations are the same.

上述した本発明の他の一実施形態によるステージは図５の駆動波形によって駆動される。したがって、第２安定化部２７０を中心に動作過程を説明する。 The stage according to another embodiment of the present invention described above is driven by the driving waveform of FIG. Therefore, the operation process will be described with a focus on the second stabilizing unit 270.

第４トランジスタＭ４は第２ノードＮ２の電圧に応じてターンオンする。即ち、第４トランジスタＭ４は、第２ノードＮ２がロー電圧に設定される間ターンオン状態を保持する。この場合、第４トランジスタＭ４は、図５の第４時点ｔ４の以前及び第６時点ｔ６の以後にターンオン状態に設定される。 The fourth transistor M4 is turned on according to the voltage of the second node N2. That is, the fourth transistor M4 maintains a turn-on state while the second node N2 is set to a low voltage. In this case, the fourth transistor M4 is set to be turned on before the fourth time point t4 and after the sixth time point t6 in FIG.

第４トランジスタＭ４がターンオン状態に設定される場合、第２クロック信号ＣＬＫ２が供給されると、第１キャパシタＣ１’のカップリングによって第２ノードＮ２の電圧が第２電源ＶＳＳより低い電圧に下降する。（ｔ３時点など） When the fourth transistor M4 is set to the turn-on state, when the second clock signal CLK2 is supplied, the voltage of the second node N2 drops to a voltage lower than the second power supply VSS due to the coupling of the first capacitor C1 ′. . (Such as t3)

一方、第３トランジスタＭ３は第１ノードＮ１の電圧に応じてターンオンする。即ち、第３トランジスタＭ３は、第１ノードＮ１がロー電圧に設定される間ターンオン状態を保持する。この場合、第３トランジスタＭ３は、図５の第５時点ｔ５及び第６時点ｔ６の間ターンオン状態を保持する。 On the other hand, the third transistor M3 is turned on according to the voltage of the first node N1. That is, the third transistor M3 maintains a turn-on state while the first node N1 is set to a low voltage. In this case, the third transistor M3 maintains the turn-on state between the fifth time point t5 and the sixth time point t6 in FIG.

第３トランジスタＭ３がターンオンすると、第６ノードＮ６に第１電源ＶＤＤの電圧が供給される。即ち、発光制御線Ｅ１に発光制御信号が供給される間、第６ノードＮ６は第１電源ＶＤＤの電圧を保持する。この第６ノードＮ６が第１電源ＶＤＤの電圧を保持すると、第２ノードＮ２が安定的にハイ電圧を保持することができる。 When the third transistor M3 is turned on, the voltage of the first power supply VDD is supplied to the sixth node N6. That is, while the light emission control signal is supplied to the light emission control line E1, the sixth node N6 holds the voltage of the first power supply VDD. When the sixth node N6 holds the voltage of the first power supply VDD, the second node N2 can stably hold the high voltage.

より詳細に説明すると、図４のステージの場合、第１キャパシタＣ１は第３入力端子１０３に供給される第２クロック信号ＣＬＫ２の供給を受けるため、第２ノードＮ２の電圧は第２クロック信号ＣＬＫ２によって電圧が変動する。特に、図５の第５時点ｔ５及び第６時点ｔ６の間でも第２クロック信号ＣＬＫ２によって第２ノードＮ２の電圧が揺れ、これにより動作の信頼性が低下する恐れがある。 More specifically, in the case of the stage of FIG. 4, since the first capacitor C1 is supplied with the second clock signal CLK2 supplied to the third input terminal 103, the voltage at the second node N2 is the second clock signal CLK2. The voltage varies depending on. In particular, even between the fifth time point t5 and the sixth time point t6 in FIG. 5, the voltage of the second node N2 may fluctuate due to the second clock signal CLK2, which may reduce the operation reliability.

一方、図６のステージの場合、図５の第５時点ｔ５及び第６時点ｔ６の間、第１キャパシタＣ１’の第１端子は第１電源ＶＤＤの電圧に保持されるため、第２ノードＮ２の電圧を安定的に保持することができる。 On the other hand, in the case of the stage of FIG. 6, the first terminal of the first capacitor C1 ′ is held at the voltage of the first power supply VDD between the fifth time point t5 and the sixth time point t6 of FIG. Can be stably maintained.

本発明の技術思想は上記好ましい実施形態を参照して具体的に述べたが、上記した実施形態はその説明のためのものであり、これに限定するためのものではないことに注意すべきである。また、本発明の技術分野の通常の知識を有する者であれば、本発明の技術思想の範囲内で多様な変形例が可能であることが理解できるだろう。 Although the technical idea of the present invention has been specifically described with reference to the above-described preferred embodiments, it should be noted that the above-described embodiments are for the purpose of explanation and are not intended to limit the present invention. is there. In addition, those skilled in the art of the present invention can understand that various modifications are possible within the scope of the technical idea of the present invention.

上述した発明の権利範囲は添付の特許請求の範囲により定められるものであって、明細書の本文の記載に拘束されず、請求の範囲に記載の発明に属する変形や変更はすべて本発明の範囲に属する。 The scope of the right of the invention described above is defined by the appended claims, and is not restricted by the description of the text of the specification, and all modifications and changes belonging to the claimed invention are within the scope of the present invention. Belonging to.

１０ 走査駆動部
２０ データ駆動部
３０ 発光駆動部
４０ 画素部
５０ 画素
６０ タイミング制御部
２１０ 入力部
２２０ 出力部
２３０、２４０、２５０ 信号処理部
２６０、２７０ 安定化部 DESCRIPTION OF SYMBOLS 10 Scan drive part 20 Data drive part 30 Light emission drive part 40 Pixel part 50 Pixel 60 Timing control part 210 Input part 220 Output part 230,240,250 Signal processing part 260,270 Stabilization part

Claims (20)

第１ノード及び第２ノードの電圧に応じて第１電源または第２電源の電圧を出力端子に供給するための出力部と、
第１入力端子及び第２入力端子に供給される信号に応じて第３ノード及び第４ノードの電圧を制御するための入力部と、
前記第２ノードの電圧に応じて前記第１ノードの電圧を制御するための第１信号処理部と、
第５ノードに接続され、第３入力端子に供給される信号に応じて前記第１ノードの電圧を制御するための第２信号処理部と、
前記第３ノードの電圧及び前記第３入力端子に供給される信号に応じて前記第４ノードの電圧を制御するための第３信号処理部と、
前記第２信号処理部と前記入力部の間に接続され、前記第３ノード及び第４ノードの電圧の下降幅を制限するための第１安定化部と、を備えることを特徴とするステージ。 An output unit for supplying the voltage of the first power source or the second power source to the output terminal according to the voltage of the first node and the second node;
An input unit for controlling voltages of the third node and the fourth node according to signals supplied to the first input terminal and the second input terminal;
A first signal processing unit for controlling the voltage of the first node according to the voltage of the second node;
A second signal processing unit connected to the fifth node for controlling the voltage of the first node according to a signal supplied to the third input terminal;
A third signal processing unit for controlling a voltage of the fourth node according to a voltage of the third node and a signal supplied to the third input terminal;
A stage comprising: a first stabilization unit connected between the second signal processing unit and the input unit for limiting a voltage drop width of the third node and the fourth node. 前記第１電源はゲートオフ電圧に設定され、前記第２電源はゲートオン電圧に設定されることを特徴とする請求項１に記載のステージ。 The stage according to claim 1, wherein the first power source is set to a gate-off voltage, and the second power source is set to a gate-on voltage. 前記第１入力端子は、前段のステージの出力信号またはスタートパルスの供給を受けることを特徴とする請求項１に記載のステージ。 2. The stage according to claim 1, wherein the first input terminal receives supply of an output signal or a start pulse of the preceding stage. 前記第１入力端子に供給される前段のステージの出力信号またはスタートパルスは、前記第２入力端子に供給されるクロック信号と少なくとも一度重なることを特徴とする請求項３に記載のステージ。 4. The stage according to claim 3, wherein the output signal or start pulse of the preceding stage supplied to the first input terminal overlaps at least once with the clock signal supplied to the second input terminal. 前記第２入力端子は第１クロック信号の供給を受け、第３入力端子は第２クロック信号の供給を受けることを特徴とする請求項１に記載のステージ。 The stage according to claim 1, wherein the second input terminal is supplied with a first clock signal, and the third input terminal is supplied with a second clock signal. 前記第１クロック信号及び第２クロック信号は同じ周期を有し、前記第２クロック信号は前記第１クロック信号から半周期分だけシフトされた信号に設定されることを特徴とする請求項５に記載のステージ。 6. The first clock signal and the second clock signal have the same period, and the second clock signal is set to a signal shifted by a half period from the first clock signal. The stage described. 前記第１安定化部は、
前記第３ノードと前記第５ノードの間に接続され、ゲート電極が前記第２電源に接続される第１トランジスタと、
前記第２ノードと前記第４ノードの間に接続され、ゲート電極が前記第２電源に接続される第２トランジスタと、を備えることを特徴とする請求項１に記載のステージ。 The first stabilization unit includes:
A first transistor connected between the third node and the fifth node and having a gate electrode connected to the second power source;
The stage according to claim 1, further comprising: a second transistor connected between the second node and the fourth node and having a gate electrode connected to the second power source. 前記入力部は、
前記第１入力端子と前記第４ノードの間に接続され、ゲート電極が前記第２入力端子に接続される第７トランジスタと、
前記第３ノードと前記第２入力端子の間に接続され、ゲート電極が前記第４ノードに接続される第８トランジスタと、
前記第３ノードと前記第２電源の間に接続され、ゲート電極が前記第２入力端子に接続される第９トランジスタと、を備えることを特徴とする請求項１に記載のステージ。 The input unit is
A seventh transistor connected between the first input terminal and the fourth node and having a gate electrode connected to the second input terminal;
An eighth transistor connected between the third node and the second input terminal and having a gate electrode connected to the fourth node;
The stage according to claim 1, further comprising: a ninth transistor connected between the third node and the second power source and having a gate electrode connected to the second input terminal. 前記出力部は、
前記第１電源と前記出力端子の間に接続され、ゲート電極が前記第１ノードに接続される第１０トランジスタと、
前記第２電源と前記出力端子の間に接続され、ゲート電極が前記第２ノードに接続される第１１トランジスタと、を備えることを特徴とする請求項１に記載のステージ。 The output unit is
A tenth transistor connected between the first power supply and the output terminal and having a gate electrode connected to the first node;
The stage according to claim 1, further comprising: an eleventh transistor connected between the second power source and the output terminal and having a gate electrode connected to the second node. 前記第１信号処理部は、
前記第１電源と前記第１ノードの間に接続され、ゲート電極が前記第２ノードに接続される第１２トランジスタと、
前記第１電源と前記第１ノードの間に接続される第３キャパシタと、を備えることを特徴とする請求項１に記載のステージ。 The first signal processing unit includes:
A twelfth transistor connected between the first power source and the first node and having a gate electrode connected to the second node;
The stage according to claim 1, further comprising: a third capacitor connected between the first power source and the first node. 前記第２信号処理部は、
前記第２ノードと前記第３入力端子の間に接続される第１キャパシタと、
第１端子が前記第５ノードに接続される第２キャパシタと、
前記第２キャパシタの第２端子と前記第１ノードの間に接続され、ゲート電極が前記第３入力端子に接続される第５トランジスタと、
前記第２キャパシタの第２端子と前記第３入力端子の間に接続され、ゲート電極が前記第５ノードに接続される第６トランジスタと、を備えることを特徴とする請求項１に記載のステージ。 The second signal processor is
A first capacitor connected between the second node and the third input terminal;
A second capacitor having a first terminal connected to the fifth node;
A fifth transistor connected between the second terminal of the second capacitor and the first node and having a gate electrode connected to the third input terminal;
The stage according to claim 1, further comprising: a sixth transistor connected between the second terminal of the second capacitor and the third input terminal and having a gate electrode connected to the fifth node. . 前記第３信号処理部は、
第１電源と前記第４ノードの間に直列接続される第１３トランジスタ及び第１４トランジスタを備え、
前記第１３トランジスタのゲート電極は前記第３ノードに接続され、前記第１４トランジスタのゲート電極は前記第３入力端子に接続されることを特徴とする請求項１に記載のステージ。 The third signal processor is
A thirteenth transistor and a fourteenth transistor connected in series between a first power source and the fourth node;
The stage according to claim 1, wherein the gate electrode of the thirteenth transistor is connected to the third node, and the gate electrode of the fourteenth transistor is connected to the third input terminal. 前記第１電源、前記第１ノード、及び前記第３入力端子に接続され、前記出力端子に前記第１電源の電圧が出力される間前記第２ノードの電圧を一定に保持するための第２安定化部をさらに備えることを特徴とする請求項１に記載のステージ。 The second power source is connected to the first power source, the first node, and the third input terminal, and is configured to hold the voltage of the second node constant while the voltage of the first power source is output to the output terminal. The stage according to claim 1, further comprising a stabilization unit. 前記第２安定化部は、
前記第１電源と第６ノードの間に接続され、ゲート電極が前記第１ノードに接続される第３トランジスタと、
前記第６ノードと前記第３入力端子の間に接続され、ゲート電極が前記第２ノードに接続される第４トランジスタと、
前記第２ノードと前記第６ノードの間に接続される第１キャパシタと、を備えることを特徴とする請求項１３に記載のステージ。 The second stabilization unit includes:
A third transistor connected between the first power supply and a sixth node, and having a gate electrode connected to the first node;
A fourth transistor connected between the sixth node and the third input terminal and having a gate electrode connected to the second node;
The stage according to claim 13, further comprising a first capacitor connected between the second node and the sixth node. 前記第２信号処理部は、
第１端子が前記第５ノードに接続される第２キャパシタと、
前記第２キャパシタの第２端子と前記第１ノードの間に接続され、ゲート電極が前記第３入力端子に接続される第５トランジスタと、
前記第２キャパシタの第２端子と前記第３入力端子の間に接続され、ゲート電極が前記第５ノードに接続される第６トランジスタと、を備えることを特徴とする請求項１４に記載のステージ。 The second signal processor is
A second capacitor having a first terminal connected to the fifth node;
A fifth transistor connected between the second terminal of the second capacitor and the first node and having a gate electrode connected to the third input terminal;
The stage according to claim 14, further comprising: a sixth transistor connected between a second terminal of the second capacitor and the third input terminal, and having a gate electrode connected to the fifth node. . 走査線、データ線及び発光制御線と接続される画素と、
前記走査線に走査信号を供給するための走査駆動部と、
前記データ線にデータ信号を供給するためのデータ駆動部と、
前記発光制御線に発光制御信号を供給するために複数のステージを含む発光駆動部と、を備え、
前記ステージのそれぞれは、
第１ノード及び第２ノードの電圧に応じて第１電源または第２電源の電圧を出力端子に供給するための出力部と、
第１入力端子及び第２入力端子に供給される信号に応じて第３ノード及び第４ノードの電圧を制御するための入力部と、
前記第２ノードの電圧に応じて前記第１ノードの電圧を制御するための第１信号処理部と、
第５ノードに接続され、第３入力端子に供給される信号に応じて前記第１ノードの電圧を制御するための第２信号処理部と、
前記第３ノード及び前記第３入力端子に供給される信号に応じて前記第４ノードの電圧を制御するための第３信号処理部と、
前記第２信号処理部と前記入力部の間に接続され、前記第３ノード及び第４ノードの電圧の下降幅を制限するための第１安定化部と、を備えることを特徴とする有機電界発光表示装置。 Pixels connected to scanning lines, data lines, and light emission control lines;
A scan driver for supplying a scan signal to the scan line;
A data driver for supplying a data signal to the data line;
A light emission drive unit including a plurality of stages for supplying a light emission control signal to the light emission control line,
Each of the stages
An output unit for supplying the voltage of the first power source or the second power source to the output terminal according to the voltage of the first node and the second node;
An input unit for controlling voltages of the third node and the fourth node according to signals supplied to the first input terminal and the second input terminal;
A first signal processing unit for controlling the voltage of the first node according to the voltage of the second node;
A second signal processing unit connected to the fifth node for controlling the voltage of the first node according to a signal supplied to the third input terminal;
A third signal processing unit for controlling a voltage of the fourth node according to a signal supplied to the third node and the third input terminal;
An organic electric field, comprising: a first stabilizing unit connected between the second signal processing unit and the input unit and configured to limit a voltage drop of the third node and the fourth node. Luminescent display device. 前記第１電源はゲートオフ電圧に設定され、前記第２電源はゲートオン電圧に設定され、
前記出力端子に供給される前記第１電源の電圧が発光制御信号として使用されることを特徴とする請求項１６に記載の有機電界発光表示装置。 The first power source is set to a gate-off voltage, the second power source is set to a gate-on voltage;
The organic light emitting display as claimed in claim 16, wherein the voltage of the first power source supplied to the output terminal is used as a light emission control signal. 前記第１入力端子は、前段のステージの出力信号またはスタートパルスの供給を受け、
ｊ（ｊは奇数または偶数）番目のステージの前記第２入力端子は第１クロック信号、前記第３入力端子は第２クロック信号の供給を受け、
ｊ＋１番目のステージの前記第２入力端子は第２クロック信号、前記第３入力端子は第１クロック信号の供給を受けることを特徴とする請求項１６に記載の有機電界発光表示装置。 The first input terminal is supplied with the output signal or start pulse of the preceding stage,
The second input terminal of the jth stage (j is an odd number or even number) is supplied with the first clock signal, the third input terminal is supplied with the second clock signal,
The organic light emitting display as claimed in claim 16, wherein the second input terminal of the (j + 1) th stage is supplied with a second clock signal, and the third input terminal is supplied with a first clock signal. 前記第１安定化部は、
前記第３ノードと前記第５ノードの間に接続され、ゲート電極が前記第２電源に接続される第１トランジスタと、
前記第２ノードと前記第４ノードの間に接続され、ゲート電極が前記第２電源に接続される第２トランジスタと、を備えることを特徴とする請求項１６に記載の有機電界発光表示装置。 The first stabilization unit includes:
A first transistor connected between the third node and the fifth node and having a gate electrode connected to the second power source;
The organic light emitting display as claimed in claim 16, further comprising: a second transistor connected between the second node and the fourth node and having a gate electrode connected to the second power source. 前記第１電源、前記第１ノード、及び前記第３入力端子に接続され、前記出力端子に前記第１電源の電圧が出力される間前記第２ノードの電圧を一定に保持するための第２安定化部をさらに備え、
前記第２安定化部は、
前記第１電源と第６ノードの間に接続され、ゲート電極が前記第１ノードに接続される第３トランジスタと、
前記第６ノードと前記第３入力端子の間に接続され、ゲート電極が前記第２ノードに接続される第４トランジスタと、
前記第２ノードと前記第６ノードの間に接続される第１キャパシタと、を備えることを特徴とする請求項１６に記載の有機電界発光表示装置。 The second power source is connected to the first power source, the first node, and the third input terminal, and is configured to hold the voltage of the second node constant while the voltage of the first power source is output to the output terminal. And further comprising a stabilizing part,
The second stabilization unit includes:
A third transistor connected between the first power supply and a sixth node, and having a gate electrode connected to the first node;
A fourth transistor connected between the sixth node and the third input terminal and having a gate electrode connected to the second node;
The organic light emitting display as claimed in claim 16, further comprising a first capacitor connected between the second node and the sixth node.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020523641A (en) * 2018-01-19 2020-08-06 昆山国顕光電有限公司Ｋｕｎｓｈａｎ Ｇｏ−Ｖｉｓｉｏｎｏｘ Ｏｐｔｏ−Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．， Ｌｔｄ． Light emission control drive circuit, light emission control driver, and organic light emitting display device
JP2021515252A (en) * 2018-02-24 2021-06-17 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． Shift register, gate drive circuit and display device
JP2022510042A (en) * 2018-12-06 2022-01-26 京東方科技集團股▲ふん▼有限公司 Shift register, light emission control circuit and display panel

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102511947B1 (en) 2016-06-17 2023-03-21 삼성디스플레이 주식회사 Stage and Organic Light Emitting Display Device Using the same
CN106486065B (en) * 2016-12-29 2019-03-12 上海天马有机发光显示技术有限公司 Shifting deposit unit, register, organic light emitting display panel and driving method
KR102567324B1 (en) * 2017-08-30 2023-08-16 엘지디스플레이 주식회사 Gate driver and display device including the same
US10643533B2 (en) * 2018-01-19 2020-05-05 Kunshan Go-Visionox Opto-Electronics Co., Ltd. Emission control driving circuit, emission control driver and organic light emitting display device
CN108389544B (en) * 2018-03-23 2021-05-04 上海天马有机发光显示技术有限公司 Emission controller, control method thereof and display device
KR102415379B1 (en) * 2018-03-29 2022-07-01 삼성디스플레이 주식회사 Emission driver and organic light emitting display device having the same
KR102527817B1 (en) 2018-04-02 2023-05-04 삼성디스플레이 주식회사 Display device
CN108831385B (en) * 2018-06-25 2020-04-28 上海天马有机发光显示技术有限公司 Scanning driving circuit, display device and driving method
KR20200013923A (en) 2018-07-31 2020-02-10 엘지디스플레이 주식회사 Gate driver and electroluminescence display device using the same
CN109616056A (en) * 2018-08-24 2019-04-12 京东方科技集团股份有限公司 Shift register and its driving method, gate driving circuit and display device
KR102633064B1 (en) * 2018-11-12 2024-02-06 삼성디스플레이 주식회사 Stage and emission control driver having the same
KR20200061469A (en) * 2018-11-23 2020-06-03 삼성디스플레이 주식회사 Stage and Scan Driver Including the same
US11348530B2 (en) 2018-12-10 2022-05-31 Samsung Display Co., Ltd. Scan driver and display device having the same
KR20200072635A (en) * 2018-12-12 2020-06-23 삼성디스플레이 주식회사 Scan driver and display device having the same
TWI681400B (en) * 2019-03-11 2020-01-01 友達光電股份有限公司 Shift register circuit and gate driving circuit
KR20200111322A (en) * 2019-03-18 2020-09-29 삼성디스플레이 주식회사 Stage and emission control driver having the same
KR20200142161A (en) 2019-06-11 2020-12-22 삼성디스플레이 주식회사 Stage and display device including the same
KR20210029336A (en) * 2019-09-05 2021-03-16 삼성디스플레이 주식회사 Emission driver and display device having the same
KR102669165B1 (en) * 2019-11-05 2024-05-28 삼성디스플레이 주식회사 Light emission control driver and display device including the same
CN110956919A (en) * 2019-12-19 2020-04-03 京东方科技集团股份有限公司 Shift register circuit, driving method thereof, gate driving circuit and display panel
KR20210081507A (en) 2019-12-23 2021-07-02 삼성디스플레이 주식회사 Emission driver and display device having the same
KR20210132791A (en) * 2020-04-27 2021-11-05 삼성디스플레이 주식회사 Emission controlling driver and display apparatus including the same
CN114842901A (en) * 2021-02-01 2022-08-02 京东方科技集团股份有限公司 Shift register unit, scanning driving circuit, display substrate and display device
WO2024087130A1 (en) * 2022-10-28 2024-05-02 京东方科技集团股份有限公司 Shift register unit, gate driving circuit, and display apparatus

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010211905A (en) * 2009-02-12 2010-09-24 Semiconductor Energy Lab Co Ltd Drive circuit, display device, and electronic device
JP2014041337A (en) * 2012-08-21 2014-03-06 Samsung Display Co Ltd Light emitting control drive unit and organic light emitting display device including the same
US20150035733A1 (en) * 2013-08-05 2015-02-05 Samsung Display Co., Ltd. Stage circuit and organic light emitting display device using the same
CN105321491A (en) * 2015-11-18 2016-02-10 武汉华星光电技术有限公司 Gate driver on array drive circuit and liquid crystal display using gate driver on array drive circuit

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426349A (en) * 1978-03-20 1995-06-20 Nilssen; Ole K. Electronic ballast with two-transistor switching device
JP3539555B2 (en) * 1999-10-21 2004-07-07 シャープ株式会社 Liquid crystal display
KR100722124B1 (en) * 2005-08-29 2007-05-25 삼성에스디아이 주식회사 scan driving circuit and Organic Light Emitting Display Using the same
US9153341B2 (en) * 2005-10-18 2015-10-06 Semiconductor Energy Laboratory Co., Ltd. Shift register, semiconductor device, display device, and electronic device
WO2007080813A1 (en) * 2006-01-07 2007-07-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and display device and electronic device having the same
US8266663B2 (en) 2006-08-01 2012-09-11 At&T Intellectual Property I, L.P. Interactive content system and method
KR101293559B1 (en) 2007-04-06 2013-08-06 삼성디스플레이 주식회사 Touch sensible display device, and apparatus and driving method thereof
JP2009077475A (en) * 2007-09-19 2009-04-09 Fujitsu Microelectronics Ltd Rectifier circuit
JP4591511B2 (en) * 2008-01-15 2010-12-01 ソニー株式会社 Display device and electronic device
KR100911982B1 (en) * 2008-03-04 2009-08-13 삼성모바일디스플레이주식회사 Emission driver and light emitting display device using the same
JP4957696B2 (en) * 2008-10-02 2012-06-20 ソニー株式会社 Semiconductor integrated circuit, self-luminous display panel module, electronic device, and power line driving method
KR100986862B1 (en) * 2009-01-29 2010-10-08 삼성모바일디스플레이주식회사 Emission Driver and Organic Light Emitting Display Using the same
WO2011092924A1 (en) * 2010-01-29 2011-08-04 シャープ株式会社 Shift register and display device
EP2549465A4 (en) * 2010-03-15 2013-08-21 Sharp Kk Scan signal line drive circuit and display device provided therewith
KR101944465B1 (en) * 2011-01-06 2019-02-07 삼성디스플레이 주식회사 Emission Driver and Organic Light Emitting Display Device Using the same
KR101839953B1 (en) * 2011-01-21 2018-03-20 삼성디스플레이 주식회사 Driver, and display device using the same
TWI493871B (en) 2012-06-05 2015-07-21 Au Optronics Corp Shift register circuitry, display and shift register
KR20130137860A (en) * 2012-06-08 2013-12-18 삼성디스플레이 주식회사 Stage circuit and emission driver using the same
KR101988590B1 (en) * 2012-10-24 2019-06-13 삼성디스플레이 주식회사 Emission Driver
KR20140140271A (en) * 2013-05-29 2014-12-09 삼성디스플레이 주식회사 Pixel and Organic Light Emitting Display Device Using the same
KR102167138B1 (en) * 2014-09-05 2020-10-16 엘지디스플레이 주식회사 Shift register and display device using the sane
WO2016072140A1 (en) * 2014-11-04 2016-05-12 ソニー株式会社 Display device, method for driving display device, and electronic device
US9792871B2 (en) 2015-11-18 2017-10-17 Wuhan China Star Optoelectronics Technology Co., Ltd. Gate driver on array circuit and liquid crystal display adopting the same
CN105304021B (en) * 2015-11-25 2017-09-19 上海天马有机发光显示技术有限公司 Shift-register circuit, gate driving circuit and display panel
CN105469761B (en) 2015-12-22 2017-12-29 武汉华星光电技术有限公司 GOA circuits for narrow frame liquid crystal display panel
KR102458968B1 (en) * 2016-05-18 2022-10-27 삼성디스플레이 주식회사 Display device
KR102582642B1 (en) * 2016-05-19 2023-09-26 삼성디스플레이 주식회사 Display device
KR102463953B1 (en) 2016-05-25 2022-11-08 삼성디스플레이 주식회사 Emission controlling driver and display device having the same
KR102513988B1 (en) * 2016-06-01 2023-03-28 삼성디스플레이 주식회사 Display device
KR102511947B1 (en) * 2016-06-17 2023-03-21 삼성디스플레이 주식회사 Stage and Organic Light Emitting Display Device Using the same
KR20180030314A (en) * 2016-09-12 2018-03-22 삼성디스플레이 주식회사 Display device
CN106935197A (en) * 2017-04-07 2017-07-07 京东方科技集团股份有限公司 Pixel compensation circuit, driving method, organic electroluminescence display panel and display device
KR102519539B1 (en) * 2017-05-15 2023-04-11 삼성디스플레이 주식회사 Stage and Scan Driver Using the same
KR102395869B1 (en) * 2017-07-17 2022-05-10 삼성디스플레이 주식회사 Stage Circuit and Scan Driver Using The Same
KR102633064B1 (en) 2018-11-12 2024-02-06 삼성디스플레이 주식회사 Stage and emission control driver having the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010211905A (en) * 2009-02-12 2010-09-24 Semiconductor Energy Lab Co Ltd Drive circuit, display device, and electronic device
JP2014041337A (en) * 2012-08-21 2014-03-06 Samsung Display Co Ltd Light emitting control drive unit and organic light emitting display device including the same
US20150035733A1 (en) * 2013-08-05 2015-02-05 Samsung Display Co., Ltd. Stage circuit and organic light emitting display device using the same
CN105321491A (en) * 2015-11-18 2016-02-10 武汉华星光电技术有限公司 Gate driver on array drive circuit and liquid crystal display using gate driver on array drive circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020523641A (en) * 2018-01-19 2020-08-06 昆山国顕光電有限公司Ｋｕｎｓｈａｎ Ｇｏ−Ｖｉｓｉｏｎｏｘ Ｏｐｔｏ−Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．， Ｌｔｄ． Light emission control drive circuit, light emission control driver, and organic light emitting display device
JP2021515252A (en) * 2018-02-24 2021-06-17 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． Shift register, gate drive circuit and display device
JP2022510042A (en) * 2018-12-06 2022-01-26 京東方科技集團股▲ふん▼有限公司 Shift register, light emission control circuit and display panel
JP7469042B2 (en) 2018-12-06 2024-04-16 京東方科技集團股▲ふん▼有限公司 SHIFT REGISTER, LIGHT EMITTING CONTROL CIRCUIT AND DISPLAY PANEL

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