JP2017168537A - 半導体装置およびその製造方法 - Google Patents
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- 238000010586 diagram Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
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Abstract
【解決手段】実施形態によれば、まず、接合工程で、基板11上に複数設けられた第1サイズのチップ形成領域10Rの、複数のチップ形成領域10Rに跨る位置に、第1サイズよりも小さい第2サイズの化合物半導体層を接合する。その後、加工工程で、化合物半導体層を加工し、化合物半導体素子をチップ形成領域10Rごとに形成する。そして、分割工程で、基板11を、チップ形成領域10Rごとに分割する。
【選択図】図2
Description
図1は、第1の実施形態による半導体装置の構成の一例を模式的に示す図であり、(a)は上面図であり、(b)は(a)のA−A断面図である。半導体装置としての半導体チップ10は、正方形状の基板11上に、第1構造20と、光機能素子30と、第2構造40と、が配置される構造を有する。
第1の実施形態では、隣接する4つのチップ形成領域が共有する角部に、化合物半導体チップを配置する場合を示した。第2の実施形態では、隣接する2つのチップ形成領域が共有する辺部に、化合物半導体チップを配置する場合を示す。
基板上に複数設けられた第1サイズのチップ形成領域の、複数のチップ形成領域に跨る位置に、前記第1サイズよりも小さい第2サイズの化合物半導体層を接合する接合工程と、
前記化合物半導体層を加工し、化合物半導体素子を前記チップ形成領域ごとに形成する加工工程と、
前記基板を、前記チップ形成領域ごとに分割する分割工程と、
を含むことを特徴とする半導体装置の製造方法。
[付記2]
前記基板が、シリコン基板であることを特徴とする付記1に記載の半導体装置の製造方法。
[付記3]
前記基板上の第1サイズのチップ形成領域に、素子パターンが形成されていることを特徴とする付記1に記載の半導体装置の製造方法。
[付記4]
前記チップ形成領域は矩形状を有し、
前記接合工程では、4つの前記チップ形成領域からなるチップ共有単位を単位として、前記チップ共有単位の中心を含む領域に第1化合物半導体層を接合することを特徴とする付記1に記載の半導体装置の製造方法。
[付記5]
前記接合工程では、前記チップ共有単位の4つの角部に第2化合物半導体層をさらに接合することを特徴とする付記4に記載の半導体装置の製造方法。
[付記6]
前記接合工程では、前記チップ共有単位の対向する一対の辺部の中点を含む領域に第3化合物半導体層をさらに接合することを特徴とする付記5に記載の半導体装置の製造方法。
[付記7]
前記接合工程では、前記チップ共有単位は、異なる前記素子パターンを有する4種類の前記チップ形成領域によって形成されることを特徴とする付記6に記載の半導体装置の製造方法。
[付記8]
前記接合工程では、前記チップ共有単位の対向する他の一対の辺部の中点を含む領域に第4化合物半導体層をさらに接合することを特徴とする付記6に記載の半導体装置の製造方法。
[付記9]
前記接合工程では、
前記チップ共有単位は、異なる前記素子パターンを有する2種類の前記チップ形成領域によって形成され、
前記チップ共有単位が2回回転対称となるように、前記チップ形成領域が配置されることを特徴とする付記8に記載の半導体装置の製造方法。
[付記10]
前記チップ形成領域は矩形状を有し、
前記接合工程では、2つの前記チップ形成領域からなるチップ共有単位を単位として、前記チップ共有単位の中心を含む領域に前記化合物半導体層を配置することを特徴とする付記1に記載の半導体装置の製造方法。
[付記11]
前記接合工程では、
前記チップ共有単位は、1種類の前記チップ形成領域によって形成され、
前記チップ共有単位が2回回転対称となるように、前記チップ形成領域が配置されることを特徴とする付記10に記載の半導体装置の製造方法。
[付記12]
前記接合工程では、前記素子パターンが形成された前記基板と前記化合物半導体層とを接着剤を介して接合することを特徴とする付記1に記載の半導体装置の製造方法。
[付記13]
前記接合工程は、
前記基板上の最表面を平坦化する平坦化工程と、
前記基板上の平坦化された面と前記化合物半導体層の表面とを、水酸基で終端する水酸基終端工程と、
前記基板の平坦化された面に、前記化合物半導体層を仮接合する仮接合工程と、
前記基板と前記化合物半導体層とを加熱して本接合する本接合工程と、
を含むことを特徴とする付記1に記載の半導体装置の製造方法。
[付記14]
前記接合工程では、化合物半導体基板に前記化合物半導体層を形成した化合物半導体チップを前記チップ形成領域に接合することを特徴とする付記1に記載の半導体装置の製造方法。
[付記15]
基板と、
前記基板上に設けられ、素子パターンを含み、所定の機能を有する機能ブロックを含む第1構造と、
前記第1構造上に直接接合される化合物半導体素子と、
を備え、
前記化合物半導体素子の配置位置の外側には、他の機能ブロックが配置されないことを特徴とする半導体装置。
[付記16]
前記基板は、矩形状を有し、
前記化合物半導体素子は、前記基板の中心からの距離が最も遠い位置に配置されることを特徴とする付記15に記載の半導体装置。
[付記17]
前記化合物半導体素子は、複数設けられることを特徴とする付記15に記載の半導体装置。
[付記18]
前記第1構造は、受信光/電気信号変換回路と、電気信号/送信光変換回路と、を前記機能ブロックとして有し、
前記化合物半導体素子は、前記受信光/電気信号変換回路上に接合される受光素子と、前記電気信号/送信光変換回路上に接合される受光素子と、を備えることを特徴とする付記15に記載の半導体装置。
[付記19]
前記基板は、シリコン基板であることを特徴とする付記15に記載の半導体装置。
Claims (7)
- 基板上に複数設けられた第1サイズのチップ形成領域の、複数のチップ形成領域に跨る位置に、前記第1サイズよりも小さい第2サイズの化合物半導体層を接合する接合工程と、
前記化合物半導体層を加工し、化合物半導体素子を前記チップ形成領域ごとに形成する加工工程と、
前記基板を、前記チップ形成領域ごとに分割する分割工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記チップ形成領域は矩形状を有し、
前記接合工程では、4つの前記チップ形成領域からなるチップ共有単位を単位として、前記チップ共有単位の中心を含む領域に第1化合物半導体層を接合することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記接合工程では、
前記チップ共有単位は、1種類の前記チップ形成領域によって形成され、
前記チップ共有単位が4回回転対称となるように、前記チップ形成領域が配置されることを特徴とする請求項2に記載の半導体装置の製造方法。 - 前記接合工程では、前記チップ共有単位の4つの角部に第2化合物半導体層をさらに接合することを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記チップ形成領域は矩形状を有し、
前記接合工程では、2つの前記チップ形成領域からなるチップ共有単位を単位として、前記チップ共有単位の中心を含む領域に前記化合物半導体層を配置することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記接合工程は、
前記基板上の最表面を平坦化する平坦化工程と、
前記基板上の平坦化された面と前記化合物半導体層の表面とを、水酸基で終端する水酸基終端工程と、
前記基板の平坦化された面に、前記化合物半導体層を仮接合する仮接合工程と、
前記基板と前記化合物半導体層とを加熱して本接合する本接合工程と、
を含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 基板と、
前記基板上に設けられ、素子パターンを含み、所定の機能を有する機能ブロックを含む第1構造と、
前記第1構造上に直接接合される化合物半導体素子と、
を備え、
前記化合物半導体素子の配置位置の外側には、他の機能ブロックが配置されないことを特徴とする半導体装置。
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JP2020144294A (ja) * | 2019-03-08 | 2020-09-10 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP7069153B2 (ja) | 2016-11-14 | 2022-05-17 | コミサリア ア レネルジ アトミク エ オウ エネルジ アルタナティヴ | 複数のオプトエレクトロニクスチップの共同製造方法 |
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US11462419B2 (en) | 2018-07-06 | 2022-10-04 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US20230215836A1 (en) * | 2021-12-23 | 2023-07-06 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding on package substrates |
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