JP2017152559A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Abstract
Description
以下、図面を参照しながら本実施の形態の半導体装置について詳細に説明する。
図1は、本実施の形態の半導体装置の構成を示す断面図であり、図2は、本実施の形態の半導体装置の構成を示す模式的な平面図である。図1は、例えば、図2のA−A断面部に対応する。図2の上図は、主として、p−型のエピタキシャル層PEPの主表面の平面レイアウトを示し、図2の下図は、p−型のエピタキシャル層PEPの下部の半導体領域の平面レイアウトを示したものである。
このようなオン耐圧の低下は、以下の現象によるものと考えられる。即ち、比較例1の半導体装置においては、ゲート電極GEに電位が印加されオン状態となり、ドレイン領域DRに高電位(高電圧)が印加された場合、ドレイン領域DR近傍において高インパクトイオン化により発生したホールが、p型半導体領域PISOを通って、ソース領域SRやバックゲート(ゲート電極GEの下方の半導体領域(CH))へ抜けていく。このような長い経路を介したホールの移動により、ソース領域SRとバックゲートとの間に、電位差が生じ易くなる。この電位差が、VF電位(NP接合部の順方向降下電位)以上となると、スナップバック動作が発生し、オン耐圧が小さくなる。特に、ゲート幅やフィンガー数が大きくなった場合には、低いドレイン電位でも、ソース領域SRとバックゲートとの間の電位差が、VF電位以上となり易く、オン耐圧が小さくなる。
図9は、オン耐圧とゲート幅との関係を示すグラフである。(a)は、比較例1の場合、(b)は、本実施の形態の場合を示す。各グラフの縦軸は、オン耐圧(V)を示し、横軸は、ゲート幅/フィンガー数を示す。なお、ゲート−ソース間電位(Vgs)は、4.0Vとした。また、(a)と(b)のグラフスケールは同じである。
次いで、図15〜図26を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図15〜図26は、本実施の形態の半導体装置の製造工程を示す断面図または平面図である。
本実施の形態においては、実施の形態1(図1)の応用例について説明する。特に、p型半導体領域H1PWとp型半導体領域PISOのレイアウト例について説明する。
図27は、本実施の形態の応用例1の半導体装置の構成を示す断面図である。実施の形態1(図1)においては、p型ウエル領域PWLの下方に、p型半導体領域PISOが形成されていない領域を有するが、p型半導体領域PISOをp型ウエル領域PWLの下を通って深い絶縁領域DTIまで延在させてもよい。言い換えれば、深い絶縁領域DTIで囲まれた領域内の全面にp型半導体領域PISOを設けてもよい。p型半導体領域PISO以外の構成は、実施の形態1(図1)の場合と同様であるため、その説明を省略する。
図28は、本実施の形態の応用例2の半導体装置の構成を示す断面図である。実施の形態1(図1)においては、p型ウエル領域PWLの下方に、p型半導体領域H1PWが形成されていない領域を有するが、p型半導体領域H1PWをp型ウエル領域PWLの下を通って深い絶縁領域DTIまで延在させてもよい。別の言い方をすれば、実施の形態1(図1)においては、p型半導体領域H1PWの右端部を、p型ウエル領域PWLの下方に配置したが、p型半導体領域H1PWの右端部を深い絶縁領域DTIに接するように配置してもよい。p型半導体領域H1PW以外の構成は、実施の形態1(図1)の場合と同様であるため、その説明を省略する。このように、p型半導体領域H1PWの右端部が深い絶縁領域DTIに接し、p型半導体領域H1PWの形成領域が図中右側に大きくなる分には特性上の問題は生じない。
図29は、本実施の形態の応用例3の半導体装置の構成を示す断面図である。本応用例は、応用例1のp型半導体領域PISOと応用例2のp型半導体領域H1PWを組み合わせたものである。本応用例においても、p型半導体領域PISOを設けることで、負入力耐圧を確保することができ、また、p型半導体領域H1PWを設けることで、オン耐圧を向上することができる。
図30は、本実施の形態の応用例4の半導体装置の構成を示す断面図である。図30に示す半導体装置は、実施の形態1(図1)に示す各構成部を、ドレイン領域DRに対称に配置したフィンガー領域FRを2つ並べたLDMOSの断面図である。
図31は、本実施の形態の応用例5の半導体装置の構成を示す断面図である。図30に示す半導体装置において、フィンガー領域FRの境界において、分割されているp型半導体領域H1PWを繋げたものである。
実施の形態1、2において説明した半導体装置(LDMOS)の適用箇所に制限はないが、一例として、以下に示す半導体チップに組み込むことができる。
12 プリドライバ回路部
13 アナログ回路部
14 電源回路部
15 ロジック回路部
16 入出力回路部
BC ボディコンタクト領域
C 半導体チップ
DR ドレイン領域
DTI 深い絶縁領域
FR フィンガー領域
GE ゲート電極
GOX ゲート絶縁膜
H1PW p型半導体領域
HNDF n型ドリフト領域
IL1 層間絶縁膜
M1 配線
NBL n型埋め込み領域
OR とのオーバーラップ領域
P1 プラグ
PT1 ポイント
PT2 ポイント
P1BC ボディコンタクトプラグ
P1D ドレインプラグ
P1S ソースプラグ
PEP p−型のエピタキシャル層
PISO p型半導体領域
PR1 フォトレジスト膜
PR2 フォトレジスト膜
PR3 フォトレジスト膜
PR4 フォトレジスト膜
PWL p型ウエル領域
S 支持基板
S1 半導体基板
SR ソース領域
STI 絶縁領域
STId ドレイン絶縁領域
Claims (20)
- 半導体層と、
前記半導体層中に離間して形成された、第1導電型のソース領域およびドレイン領域と、
前記ソース領域およびドレイン領域との間に位置するチャネル形成領域と、
前記チャネル形成領域と前記ドレイン領域との間の前記半導体層中に形成された第1絶縁領域と、
前記チャネル形成領域上にゲート絶縁膜を介して形成され、前記第1絶縁領域上まで延在するゲート電極と、
前記ドレイン領域を囲む前記第1導電型の第1半導体領域と、
前記ソース領域を囲む前記第1導電型と逆導電型である第2導電型の第2半導体領域と、
前記第1半導体領域の下方に配置された前記第2導電型の第3半導体領域と、
前記第3半導体領域と前記第2半導体領域との間に配置された前記第2導電型の第4半導体領域と、
を有し、
平面視において、前記第4半導体領域は、前記第3半導体領域の前記第2半導体領域側の端部と重なるように配置され、かつ、前記第4半導体領域は、前記第2半導体領域の前記第1半導体領域側の端部と重なるように配置されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体領域の前記第2導電型の不純物の濃度は、前記第4半導体領域の前記第2導電型の不純物の濃度より高く、
前記第4半導体領域の前記第2導電型の不純物の濃度は、前記第3半導体領域の前記第2導電型の不純物の濃度より高い、半導体装置。 - 請求項2記載の半導体装置において、
前記ドレイン領域の前記第1導電型の不純物の濃度は、前記第1半導体領域の前記第1導電型の不純物の濃度より高い、半導体装置。 - 請求項1記載の半導体装置において、
前記第3半導体領域の下方に、前記第1導電型の第5半導体領域を有する、半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体領域と接するように配置され、第1絶縁領域の底面より深い位置に底面を有する第2絶縁領域を有する、半導体装置。 - 請求項1記載の半導体装置において、
前記第4半導体領域の第1端部は、前記ドレイン領域から前記第1絶縁領域の幅の1/3の地点から前記第2半導体領域の前記第1絶縁領域側の端の地点の間に位置する、半導体装置。 - 請求項1記載の半導体装置において、
前記第4半導体領域の第2端部は、前記第2半導体領域の前記第1絶縁領域側の端の地点から前記ソース領域の方向に位置する、半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体領域の下方には、前記第3半導体領域が形成されていない領域を有する、半導体装置。 - 請求項1記載の半導体装置において、
前記第1導電型は、n型であり、前記第2導電型は、p型である、半導体装置。 - 請求項5記載の半導体装置は、
平面視において、
矩形の前記ドレイン領域と、
前記ドレイン領域を囲む矩形環状の前記ソース領域と、
を有するセル領域を有する、半導体装置。 - 請求項10記載の半導体装置は、
複数の前記セル領域を有し、
前記複数のセル領域を囲む前記第2絶縁領域を有する、半導体装置。 - (a)第1導電型のドレイン領域の形成予定領域を囲む、前記第1導電型の第1半導体領域を形成する工程、
(b)前記第1導電型のソース領域の形成予定領域を囲む、前記第1導電型と逆導電型である第2導電型の第2半導体領域を形成する工程、
(c)前記ソース領域の形成予定領域および前記ドレイン領域の形成予定領域間の、前記ドレイン領域の形成予定領域側の半導体層中に第1絶縁領域を形成する工程、
(d)前記第1絶縁領域と前記ソース領域の形成予定領域との間の前記半導体層上にゲート絶縁膜を介してゲート電極を形成する工程、
(e)前記ソース領域の形成予定領域および前記ドレイン領域の形成予定領域の前記半導体層中に、前記第1導電型の不純物を導入することにより、前記ソース領域およびドレイン領域を形成する工程、
を有する半導体装置の製造方法であって、
さらに、
(f)前記第1半導体領域または前記第1半導体領域の形成予定領域の下方に、前記第2導電型の第3半導体領域を形成する工程、
(g)前記第3半導体領域または前記第3半導体領域の形成予定領域と、前記第2半導体領域または前記第2半導体領域の形成予定領域と、との間に、前記第2導電型の第4半導体領域を形成する工程、
を有し、
平面視において、前記第4半導体領域は、前記第3半導体領域の前記第2半導体領域側の端部と重なり、かつ、前記第4半導体領域は、前記第2半導体領域の前記第1半導体領域側の端部と重なる、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記(a)、(b)、(f)および(g)工程は、イオン注入工程を有する、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記第2半導体領域の前記第2導電型の不純物の濃度は、前記第4半導体領域の前記第2導電型の不純物の濃度より高く、
前記第4半導体領域の前記第2導電型の不純物の濃度は、前記第3半導体領域の前記第2導電型の不純物の濃度より高い、半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記ドレイン領域の前記第1導電型の不純物の濃度は、前記第1半導体領域の前記第1導電型の不純物の濃度より高い、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
(h)前記第3半導体領域の下方に、前記第1導電型の第5半導体領域を形成する工程、を有する、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
(i)前記第2半導体領域と接するように、前記第1絶縁領域の底面より深い位置に底面を有する第2絶縁領域を形成する工程、を有する、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記第4半導体領域の第1端部は、前記ドレイン領域から前記第1絶縁領域の幅の1/3の地点から前記第2半導体領域の前記第1絶縁領域側の端の地点の間に位置する、半導体装置の製造方法。 - 請求項18記載の半導体装置の製造方法において、
前記第4半導体領域の第2端部は、前記第2半導体領域の前記第1絶縁領域側の端の地点から前記ソース領域の方向に位置する、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記第1導電型は、n型であり、前記第2導電型は、p型である、半導体装置の製造方法。
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- 2017-02-26 EP EP17158016.0A patent/EP3211675B1/en active Active
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US11088031B2 (en) | 2014-11-19 | 2021-08-10 | Key Foundry Co., Ltd. | Semiconductor and method of fabricating the same |
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KR102291315B1 (ko) * | 2019-10-16 | 2021-08-18 | 주식회사 키 파운드리 | 반도체 소자 |
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EP3211675A1 (en) | 2017-08-30 |
US10388741B2 (en) | 2019-08-20 |
JP6591312B2 (ja) | 2019-10-16 |
TW201801318A (zh) | 2018-01-01 |
US20170250259A1 (en) | 2017-08-31 |
CN107123681A (zh) | 2017-09-01 |
CN107123681B (zh) | 2022-03-01 |
EP3211675B1 (en) | 2020-12-16 |
US20190334001A1 (en) | 2019-10-31 |
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