JP2017147316A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2017147316A
JP2017147316A JP2016027673A JP2016027673A JP2017147316A JP 2017147316 A JP2017147316 A JP 2017147316A JP 2016027673 A JP2016027673 A JP 2016027673A JP 2016027673 A JP2016027673 A JP 2016027673A JP 2017147316 A JP2017147316 A JP 2017147316A
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semiconductor element
heat radiating
radiating plate
heat
heat radiation
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裕孝 大野
Hirotaka Ono
裕孝 大野
智弘 宮崎
Toshihiro Miyazaki
智弘 宮崎
憲司 小野田
Kenji Onoda
憲司 小野田
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Denso Corp
Toyota Motor Corp
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Denso Corp
Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress generation of air bubbles in a resin of a semiconductor device.SOLUTION: A semiconductor device comprises: a semiconductor element; a pair of heat radiation plates that include a first heat radiation plate on whose one surface the semiconductor element is bonded, and a second heat radiation plate opposed to the first heat radiation plate while interposing the semiconductor element; a spacer block bonded with the semiconductor element and the second heat radiation plate; and a resin filled between the pair of heat radiation plates. The one surface has: a peripheral groove that extends along an outer edge of the semiconductor element, and that becomes deeper as it approaches the semiconductor element in a cross section vertical to the extending direction; an injection groove that extends from a first position of the peripheral groove to the circumference of the first heat radiation plate; and a discharge groove that extends from a second position of the peripheral groove to the circumference of the first heat radiation plate. The first position and the second position of the peripheral groove are located at opposite sides to each other while interposing the semiconductor element.SELECTED DRAWING: Figure 2

Description

本明細書で開示する技術は、半導体装置に関する。   The technology disclosed in this specification relates to a semiconductor device.

特許文献１に、半導体装置が開示されている。この半導体装置は、半導体素子と、一対の放熱板と、ブロック体（即ちスペーサブロック）と、樹脂と、を備える。一対の放熱板は、半導体素子が一方の面に載置されている第１の放熱板と、半導体素子を挟んで第１の放熱板に対向する第２の放熱板と、を有する。樹脂は、半導体素子を封止しており、一対の放熱板の間に充填されている。   Patent Document 1 discloses a semiconductor device. This semiconductor device includes a semiconductor element, a pair of heat sinks, a block body (that is, a spacer block), and a resin. The pair of heat sinks includes a first heat sink on which the semiconductor element is placed on one surface, and a second heat sink opposite to the first heat sink with the semiconductor element interposed therebetween. The resin seals the semiconductor element and is filled between a pair of heat sinks.

特開２０１０−０６２４９０号公報JP 2010-062490 A

上記の半導体装置の製造では、半導体素子を樹脂によって封止するために、通常、トランスファー成形（又は射出成形でもよい。以下においても同様）が実施される。このトランスファー成形では、一対の放熱板の間に半導体素子及びスペーサブロックがはんだ付けされた半製品を金型内に配置し、金型に設けられた注入口から金型内へ加熱された樹脂を注入する。金型内に注入された樹脂は、金型内の空間を充填するように広がり、一対の放熱板の間にも流れ込む。一対の放熱板の間に流れ込んだ樹脂は、半導体素子及びスペーサブロック（以下、半導体素子等）を避けるように、半導体素子等の一方側と他方側とに分岐して流れる。そして、一方側を通って流れた樹脂と、他方側を通って流れた樹脂は、半導体素子等を越えた位置で再び合流する。さらに樹脂の注入が続けられることによって、樹脂が一対の放熱板の間に充填される。   In the manufacture of the semiconductor device described above, transfer molding (or injection molding may be used. The same applies to the following) is usually performed in order to seal the semiconductor element with resin. In this transfer molding, a semi-finished product in which a semiconductor element and a spacer block are soldered between a pair of heat sinks is placed in a mold, and heated resin is injected into the mold from an inlet provided in the mold. . The resin injected into the mold spreads so as to fill the space in the mold and flows between the pair of heat sinks. The resin flowing between the pair of heat radiating plates branches and flows into one side and the other side of the semiconductor element or the like so as to avoid the semiconductor element and the spacer block (hereinafter, semiconductor element or the like). Then, the resin flowing through one side and the resin flowing through the other side merge again at a position beyond the semiconductor element or the like. Further, the resin is filled between the pair of heat sinks by continuing to inject the resin.

一対の放熱板の間を樹脂が流れるときに、半導体素子等から近い範囲（以下、内側範囲という）では、一対の放熱板による抵抗の影響が大きいので、樹脂が比較的にゆっくり流れる。一方、半導体素子等から遠い範囲（以下、外側範囲という）では、一対の放熱板による抵抗の影響が小さいので、樹脂が比較的に速く流れる。そのため、樹脂が半導体素子等の両側へ分岐して流れたときに、外側範囲を流れる樹脂が先に合流し、その後に内側範囲を流れる樹脂が合流することが起こり得る。この場合、樹脂によって空気が巻き込まれることにより、内側範囲に気泡（ボイド）が発生する。このような気泡は、その後に樹脂の注入が続けられても、樹脂内に残存するおそれがある。本明細書では、半導体装置の樹脂内に気泡が発生することを抑制し得る技術を提供する。   When the resin flows between the pair of heat sinks, the resin flows relatively slowly in a range close to the semiconductor element or the like (hereinafter referred to as an inner range) because the resistance of the pair of heat sinks is large. On the other hand, in a range far from the semiconductor element or the like (hereinafter referred to as the outer range), the resin flows relatively quickly because the influence of the resistance by the pair of heat sinks is small. Therefore, when the resin branches and flows to both sides of the semiconductor element or the like, it is possible that the resin flowing in the outer range first merges and then the resin flowing in the inner range merges. In this case, air is entrained by the resin, and bubbles are generated in the inner range. Such bubbles may remain in the resin even if resin injection is continued thereafter. The present specification provides a technique capable of suppressing the generation of bubbles in the resin of a semiconductor device.

本明細書で開示される半導体装置は、半導体素子と、半導体素子が一方の面に接合された第１の放熱板と、半導体素子を挟んで第１の放熱板に対向する第２の放熱板と、を有する一対の放熱板と、半導体素子及び第２の放熱板の間に位置しているとともに、半導体素子及び第２の放熱板のそれぞれと接合されたスペーサブロックと、一対の放熱板の間に充填されている樹脂と、を備える。第１の放熱板の一方の面は、半導体素子の外縁に沿って延伸するとともに、その延伸方向に垂直な断面では、半導体素子に近づくにつれて深くなる周辺溝と、周辺溝の第１位置から第１の放熱板の周縁まで伸びる注入溝と、周辺溝の第２位置から第１の放熱板の周縁まで伸びる排出溝と、を有する。周辺溝の第１位置と第２位置は、半導体素子を挟んで互いに反対側に位置する。   A semiconductor device disclosed in this specification includes a semiconductor element, a first heat radiating plate in which the semiconductor element is bonded to one surface, and a second heat radiating plate facing the first heat radiating plate with the semiconductor element interposed therebetween. And a space between the semiconductor element and the second heat radiating plate, a spacer block joined to each of the semiconductor element and the second heat radiating plate, and a space between the pair of heat radiating plates. A resin. One surface of the first heat radiating plate extends along the outer edge of the semiconductor element, and in a cross section perpendicular to the extending direction, a peripheral groove that becomes deeper as the semiconductor element is approached, and a first position of the peripheral groove from the first position. An injection groove extending to the periphery of one heat sink, and a discharge groove extending from the second position of the peripheral groove to the periphery of the first heat sink. The first position and the second position of the peripheral groove are located on opposite sides of the semiconductor element.

上記の半導体装置では、半導体素子が接合された第１放熱板の表面に、周辺溝が設けられている。周辺溝は、半導体素子の外縁に沿って延伸しており、その延伸方向に垂直な断面では、半導体素子に近づくにつれて深くなっている。これにより、一対の放熱板の間の内側範囲では、樹脂が流れることができるスペースが大きくなり、樹脂が受ける抵抗が緩和される。即ち、内側範囲において樹脂が流れやすくなる。また、半導体素子が接合された第１放熱板の表面には、注入溝と排出溝がさらに設けられている。注入溝と排出溝は、半導体素子を挟んで互いに反対側の位置において、それぞれ周辺溝から第１放熱板の周縁まで伸びている。これにより、内側範囲へ向かう樹脂の流れ、及び、内側範囲から排出される樹脂の流れが促進される。このような構成により、外側範囲を流れる樹脂が合流する前に、内側範囲を流れる樹脂が合流しやすくなっている。その結果、半導体装置の樹脂内に気泡が発生することを抑制し得る。   In the above semiconductor device, a peripheral groove is provided on the surface of the first heat radiating plate to which the semiconductor element is bonded. The peripheral groove extends along the outer edge of the semiconductor element, and the cross section perpendicular to the extending direction becomes deeper as the semiconductor element is approached. Thereby, in the inner range between a pair of heat sinks, the space in which the resin can flow increases, and the resistance received by the resin is reduced. That is, the resin easily flows in the inner range. In addition, an injection groove and a discharge groove are further provided on the surface of the first heat radiation plate to which the semiconductor element is bonded. The injection groove and the discharge groove respectively extend from the peripheral groove to the periphery of the first heat radiating plate at positions opposite to each other across the semiconductor element. Thereby, the flow of resin toward the inner range and the flow of resin discharged from the inner range are promoted. With such a configuration, the resin flowing in the inner area is easily merged before the resin flowing in the outer area is merged. As a result, generation of bubbles in the resin of the semiconductor device can be suppressed.

第１実施例の半導体装置１０の正面図。The front view of the semiconductor device 10 of 1st Example. 図１中のＩＩ−ＩＩ線における断面図。Sectional drawing in the II-II line | wire in FIG. 図１中のＩＩＩ−ＩＩＩ線における断面図。Sectional drawing in the III-III line in FIG. 第１実施例の半導体装置１０の回路構成を示す回路図。1 is a circuit diagram showing a circuit configuration of a semiconductor device according to a first embodiment. 第１実施例の第１放熱板３６、３８が金型７０内に配置された様子を示す図。The figure which shows a mode that the 1st heat sinks 36 and 38 of 1st Example are arrange | positioned in the metal mold | die 70. FIG. 比較例の半導体装置の製造工程においてトランスファー成形が実施される様子を示す図。The figure which shows a mode that transfer molding is implemented in the manufacturing process of the semiconductor device of a comparative example. 図６の続きの図。FIG. 7 is a continuation of FIG. 6. 第１実施例の半導体装置１０の製造工程においてトランスファー成形が実施される様子を示す図。The figure which shows a mode that transfer molding is implemented in the manufacturing process of the semiconductor device 10 of 1st Example. 図８の続きの図。FIG. 9 is a continuation of FIG. 8. 第２実施例の第２放熱板３２の斜視図。The perspective view of the 2nd heat sink 32 of 2nd Example. 図１０中のＸＩ線における断面図。Sectional drawing in the XI line in FIG. 図１０中のＸＩＩ線における断面図。Sectional drawing in the XII line | wire in FIG. 第３実施例の第１放熱板３６を示す図。The figure which shows the 1st heat sink 36 of 3rd Example.

（第１実施例）
図面を参照して、第１実施例の半導体装置１０について説明する。本実施例の半導体装置１０は、一例ではあるが、電力の変換や制御を行うための電力変換装置に用いられ、特に、インバータ回路の一つの上下アームを構成する。図１〜図４に示すように、半導体装置１０は、第１半導体素子１２と、第２半導体素子１４と、第１半導体素子１２及び第２半導体素子１４を封止する封止体２０を備える。第１半導体素子１２と第２半導体素子１４は、許容電流が１００アンペア以上であり、パワー半導体素子に属するものである。図４に示すように、第１半導体素子１２と第２半導体素子１４は、電気的に直列に接続されている。一例ではあるが、第１半導体素子１２と第２半導体素子１４のそれぞれは、単一の半導体基板にトランジスタ素子とダイオード素子が形成された半導体素子であり、互いに等しい構造及び特性を有する。なお、第１半導体素子１２及び第２半導体素子１４の構成は特に限定されない。第１半導体素子１２及び第２半導体素子１４は、ＩＧＢＴ又はＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）といったトランジスタ素子であってよく、また、必ずしもダイオード素子を内蔵する必要はない。 (First embodiment)
A semiconductor device 10 according to a first embodiment will be described with reference to the drawings. Although the semiconductor device 10 of this embodiment is an example, it is used in a power conversion device for performing power conversion and control, and particularly constitutes one upper and lower arm of an inverter circuit. As shown in FIGS. 1 to 4, the semiconductor device 10 includes a first semiconductor element 12, a second semiconductor element 14, and a sealing body 20 that seals the first semiconductor element 12 and the second semiconductor element 14. . The first semiconductor element 12 and the second semiconductor element 14 have an allowable current of 100 amperes or more and belong to the power semiconductor element. As shown in FIG. 4, the first semiconductor element 12 and the second semiconductor element 14 are electrically connected in series. As an example, each of the first semiconductor element 12 and the second semiconductor element 14 is a semiconductor element in which a transistor element and a diode element are formed on a single semiconductor substrate, and has the same structure and characteristics. The configurations of the first semiconductor element 12 and the second semiconductor element 14 are not particularly limited. The first semiconductor element 12 and the second semiconductor element 14 may be transistor elements such as IGBTs or MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and do not necessarily include a diode element.

封止体２０は、樹脂材料で構成されている。なお、封止体２０を構成する樹脂材料は特に限定されず、パワー半導体素子向けの各種の封止材が採用可能である。封止体２０は、概して板状の形状を有しており、正面２１、背面２２、上面２３、下面２４、右側面２５及び左側面２６を有する。正面２１は、図面においてＸ軸正方向側の面である。背面２２は、図面においてＸ軸負方向側の面であり、正面２１の反対側に位置する。上面２３は、図面においてＺ軸正方向側の面であり、正面２１及び背面２２と隣り合う。下面２４は、図面においてＺ軸負方向側の面であり、上面２３の反対側に位置する。下面２４は、正面２１及び背面２２と隣り合う。右側面２５は、図面においてＹ軸負方向側の面であり、正面２１、背面２２、上面２３及び下面２４と隣り合う。左側面２６は、図面においてＹ軸正方向側の面であり、右側面２５の反対側に位置する。左側面２６は、正面２１、背面２２、上面２３及び下面２４と隣り合う。   The sealing body 20 is made of a resin material. In addition, the resin material which comprises the sealing body 20 is not specifically limited, The various sealing materials for power semiconductor elements are employable. The sealing body 20 has a generally plate shape and includes a front surface 21, a back surface 22, an upper surface 23, a lower surface 24, a right side surface 25 and a left side surface 26. The front surface 21 is a surface on the X axis positive direction side in the drawing. The back surface 22 is a surface on the X axis negative direction side in the drawing, and is located on the opposite side of the front surface 21. The upper surface 23 is a surface on the Z axis positive direction side in the drawing, and is adjacent to the front surface 21 and the back surface 22. The lower surface 24 is a surface on the Z axis negative direction side in the drawing, and is located on the opposite side of the upper surface 23. The lower surface 24 is adjacent to the front surface 21 and the back surface 22. The right side surface 25 is a surface on the Y axis negative direction side in the drawing, and is adjacent to the front surface 21, the back surface 22, the upper surface 23, and the lower surface 24. The left side surface 26 is a surface on the Y axis positive direction side in the drawing, and is located on the opposite side of the right side surface 25. The left side surface 26 is adjacent to the front surface 21, the back surface 22, the upper surface 23, and the lower surface 24.

封止体２０の正面２１及び背面２２は、互いに平行な平面であり、それらの法線はＸ軸に平行である。半導体装置１０が二つの冷却器の間に配置されたときに、封止体２０の正面２１及び背面２２は、それぞれ隣接する冷却器にグリスを介して対向する。   The front surface 21 and the back surface 22 of the sealing body 20 are planes parallel to each other, and their normal lines are parallel to the X axis. When the semiconductor device 10 is disposed between the two coolers, the front surface 21 and the back surface 22 of the sealing body 20 face the adjacent coolers via grease.

図１〜図４に示すように、半導体装置１０はさらに、二つの第１放熱板３６、３８と、二つの第２放熱板３２、３４とを備える。二つの第１放熱板３６、３８は、封止体２０の背面２２に露出している。第１放熱板３６、３８の構造の詳細については後述する。二つの第２放熱板３２、３４は、封止体２０の正面２１に露出している。換言すると、封止体２０は、放熱板３２、３６の間、及び放熱板３４、３８の間に充填されている。それぞれの放熱板３２、３４、３６、３８は、封止体２０を構成する材料よりも熱伝導率の高い材料で構成されており、半導体装置１０内で発生した熱（特に半導体素子１２、１４の発熱）を、半導体装置１０の外部へ放出する。一例ではあるが、本実施例における放熱板３２、３４、３６、３８は、金属材料（詳しくは銅）で構成されている。放熱板３２、３４、３６、３８を構成する材料は特に限定されない。放熱板３２、３４、３６、３８の一部又は全部を、セラミック材料その他の熱伝達率に優れた材料で構成することができる。また、封止体２０の正面２１又は背面２２に露出する放熱板の位置、大きさ、数も特に限定されない。   As shown in FIGS. 1 to 4, the semiconductor device 10 further includes two first heat radiating plates 36 and 38 and two second heat radiating plates 32 and 34. The two first heat radiation plates 36 and 38 are exposed on the back surface 22 of the sealing body 20. Details of the structure of the first heat radiation plates 36 and 38 will be described later. The two second heat radiation plates 32 and 34 are exposed on the front surface 21 of the sealing body 20. In other words, the sealing body 20 is filled between the heat sinks 32 and 36 and between the heat sinks 34 and 38. Each of the heat radiating plates 32, 34, 36, and 38 is made of a material having a higher thermal conductivity than the material that forms the sealing body 20, and generates heat generated in the semiconductor device 10 (particularly, the semiconductor elements 12, 14). ) Is released to the outside of the semiconductor device 10. Although it is an example, the heat sinks 32, 34, 36, and 38 in the present embodiment are made of a metal material (specifically, copper). The material which comprises the heat sinks 32, 34, 36, and 38 is not specifically limited. Part or all of the radiator plates 32, 34, 36, and 38 can be made of a ceramic material or other material having excellent heat transfer coefficient. Further, the position, size, and number of the heat radiating plates exposed on the front surface 21 or the back surface 22 of the sealing body 20 are not particularly limited.

図２を参照して、封止体２０の内部の構成について説明する。なお、下記する説明は一例であり、半導体装置１０の構成を限定するものではない。図２に示すように、一方の第１放熱板３６は、はんだ層５３を介して第１半導体素子１２の下面電極１２ｂに接合されている。また、一方の第２放熱板３２は、第１スペーサブロック４２及びはんだ層５１、５２を介して、第１半導体素子１２の上面電極１２ａに接合されている。即ち、第１放熱板３６と第２放熱板３２は、第１半導体素子１２を挟んで対向する一対の放熱板を構成している。   With reference to FIG. 2, the internal structure of the sealing body 20 is demonstrated. Note that the following description is an example and does not limit the configuration of the semiconductor device 10. As shown in FIG. 2, one first heat radiating plate 36 is joined to the lower surface electrode 12 b of the first semiconductor element 12 through a solder layer 53. One of the second heat radiating plates 32 is joined to the upper surface electrode 12 a of the first semiconductor element 12 via the first spacer block 42 and the solder layers 51 and 52. That is, the first heat radiating plate 36 and the second heat radiating plate 32 constitute a pair of heat radiating plates facing each other with the first semiconductor element 12 interposed therebetween.

第１スペーサブロック４２は、第１半導体素子１２及び第２放熱板３２の間に位置している。第１スペーサブロック４２は、はんだ層５２を介して第１半導体素子１２と接合され、はんだ層５１を介して第２放熱板３２と接合されている。第１スペーサブロック４２は、金属材料（詳しくは銅）で形成されており、封止体２０を構成する材料よりも高い熱伝達率を有する。これらにより、第１半導体素子１２は、封止体２０の背面２２に露出する第１放熱板３６と、封止体２０の正面２１に露出する第２放熱板３２の両者と熱的に接続されている。第１半導体素子１２で発生した熱は、第１放熱板３６及び第２放熱板３２へ伝達され、半導体装置１０の外部へ放出される。   The first spacer block 42 is located between the first semiconductor element 12 and the second heat radiating plate 32. The first spacer block 42 is joined to the first semiconductor element 12 via the solder layer 52 and is joined to the second heat radiating plate 32 via the solder layer 51. The first spacer block 42 is formed of a metal material (specifically, copper) and has a higher heat transfer coefficient than the material constituting the sealing body 20. Thus, the first semiconductor element 12 is thermally connected to both the first heat radiating plate 36 exposed on the back surface 22 of the sealing body 20 and the second heat radiating plate 32 exposed on the front surface 21 of the sealing body 20. ing. The heat generated in the first semiconductor element 12 is transmitted to the first heat radiating plate 36 and the second heat radiating plate 32 and released to the outside of the semiconductor device 10.

第２半導体素子１４についても、同様の構成が採用されている。即ち、他方の第１放熱板３８は、はんだ層５６を介して第２半導体素子１４の下面電極１４ｂに接合されている。また、他方の第２放熱板３４は、第２スペーサブロック４４及びはんだ層５４、５５を介して、第２半導体素子１４の上面電極１４ａに接合されている。即ち、第１放熱板３８と第２放熱板３４は、第２半導体素子１４を挟んで対向する一対の放熱板を構成している。第２スペーサブロック４４は、金属材料（詳しくは銅）で形成されており、封止体２０を構成する材料よりも高い熱伝達率を有する。これらにより、第２半導体素子１４は、封止体２０の背面２２に露出する第１放熱板３８と、封止体２０の正面２１に露出する第２放熱板３４の両者と熱的に接続されている。第２半導体素子１４で発生した熱は、第１放熱板３８及び第２放熱板３４へ伝達され、半導体装置１０の外部へ放出される。   The second semiconductor element 14 has the same configuration. That is, the other first heat radiation plate 38 is joined to the lower surface electrode 14 b of the second semiconductor element 14 via the solder layer 56. The other second heat radiating plate 34 is joined to the upper surface electrode 14 a of the second semiconductor element 14 via the second spacer block 44 and the solder layers 54 and 55. That is, the first heat radiating plate 38 and the second heat radiating plate 34 constitute a pair of heat radiating plates facing each other with the second semiconductor element 14 interposed therebetween. The second spacer block 44 is formed of a metal material (specifically, copper) and has a higher heat transfer coefficient than the material constituting the sealing body 20. Thus, the second semiconductor element 14 is thermally connected to both the first heat radiating plate 38 exposed on the back surface 22 of the sealing body 20 and the second heat radiating plate 34 exposed on the front surface 21 of the sealing body 20. ing. The heat generated in the second semiconductor element 14 is transmitted to the first heat radiating plate 38 and the second heat radiating plate 34 and released to the outside of the semiconductor device 10.

本実施例の半導体装置１０では、二つの第１放熱板３６、３８、二つの第２放熱板３２、３４、第１スペーサブロック４２及び第２スペーサブロック４４が、単に放熱用の部材ではなく、第１半導体素子１２及び第２半導体素子１４へ電気的に接続された導電経路を構成する。ここで、第２半導体素子１４の下面電極１４ｂに接続された第１放熱板３８の継手３９と、第１半導体素子１２の上面電極１２ａに接続された第２放熱板３２の継手３３は、はんだ層５７を介して接合されており、互いに電気的に接続されている。これにより、第１半導体素子１２と第２半導体素子１４が電気的に直列に接続されている。   In the semiconductor device 10 of the present embodiment, the two first heat radiating plates 36 and 38, the two second heat radiating plates 32 and 34, the first spacer block 42 and the second spacer block 44 are not merely heat radiating members, A conductive path electrically connected to the first semiconductor element 12 and the second semiconductor element 14 is formed. Here, the joint 39 of the first heat radiating plate 38 connected to the lower surface electrode 14b of the second semiconductor element 14 and the joint 33 of the second heat radiating plate 32 connected to the upper surface electrode 12a of the first semiconductor element 12 are soldered. The layers 57 are joined and electrically connected to each other. Thereby, the first semiconductor element 12 and the second semiconductor element 14 are electrically connected in series.

図１、図３に示すように、半導体装置１０はさらに、複数の第１信号端子６２と、複数の第２信号端子６４とを備える。それぞれの第１信号端子６２及び第２信号端子６４は、封止体２０の上面２３から、図面においてＺ軸正方向に突出している。図３に示すように、複数の第１信号端子６２は、第１半導体素子１２に設けられた複数の信号パッド１２ｃへ電気的に接続されている。一例であるが、複数の第１信号端子６２には、ゲート信号用の信号端子、温度センス用の信号端子及び電流センス用の信号端子が含まれる。同様に、図示省略するが、複数の第２信号端子６４は、第２半導体素子１４に設けられた複数の信号パッドへ電気的に接続されている。複数の第１信号端子６２にも、例えば、ゲート信号用の信号端子、温度センス用の信号端子及び電流センス用の信号端子が含まれる。   As shown in FIGS. 1 and 3, the semiconductor device 10 further includes a plurality of first signal terminals 62 and a plurality of second signal terminals 64. Each of the first signal terminal 62 and the second signal terminal 64 protrudes from the upper surface 23 of the sealing body 20 in the positive Z-axis direction in the drawing. As shown in FIG. 3, the plurality of first signal terminals 62 are electrically connected to the plurality of signal pads 12 c provided in the first semiconductor element 12. As an example, the plurality of first signal terminals 62 include a signal terminal for a gate signal, a signal terminal for temperature sensing, and a signal terminal for current sensing. Similarly, although not shown, the plurality of second signal terminals 64 are electrically connected to a plurality of signal pads provided in the second semiconductor element 14. The plurality of first signal terminals 62 also include, for example, a signal terminal for gate signals, a signal terminal for temperature sensing, and a signal terminal for current sensing.

半導体装置１０はさらに、正極端子６６と負極端子６７と出力端子６８とを備える。正極端子６６、負極端子６７及び出力端子６８は、封止体２０の下面２４から、図面においてＺ軸負方向に突出している。正極端子６６は、第１半導体素子１２の下面電極１２ｂに接合された第１放熱板３６と電気的に接続されている。負極端子６７は、第２半導体素子１４の上面電極１４ａに第２スペーサブロック４４を介して接合された第２放熱板３４と電気的に接続されている。そして、出力端子６８は、第２半導体素子１４の下面電極１４ｂに接合された第１放熱板３８と電気的に接続されている。これにより、正極端子６６は第１半導体素子１２の下面電極１２ｂと電気的に接続され、負極端子６７は第２半導体素子１４の上面電極１４ａと電気的に接続され、出力端子６８は第１半導体素子１２の上面電極１２ａ及び第２半導体素子１４の下面電極１４ｂと電気的に接続されている（図４参照）。   The semiconductor device 10 further includes a positive terminal 66, a negative terminal 67, and an output terminal 68. The positive terminal 66, the negative terminal 67, and the output terminal 68 protrude from the lower surface 24 of the sealing body 20 in the negative Z-axis direction in the drawing. The positive electrode terminal 66 is electrically connected to the first heat radiating plate 36 joined to the lower surface electrode 12 b of the first semiconductor element 12. The negative terminal 67 is electrically connected to the second heat radiating plate 34 joined to the upper surface electrode 14 a of the second semiconductor element 14 via the second spacer block 44. The output terminal 68 is electrically connected to the first heat radiating plate 38 joined to the lower surface electrode 14b of the second semiconductor element 14. Thereby, the positive terminal 66 is electrically connected to the lower surface electrode 12b of the first semiconductor element 12, the negative terminal 67 is electrically connected to the upper surface electrode 14a of the second semiconductor element 14, and the output terminal 68 is connected to the first semiconductor. The upper surface electrode 12a of the element 12 and the lower surface electrode 14b of the second semiconductor element 14 are electrically connected (see FIG. 4).

次いで、図２、３、５を参照して第１放熱板３６、３８の構造の詳細を説明する。半導体素子１２、１４は、トランスファー成形により封止体２０を構成する樹脂材料によって封止される。第１放熱板３６、３８は、トランスファー成形を適切に実施するために、以下で説明する構造を備える。図５には、トランスファー成形の際に第１放熱板３６、３８が金型７０内に配置された様子が示されている。金型７０は、封止体２０が注入される注入口７２を有する。第１放熱板３６は、周辺溝３６ａ、注入溝３６ｂ及び排出溝３６ｃを有する。周辺溝３６ａは、第１半導体素子１２の外縁に沿って延伸するとともに（図５参照）、その延伸方向に垂直な断面では、第１半導体素子１２に近づくにつれて深くなる（図２、図３参照）。注入溝３６ｂは、周辺溝３６ａの第１位置３７ａから第１放熱板３６の周縁まで伸びる。第１位置３７ａは、周辺溝３６ａのうち、注入口７２に最も近い位置である。排出溝３６ｃは、周辺溝３６ａの第２位置３７ｂから第１放熱板３６の周縁まで伸びる。第２位置３７ｂは、第１半導体素子１２を挟んで第１位置３７ａの反対側に位置する。   Next, the details of the structure of the first heat radiation plates 36 and 38 will be described with reference to FIGS. The semiconductor elements 12 and 14 are sealed with a resin material constituting the sealing body 20 by transfer molding. The first heat radiation plates 36 and 38 have a structure described below in order to appropriately perform transfer molding. FIG. 5 shows a state in which the first heat radiating plates 36 and 38 are arranged in the mold 70 during the transfer molding. The mold 70 has an injection port 72 into which the sealing body 20 is injected. The first heat radiating plate 36 includes a peripheral groove 36a, an injection groove 36b, and a discharge groove 36c. The peripheral groove 36a extends along the outer edge of the first semiconductor element 12 (see FIG. 5), and becomes deeper as it approaches the first semiconductor element 12 in a cross section perpendicular to the extending direction (see FIGS. 2 and 3). ). The injection groove 36 b extends from the first position 37 a of the peripheral groove 36 a to the periphery of the first heat radiating plate 36. The first position 37a is a position closest to the inlet 72 in the peripheral groove 36a. The discharge groove 36 c extends from the second position 37 b of the peripheral groove 36 a to the periphery of the first heat radiating plate 36. The second position 37b is located on the opposite side of the first position 37a with the first semiconductor element 12 interposed therebetween.

他方の第１放熱板３８についても、同様の構成が採用されている。即ち、第１放熱板３８は、周辺溝３８ａ、注入溝３８ｂ及び排出溝３８ｃを有する。周辺溝３８ａは、第２半導体素子１４の外縁に沿って延伸するとともに、その延伸方向に垂直な断面では、第２半導体素子１４に近づくにつれて深くなる。注入溝３８ｂは、周辺溝３８ａの第１位置３９ａから第１放熱板３６の周縁まで伸びる。第１位置３９ａは、周辺溝３８ａのうち、注入口７２に最も近い位置である。排出溝３８ｃは、周辺溝３８ａの第２位置３９ｂから第１放熱板３８の周縁まで伸びる。第２位置３９ｂは、第２半導体素子１４を挟んで第１位置３９ａの反対側に位置する。   The same configuration is adopted for the other first heat radiating plate 38. That is, the first heat radiating plate 38 includes a peripheral groove 38a, an injection groove 38b, and a discharge groove 38c. The peripheral groove 38 a extends along the outer edge of the second semiconductor element 14, and becomes deeper as it approaches the second semiconductor element 14 in a cross section perpendicular to the extending direction. The injection groove 38 b extends from the first position 39 a of the peripheral groove 38 a to the periphery of the first heat radiating plate 36. The first position 39a is a position closest to the inlet 72 in the peripheral groove 38a. The discharge groove 38 c extends from the second position 39 b of the peripheral groove 38 a to the periphery of the first heat radiating plate 38. The second position 39b is located on the opposite side of the first position 39a with the second semiconductor element 14 in between.

図６、図７には、比較例の半導体装置の製造工程においてトランスファー成形が実施される様子が示されている。比較例の半導体装置では、第１放熱板３６、３８は、周辺溝、注入溝及び排出溝を有さない。トランスファー成形では、半製品を金型７０内に配置する。半製品では、一対の放熱板３２、３６の間に第１半導体素子１２及び第１スペーサブロック４２がはんだ付けされており、一対の放熱板３４、３８の間に第２半導体素子１４及び第２スペーサブロック４４がはんだ付けされている。ただし、図６、図７では、半導体素子１２、１４及びスペーサブロック４２、４４が省略され、半導体素子１２、１４が配置される位置が破線で示されている。注入口７２から金型７０内へ加熱された樹脂材料２０ａが注入されると、樹脂材料２０ａは、金型７０内の空間を充填するように広がり、一対の放熱板３４、３８の間にも流れ込む。一対の放熱板３４、３８の間に流れ込んだ樹脂材料２０ａは、第２半導体素子１４及び第２スペーサブロック４４を避けるように、第２半導体素子１４及び第２スペーサブロック４４の一方側と他方側とに分岐して流れる。そして、一方側を通って流れた樹脂材料２０ａと、他方側を通って流れた樹脂材料２０ａは、第２半導体素子１４及び第２スペーサブロック４４を越えた位置で再び合流する（図６参照）。   6 and 7 show how transfer molding is performed in the manufacturing process of the semiconductor device of the comparative example. In the semiconductor device of the comparative example, the first heat radiation plates 36 and 38 do not have a peripheral groove, an injection groove, and a discharge groove. In transfer molding, the semi-finished product is placed in the mold 70. In the semi-finished product, the first semiconductor element 12 and the first spacer block 42 are soldered between the pair of radiator plates 32 and 36, and the second semiconductor element 14 and the second semiconductor element 14 and the second spacer block 42 are paired between the pair of radiator plates 34 and 38. The spacer block 44 is soldered. However, in FIGS. 6 and 7, the semiconductor elements 12 and 14 and the spacer blocks 42 and 44 are omitted, and the positions where the semiconductor elements 12 and 14 are arranged are indicated by broken lines. When the heated resin material 20a is injected from the inlet 72 into the mold 70, the resin material 20a spreads so as to fill the space in the mold 70, and also between the pair of heat sinks 34, 38. Flows in. The resin material 20a flowing between the pair of heat sinks 34 and 38 is disposed on one side and the other side of the second semiconductor element 14 and the second spacer block 44 so as to avoid the second semiconductor element 14 and the second spacer block 44. Branches and flows. Then, the resin material 20a flowing through one side and the resin material 20a flowing through the other side merge again at a position beyond the second semiconductor element 14 and the second spacer block 44 (see FIG. 6). .

上記のように、分岐位置で分岐して流れる樹脂材料２０ａが合流する合流位置について説明する。樹脂材料２０ａの流れは、注入口７２から同心円状（あるいは放射状）に広がる第１の流れと、第１の流れが金型７０の側壁にぶつかることによって形成される第２の流れと、が合成された流れである。樹脂材料２０ａは、当該合成された流れによって、第２半導体素子１４及び第２スペーサブロック４４（以下、第２半導体素子１４等）の反対側に回り込む。ここで、第２半導体素子１４等から近い範囲（即ち内側範囲）では、第２の流れについて、一対の放熱板３４、３８による抵抗の影響が大きいので、流速が減少しやすい。そのため、内側範囲では、樹脂材料２０ａが比較的にゆっくり流れる。一方、第２半導体素子１４等から遠い範囲（即ち外側範囲）では、第２の流れについて、一対の放熱板３４、３８による抵抗の影響が小さいので、流速が減少しにくい。そのため、外側範囲では、樹脂材料２０ａが比較的に速く流れる。そのため、樹脂材料２０ａが第２半導体素子１４及び第２スペーサブロック４４の両側へ分岐して流れたときに、外側範囲を流れる樹脂材料２０ａが先に合流し、その後に内側範囲を流れる樹脂材料２０ａが合流する。その結果、樹脂材料２０ａと第２半導体素子１４との間に空気が巻き込まれ、内側範囲に気泡が発生する（図６参照）。   As described above, the joining position where the resin material 20a branched and flowing at the branching position joins will be described. The flow of the resin material 20 a is a combination of a first flow that spreads concentrically (or radially) from the inlet 72 and a second flow that is formed when the first flow hits the side wall of the mold 70. Is the flow. The resin material 20a wraps around the opposite side of the second semiconductor element 14 and the second spacer block 44 (hereinafter referred to as the second semiconductor element 14 etc.) by the combined flow. Here, in the range close to the second semiconductor element 14 and the like (that is, the inner range), the flow rate is likely to decrease because the resistance of the second flow by the pair of heat sinks 34 and 38 is large. Therefore, the resin material 20a flows relatively slowly in the inner range. On the other hand, in the range far from the second semiconductor element 14 or the like (that is, the outer range), the second flow is less affected by the resistance due to the pair of heat sinks 34 and 38, so the flow rate is less likely to decrease. Therefore, the resin material 20a flows relatively quickly in the outer range. Therefore, when the resin material 20a branches and flows to both sides of the second semiconductor element 14 and the second spacer block 44, the resin material 20a flowing in the outer range first merges, and then the resin material 20a flowing in the inner range. Join. As a result, air is entrained between the resin material 20a and the second semiconductor element 14, and bubbles are generated in the inner range (see FIG. 6).

樹脂材料２０ａの注入が続けられると、同様に、第１半導体素子１２及び第１スペーサブロック４２から近い範囲（即ち内側範囲）でも気泡が発生する。そして、さらに樹脂材料２０ａの注入が続けられることによって、樹脂材料２０ａが一対の放熱板３４、３８の間と、一対の放熱板３２、３６の間と、に充填される。しかし、二箇所の内側範囲に発生した気泡は、半導体装置１０内に残存することがある。このように気泡が残存すると、半導体装置１０内のはんだ層５１〜５６の歪振幅が増加し、はんだ層５１〜５６が劣化するおそれがある。   When the injection of the resin material 20a is continued, air bubbles are generated in a range close to the first semiconductor element 12 and the first spacer block 42 (that is, the inner range). Further, by continuing the injection of the resin material 20a, the resin material 20a is filled between the pair of heat sinks 34 and 38 and between the pair of heat sinks 32 and 36. However, bubbles generated in the two inner ranges may remain in the semiconductor device 10. If bubbles remain in this manner, the strain amplitude of the solder layers 51 to 56 in the semiconductor device 10 increases, and the solder layers 51 to 56 may be deteriorated.

図８、図９には、本実施例の半導体装置１０の製造工程においてトランスファー成形が実施される様子が示されている。比較例と同様に、半製品が金型７０内に配置され、注入口７２から金型７０内へ加熱された樹脂材料２０ａが注入されると、樹脂材料２０ａは、金型７０内の空間を充填するように広がり、一対の放熱板３４、３８の間にも流れ込む。一対の放熱板３４、３８の間に流れ込んだ樹脂材料２０ａは、分岐位置で一方側と他方側とに分岐して流れ、合流位置で再び合流する（図８参照）。ただし、比較例と異なり、本実施例では、第１放熱板３８の内側範囲に周辺溝３８ａが設けられているので（図５参照）、樹脂材料２０ａが流れることができるスペースが大きくなり、樹脂材料２０ａが受ける抵抗が緩和される。即ち、内側範囲において樹脂材料２０ａが流れやすくなる。また、第１放熱板３８の表面に注入溝３８ｂと排出溝３８ｃがさらに設けられているので（図５参照）、内側範囲へ向かう樹脂材料２０ａの流れ、及び、内側範囲から排出される樹脂材料２０ａの流れが促進される。このような構成により、外側範囲を流れる樹脂材料２０ａが合流する前に、内側範囲を流れる樹脂材料２０ａが合流しやすくなっている。その結果、半導体装置１０の封止体２０内に気泡が発生することを抑制することができる（図８参照）。樹脂材料２０ａの注入が続けられると、同様に、第１放熱板３６の内側範囲でも気泡を抑制することができる（図９参照）。   8 and 9 show how transfer molding is performed in the manufacturing process of the semiconductor device 10 of the present embodiment. Similar to the comparative example, when the semi-finished product is placed in the mold 70 and the heated resin material 20a is injected into the mold 70 from the injection port 72, the resin material 20a is placed in the space in the mold 70. It spreads so as to fill, and also flows between the pair of heat sinks 34 and 38. The resin material 20a flowing between the pair of heat sinks 34 and 38 branches and flows to one side and the other side at the branch position, and merges again at the merge position (see FIG. 8). However, unlike the comparative example, in this embodiment, the peripheral groove 38a is provided in the inner range of the first heat radiating plate 38 (see FIG. 5), so that the space through which the resin material 20a can flow increases, and the resin The resistance received by the material 20a is relaxed. That is, the resin material 20a easily flows in the inner range. Moreover, since the injection groove 38b and the discharge groove 38c are further provided on the surface of the first heat radiating plate 38 (see FIG. 5), the flow of the resin material 20a toward the inner range and the resin material discharged from the inner range. The flow of 20a is promoted. With such a configuration, the resin material 20a flowing in the inner range is easily merged before the resin material 20a flowing in the outer range is merged. As a result, it is possible to suppress the generation of bubbles in the sealing body 20 of the semiconductor device 10 (see FIG. 8). If the injection of the resin material 20a is continued, air bubbles can be similarly suppressed in the inner area of the first heat radiating plate 36 (see FIG. 9).

（第２実施例）
第２実施例では、第２放熱板３２、３４の構造のみが第１実施例とは異なる。図１０には、本実施例の第２放熱板３２が示されている。また、第１スペーサブロック４２が接合される領域が破線で示されている。半導体装置１０内での第２放熱板３２の位置関係について、第２放熱板３２の頂点Ａは、第１放熱板３６の注入溝３６ｂに対向し、頂点Ｃは、第１放熱板３６の排出溝３６ｃに対向する。 (Second embodiment)
In the second embodiment, only the structure of the second heat radiating plates 32 and 34 is different from the first embodiment. FIG. 10 shows the second heat radiating plate 32 of the present embodiment. A region where the first spacer block 42 is joined is indicated by a broken line. Regarding the positional relationship of the second heat radiating plate 32 in the semiconductor device 10, the vertex A of the second heat radiating plate 32 faces the injection groove 36 b of the first heat radiating plate 36, and the vertex C is the discharge of the first heat radiating plate 36. Opposite the groove 36c.

第２放熱板３２のＸ軸方向の厚さは、Ｚ軸負方向側の面の中央部分と、Ｙ軸正方向側の面の中央部分と、において最大となっている。第２放熱板３２のＸ軸方向の厚さは、第１スペーサブロック４２が接合される領域と、第２放熱板３２の頂点Ｂ、Ｃ、Ｄによって形成される三角形ＢＣＤの内部と、線分ＡＣ上と、において最小となっている。第２放熱板３２のＸ軸負方向側の面は、Ｘ軸方向の厚さが最大となる位置から、Ｘ軸方向の厚さが最小となる位置にかけて傾斜している（図１１、図１２参照）。なお、図示省略しているが、第２放熱板３４も、第２放熱板３２と同様の構造である。   The thickness of the second heat radiating plate 32 in the X-axis direction is maximum at the central portion of the surface on the Z-axis negative direction side and the central portion of the surface on the Y-axis positive direction side. The thickness of the second heat radiating plate 32 in the X-axis direction is such that the region where the first spacer block 42 is joined, the inside of the triangle BCD formed by the apexes B, C, and D of the second heat radiating plate 32, and the line segment It is minimum on AC. The surface on the negative X-axis direction side of the second heat radiating plate 32 is inclined from the position where the thickness in the X-axis direction is maximum to the position where the thickness in the X-axis direction is minimum (FIGS. 11 and 12). reference). Although not shown, the second heat radiating plate 34 has the same structure as the second heat radiating plate 32.

第２放熱板３２がこのような構造を採用していることによって、第１放熱板３６の外側範囲では、トランスファー成形において樹脂材料２０ａが流れることができるスペースが小さくなっている。これにより、外側範囲において樹脂材料２０ａが流れにくくなる。そのため、外側範囲を流れる樹脂材料２０ａが合流する前に、内側範囲を流れる樹脂材料２０ａがより合流しやすくなっている。その結果、半導体装置１０の封止体２０内に気泡が発生することをより効果的に抑制することができる。なお、他方の第２放熱板３４についても同様の作用及び効果を奏することができる。   By adopting such a structure for the second heat radiating plate 32, the space in which the resin material 20 a can flow in the transfer molding is reduced in the outer range of the first heat radiating plate 36. Thereby, it becomes difficult for the resin material 20a to flow in the outer side range. Therefore, before the resin material 20a flowing in the outer area joins, the resin material 20a flowing in the inner area becomes easier to join. As a result, generation of bubbles in the sealing body 20 of the semiconductor device 10 can be more effectively suppressed. In addition, the same effect | action and effect can be show | played also about the other 2nd heat sink 34.

（第３実施例）
第３実施例では、第１放熱板３６、３８の構造のみが第１実施例とは異なる。第１放熱板３６のＸ軸正方向側の面（即ち、第２放熱板３２に対向する面）は、表面が比較的に平滑な第１領域３６ｄ（図１３の色付きでない領域）と、表面が比較的に粗い第２領域３６ｅ（図１３の色付きの領域）と、を含む。第１領域３６ｄは、第１半導体素子１２の周縁から第１距離Ｌ０までの範囲である。第２領域３６ｅは、第１領域３６ｄの外側に位置し、第１放熱板３６の周縁まで広がっている。第１半導体素子１２の周縁から第１放熱板３６の周縁（即ち第２領域３６ｅの周縁）までの距離を第２距離Ｌとしたときに、第１領域３６ｄの周縁までの第１距離Ｌ０に対する第２距離Ｌの比の値（Ｌ／Ｌ０）は、２よりも大きく、３よりも小さいことが望ましい。なお、図示省略しているが、第１放熱板３８も第１放熱板３６と同様の構造を有する。 (Third embodiment)
In the third embodiment, only the structure of the first heat radiating plates 36 and 38 is different from the first embodiment. A surface on the positive side in the X-axis direction of the first heat radiating plate 36 (that is, a surface facing the second heat radiating plate 32) is a first region 36d (non-colored region in FIG. 13) having a relatively smooth surface, and a surface Includes a relatively rough second region 36e (the colored region in FIG. 13). The first region 36d is a range from the periphery of the first semiconductor element 12 to the first distance L0. The second region 36e is located outside the first region 36d and extends to the periphery of the first heat radiating plate 36. When the distance from the periphery of the first semiconductor element 12 to the periphery of the first heat dissipation plate 36 (that is, the periphery of the second region 36e) is the second distance L, the first distance L0 to the periphery of the first region 36d The ratio value (L / L0) of the second distance L is preferably larger than 2 and smaller than 3. Although not shown, the first heat radiating plate 38 has the same structure as the first heat radiating plate 36.

第１放熱板３６がこのような構造を採用していることによって、第１放熱板３６の内側範囲で流れる樹脂材料２０ａへの抵抗が小さくなり、第１放熱板３６の外側範囲で流れる樹脂材料２０ａへの抵抗が大きくなっている。即ち、内側範囲において樹脂材料２０ａが流れやすくなり、外側範囲において封止体２０が流れにくくなる。そのため、外側範囲を流れる樹脂材料２０ａが合流する前に、内側範囲を流れる樹脂材料２０ａがより合流しやすくなっている。その結果、半導体装置１０の樹脂材料２０ａ内に気泡が発生することをより効果的に抑制することができる。なお、第１放熱板３８についても、同様の作用及び効果を奏することができる。   By adopting such a structure for the first heat radiating plate 36, the resistance to the resin material 20 a flowing in the inner range of the first heat radiating plate 36 is reduced, and the resin material flowing in the outer range of the first heat radiating plate 36. The resistance to 20a is increased. That is, the resin material 20a easily flows in the inner range, and the sealing body 20 hardly flows in the outer range. Therefore, before the resin material 20a flowing in the outer area joins, the resin material 20a flowing in the inner area becomes easier to join. As a result, the generation of bubbles in the resin material 20a of the semiconductor device 10 can be more effectively suppressed. In addition, the same effect | action and effect can be show | played also about the 1st heat sink 38.

以上、いくつかの具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。以下に、本明細書の開示内容から把握される技術的事項を列記する。なお、以下に記載する技術的事項は、それぞれが独立した技術的事項であり、単独であるいは各種の組合せによって技術的有用性を発揮するものである。例えば、第２実施例において、第１放熱板３６、３８のそれぞれは、周辺溝、注入溝及び排出溝を有さなくてもよい。第２放熱板３２、３４の少なくとも一方が、図１０〜１２に示される構造を有すること自体で、半導体装置１０の封止体２０内に気泡が発生することを抑制するという一定の効果を奏し得る。また、第３実施例において、第１放熱板３６、３８のそれぞれは、周辺溝、注入溝及び排出溝を有さなくてもよい。第１放熱板３６、３８の少なくとも一方が第１領域と第２領域とを含むこと自体で、半導体装置１０の封止体２０内に気泡が発生することを抑制するという一定の効果を奏し得る。   Several specific examples have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical matters grasped from the disclosure content of the present specification are listed below. The technical items described below are independent technical items, and exhibit technical usefulness alone or in various combinations. For example, in the second embodiment, each of the first heat radiation plates 36 and 38 may not have a peripheral groove, an injection groove, and a discharge groove. When at least one of the second heat radiation plates 32 and 34 has the structure shown in FIGS. 10 to 12, there is a certain effect of suppressing generation of bubbles in the sealing body 20 of the semiconductor device 10. obtain. In the third embodiment, each of the first heat radiation plates 36 and 38 may not have a peripheral groove, an injection groove, and a discharge groove. When at least one of the first heat radiation plates 36 and 38 includes the first region and the second region, a certain effect of suppressing generation of bubbles in the sealing body 20 of the semiconductor device 10 can be obtained. .

１０、１００：半導体装置
１２：第１半導体素子
１２ａ：上面電極
１２ｂ：下面電極
１２ｃ：信号パッド
１４：第２半導体素子
１４ａ：上面電極
１４ｂ：下面電極
２０：封止体
２１：封止体の正面
２２：封止体の背面
２３：封止体の上面
２４：封止体の下面
２５：封止体の右側面
２６：封止体の左側面
３２、３４：第２放熱板
３３、３９：継手
３６、３８：第１放熱板
３６ａ、３８ａ：周辺溝
３６ｂ、３８ｂ：注入溝
３６ｃ、３８ｃ：排出溝
３７ａ、３７ｂ、３９ａ、３９ｂ：位置
３９：継手
４２、４４：スペーサブロック
５１〜５７：はんだ層
６２：第１信号端子
６４：第２信号端子
６６：正極端子
６７：負極端子
６８：出力端子
７０：金型
７２：注入口
Ａ〜Ｄ：頂点 DESCRIPTION OF SYMBOLS 10, 100: Semiconductor device 12: 1st semiconductor element 12a: Upper surface electrode 12b: Lower surface electrode 12c: Signal pad 14: 2nd semiconductor element 14a: Upper surface electrode 14b: Lower surface electrode 20: Sealing body 21: Front of sealing body 22: Back surface of the sealing body 23: Upper surface of the sealing body 24: Lower surface of the sealing body 25: Right side surface of the sealing body 26: Left side surfaces 32, 34 of the sealing body: Second heat radiation plates 33, 39: Joints 36, 38: first heat radiation plate 36a, 38a: peripheral groove 36b, 38b: injection groove 36c, 38c: discharge groove 37a, 37b, 39a, 39b: position 39: joint 42, 44: spacer block 51 to 57: solder layer 62: first signal terminal 64: second signal terminal 66: positive terminal 67: negative terminal 68: output terminal 70: mold 72: injection ports A to D: apex

Claims (1)

半導体素子と、
前記半導体素子が一方の面に接合された第１の放熱板と、前記半導体素子を挟んで前記第１の放熱板に対向する第２の放熱板と、を有する一対の放熱板と、
前記半導体素子及び前記第２の放熱板の間に位置しているとともに、前記半導体素子及び前記第２の放熱板のそれぞれと接合されたスペーサブロックと、
前記一対の放熱板の間に充填されている樹脂と、を備え、
前記第１の放熱板の前記一方の面は、
前記半導体素子の外縁に沿って延伸するとともに、その延伸方向に垂直な断面では、前記半導体素子に近づくにつれて深くなる周辺溝と、
前記周辺溝の第１位置から前記第１の放熱板の周縁まで伸びる注入溝と、
前記周辺溝の第２位置から前記第１の放熱板の周縁まで伸びる排出溝と、を有し、
前記周辺溝の前記第１位置と前記第２位置は、前記半導体素子を挟んで互いに反対側に位置する半導体装置。 A semiconductor element;
A pair of heat radiating plates each having a first heat radiating plate bonded to one surface of the semiconductor element and a second heat radiating plate facing the first heat radiating plate with the semiconductor element interposed therebetween;
A spacer block located between the semiconductor element and the second heat sink and joined to each of the semiconductor element and the second heat sink;
A resin filled between the pair of heat sinks,
The one surface of the first heat radiating plate is
In the cross section extending along the outer edge of the semiconductor element and perpendicular to the extending direction, a peripheral groove that becomes deeper as the semiconductor element is approached;
An injection groove extending from the first position of the peripheral groove to the periphery of the first heat sink;
A discharge groove extending from a second position of the peripheral groove to a peripheral edge of the first heat radiating plate,
The semiconductor device in which the first position and the second position of the peripheral groove are located on opposite sides of the semiconductor element.
JP2016027673A 2016-02-17 2016-02-17 Semiconductor device Pending JP2017147316A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019068409A1 (en) * 2017-10-06 2019-04-11 Zf Friedrichshafen Ag Heat-removing arrangement and production method
JP2019087555A (en) * 2017-11-01 2019-06-06 トヨタ自動車株式会社 Method for manufacturing semiconductor device
US10886207B2 (en) 2018-05-15 2021-01-05 Denso Corporation Semiconductor device
US11274972B2 (en) 2018-02-06 2022-03-15 Denso Corporation Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019068409A1 (en) * 2017-10-06 2019-04-11 Zf Friedrichshafen Ag Heat-removing arrangement and production method
JP2019087555A (en) * 2017-11-01 2019-06-06 トヨタ自動車株式会社 Method for manufacturing semiconductor device
US11274972B2 (en) 2018-02-06 2022-03-15 Denso Corporation Semiconductor device
US10886207B2 (en) 2018-05-15 2021-01-05 Denso Corporation Semiconductor device

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