JP7196761B2 - semiconductor equipment - Google Patents

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JP7196761B2
JP7196761B2 JP2019092435A JP2019092435A JP7196761B2 JP 7196761 B2 JP7196761 B2 JP 7196761B2 JP 2019092435 A JP2019092435 A JP 2019092435A JP 2019092435 A JP2019092435 A JP 2019092435A JP 7196761 B2 JP7196761 B2 JP 7196761B2
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conductive plate
semiconductor element
electrically connected
metal layer
intermediate conductive
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JP2020188167A (en
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崇功 川島
卓矢 門口
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Denso Corp
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Denso Corp
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本明細書が開示する技術は、半導体装置に関する。 The technology disclosed in this specification relates to a semiconductor device.

特許文献１に、半導体装置が開示されている。この半導体装置は、積層配置された上側導電板、中間導電板及び下側導電板と、上側導電板と中間導電板との間に位置する第１半導体素子と、中間導電板と下側導電板との間に位置する第２半導体素子とを備える。 A semiconductor device is disclosed in Japanese Patent Laid-Open No. 2002-200012. This semiconductor device includes an upper conductive plate, an intermediate conductive plate, and a lower conductive plate that are stacked, a first semiconductor element positioned between the upper conductive plate and the intermediate conductive plate, an intermediate conductive plate, and a lower conductive plate. and a second semiconductor element located between.

特開２０１６－３６０４７号公報JP 2016-36047 A

上記した半導体装置では、第１半導体素子及び第２半導体素子のそれぞれが、通電によって発熱する。第１半導体素子及び第２半導体素子が発熱すると、それらに隣接する三つの導電板の温度も上昇して、各々の導電板には熱膨張が生じる。特に、第１半導体素子と第２半導体素子との間に位置する中間導電板は、上側導電板及び下側導電板よりも高温となりやすく、比較的に大きく熱膨張する傾向がある。このような不均一な熱膨張は、半導体装置内に生じる歪を局所的に増大させることがあり、例えば半導体装置の耐久性を低下させるおそれがある。 In the semiconductor device described above, each of the first semiconductor element and the second semiconductor element generates heat when energized. When the first semiconductor element and the second semiconductor element generate heat, the temperature of the three conductive plates adjacent to them also rises, causing thermal expansion in each of the conductive plates. In particular, the intermediate conductive plate located between the first semiconductor element and the second semiconductor element tends to be heated to a higher temperature than the upper and lower conductive plates and tends to undergo relatively large thermal expansion. Such non-uniform thermal expansion may locally increase the strain generated in the semiconductor device, and may reduce the durability of the semiconductor device, for example.

本明細書は、三以上の導電板が積層された半導体装置において、それらの導電板に生じる不均一な熱膨張を抑制し得る技術を提供する。 This specification provides a technique capable of suppressing uneven thermal expansion occurring in the conductive plates in a semiconductor device in which three or more conductive plates are stacked.

本明細書が開示する半導体装置は、積層配置された上側導電板、中間導電板及び下側導電板と、上側導電板と中間導電板との間に位置しており、上側導電板と中間導電板とのそれぞれに電気的に接続された第１半導体素子と、中間導電板と下側導電板との間に位置しており、中間導電板と下側導電板とのそれぞれに電気的に接続された第２半導体素子とを備える。そして、中間導電板の面内方向における線膨張係数は、上側導電板の面内方向における線膨張係数及び下側導電板の面内方向における線膨張係数よりも小さい。 A semiconductor device disclosed in this specification includes an upper conductive plate, an intermediate conductive plate, and a lower conductive plate that are stacked and arranged, and is positioned between the upper conductive plate and the intermediate conductive plate. a first semiconductor element electrically connected to each of the plates and positioned between the intermediate conductive plate and the lower conductive plate and electrically connected to each of the intermediate conductive plate and the lower conductive plate; and a second semiconductor element. The in-plane linear expansion coefficient of the intermediate conductive plate is smaller than the in-plane linear expansion coefficient of the upper conductive plate and the in-plane linear expansion coefficient of the lower conductive plate.

上記した半導体装置では、中間導電板の線膨張係数が、上側導電板の線膨張係数及び下側導電板の線膨張係数よりも小さい。従って、中間導電板の温度が、上側導電板の温度及び下側導電板の温度よりも高温となったときでも、三つの導電板に不均一な熱膨張が生じることを抑制することができる。 In the semiconductor device described above, the coefficient of linear expansion of the intermediate conductive plate is smaller than the coefficient of linear expansion of the upper conductive plate and the coefficient of linear expansion of the lower conductive plate. Therefore, even when the temperature of the intermediate conductive plate becomes higher than the temperature of the upper conductive plate and the temperature of the lower conductive plate, it is possible to suppress uneven thermal expansion of the three conductive plates.

ここで、上側導電板の面内方向における線膨張係数とは、上側導電板に対して平行な方向（即ち、上側導電板の法線に対して垂直な方向）における上側導電板の線膨張係数を意味する。中間導電板の面内方向における線膨張係数及び下側導電板の面内方向における線膨張係数についても同様である。上側導電板、中間導電板及び下側導電板の各面内方向は互いに平行であり、それらの三つの導電板は、それらの面内方向に対して垂直は方向に積層配置されている。 Here, the coefficient of linear expansion in the in-plane direction of the upper conductive plate is the coefficient of linear expansion of the upper conductive plate in the direction parallel to the upper conductive plate (that is, the direction perpendicular to the normal to the upper conductive plate). means The same applies to the in-plane linear expansion coefficient of the intermediate conductive plate and the in-plane linear expansion coefficient of the lower conductive plate. The in-plane directions of the upper conductive plate, the intermediate conductive plate, and the lower conductive plate are parallel to each other, and the three conductive plates are stacked in a direction perpendicular to their in-plane directions.

実施例１の半導体装置１０の外観を示す。1 shows the appearance of the semiconductor device 10 of Example 1. FIG. 図１中のＩＩ－ＩＩ線における断面図を示す。2 shows a cross-sectional view taken along line II-II in FIG. 1. FIG. 図１中のＩＩＩ－ＩＩＩ線における断面図を示す。2 shows a cross-sectional view taken along line III-III in FIG. 1; FIG. 実施例１の半導体装置１０の回路構造を示す。1 shows the circuit structure of the semiconductor device 10 of Example 1. FIG. 一変形例の半導体装置１０’の構成を模式的に示す断面図であって、図２に示す断面図に対応する。FIG. 3 is a cross-sectional view schematically showing the configuration of a semiconductor device 10' of a modified example, and corresponds to the cross-sectional view shown in FIG. 一変形例の半導体装置１０’’の構成を模式的に示す断面図であって、図２に示す断面図に対応する。FIG. 3 is a cross-sectional view schematically showing the configuration of a semiconductor device 10 ″ according to a modified example, and corresponds to the cross-sectional view shown in FIG. 2 . 実施例２の半導体装置１０Ａの構成を模式的に示す断面図であって、図２に示す断面図に対応する。FIG. 3 is a cross-sectional view schematically showing the configuration of a semiconductor device 10A of Example 2, corresponding to the cross-sectional view shown in FIG. 2; 実施例２の半導体装置１０Ａの構成を模式的に示す断面図であって、図３に示す断面図に対応する。4 is a cross-sectional view schematically showing the configuration of a semiconductor device 10A of Example 2, and corresponds to the cross-sectional view shown in FIG. 3. FIG. 実施例２の半導体装置１０Ａの回路構造を示す。The circuit structure of the semiconductor device 10A of Example 2 is shown.

本技術の一実施形態において、中間導電板は、絶縁体基板と、絶縁体基板の上面に設けられているとともに、第１半導体素子と電気的に接続された第１金属層と、絶縁体基板の下面に設けられているとともに、第２半導体素子と電気的に接続された第２金属層とを有してもよい。そして。絶縁体基板を構成する絶縁体の線膨張係数が、第１金属層を構成する金属の線膨張係数及び第２金属層を構成する金属の線膨張係数よりも小さくてもよい。このような構成によると、第１金属層及び第２金属層によって中間導電板の導電性を確保しつつ、絶縁体基板によって中間導電板の全体としての線膨張係数を小さくすることができる。 In one embodiment of the present technology, the intermediate conductive plate includes an insulator substrate, a first metal layer provided on an upper surface of the insulator substrate and electrically connected to the first semiconductor element, and an insulator substrate. and a second metal layer electrically connected to the second semiconductor element. and. The linear expansion coefficient of the insulator forming the insulator substrate may be smaller than the linear expansion coefficient of the metal forming the first metal layer and the linear expansion coefficient of the metal forming the second metal layer. According to such a configuration, it is possible to reduce the linear expansion coefficient of the intermediate conductive plate as a whole by the insulator substrate while ensuring the conductivity of the intermediate conductive plate by the first metal layer and the second metal layer.

上記した実施形態において、絶縁体基板はセラミック基板であってもよい。この場合、特に限定されないが、中間導電板は、ＤＢＣ（Direct Bonded Cupper）基板、ＤＢＡ（Direct Bonded Aluminum）、ＡＭＣ（Active Metal Brazed Cupper）基板であってもよい。 In the embodiments described above, the insulator substrate may be a ceramic substrate. In this case, although not particularly limited, the intermediate conductive plate may be a DBC (Direct Bonded Cupper) substrate, a DBA (Direct Bonded Aluminum) substrate, or an AMC (Active Metal Brazed Cupper) substrate.

上記した実施形態において、上側導電板及び下側導電板は、金属板であってもよい。金属板は優れた熱伝導性を有するので、上側導電板及び下側導電板を介した半導体素子の放熱性（即ち、冷却性）を高めることができる。 In the above-described embodiments, the upper conductive plate and the lower conductive plate may be metal plates. Since the metal plate has excellent thermal conductivity, it is possible to enhance the heat radiation (that is, the cooling performance) of the semiconductor element via the upper and lower conductive plates.

本技術の一実施形態において、第１半導体素子と第２半導体素子の各々は、第１主電極と、第１主電極よりも面積の大きい第２主電極とを有してもよい。この場合、各々の半導体素子は、第１主電極よりも第２主電極を介して、より多く熱を外部へ放出する。そのことから、第１半導体素子と第２半導体素子との一方又は両方は、第１主電極において中間導電板と電気的に接続されているとともに、第２主電極において上側導電板又は下側導電板と電気的に接続されているとよい。中間導電板は、第１半導体素子と第２半導体素子との両者から熱を受け取るので、その温度が上昇し易い。しかしながら、放熱量の少ない第１主電極が中間導電板に接続されていると、中間導電板の温度上昇を抑制することができる。 In an embodiment of the present technology, each of the first semiconductor element and the second semiconductor element may have a first main electrode and a second main electrode having a larger area than the first main electrode. In this case, each semiconductor element emits more heat to the outside through the second main electrode than through the first main electrode. Therefore, one or both of the first semiconductor element and the second semiconductor element are electrically connected to the intermediate conductive plate at the first main electrode, and are electrically connected to the upper conductive plate or the lower conductive plate at the second main electrode. It may be electrically connected to the plate. Since the intermediate conductive plate receives heat from both the first semiconductor element and the second semiconductor element, its temperature is likely to rise. However, if the first main electrode, which dissipates less heat, is connected to the intermediate conductive plate, it is possible to suppress the temperature rise of the intermediate conductive plate.

上記した実施形態において、第１半導体素子と第２半導体素子の各々は、第１主電極と同じ側に設けられた信号電極をさらに有してもよい。この場合、中間導電板の第１金属層は、第１半導体素子の第１主電極と電気的に接続された第１主回路部と、第１主回路部から分離されているとともに、第１半導体素子の信号電極と電気的に接続された第１信号回路部とを有してもよい。同様に、中間導電板の第２金属層は、第２半導体素子の第１主電極と電気的に接続された第２主回路部と、第２主回路部から分離されているとともに、前記第２半導体素子の前記信号電極と電気的に接続された第２信号回路部とを有してもよい。このような構成によると、半導体装置の構造を複雑にするとなく、各々の半導体素子の信号電極に接続する回路を構成することができる。 In the above-described embodiments, each of the first semiconductor element and the second semiconductor element may further have a signal electrode provided on the same side as the first main electrode. In this case, the first metal layer of the intermediate conductive plate is separated from the first main circuit portion electrically connected to the first main electrode of the first semiconductor element, and the first main circuit portion. It may have a first signal circuit section electrically connected to the signal electrode of the semiconductor element. Similarly, the second metal layer of the intermediate conductive plate is separated from the second main circuit portion electrically connected to the first main electrode of the second semiconductor element, and the second main circuit portion. It may have a second signal circuit section electrically connected to the signal electrodes of the two semiconductor elements. According to such a configuration, a circuit connected to the signal electrode of each semiconductor element can be configured without complicating the structure of the semiconductor device.

本技術の一実施形態において、中間導電板の面積は、上側導電板の面積及び下側導電板の面積よりも小さくてもよい。即ち、上側導電板の面積及び下側導電板の面積は、中間導電板の面積より大きくてもよい。このような構成によると、各々の半導体素子の熱が、面積の大きな上側導電板及び下側導電板を介して、半導体装置の外部へ効率よく放出される。ここで、中間導電板の面積とは、中間導電板を垂直な方向から見たときの面積を意味する。他の導電板の面積についても同様である。 In one embodiment of the present technology, the area of the middle conductive plate may be smaller than the area of the upper conductive plate and the area of the lower conductive plate. That is, the area of the upper conductive plate and the area of the lower conductive plate may be greater than the area of the intermediate conductive plate. According to such a configuration, the heat of each semiconductor element is efficiently released to the outside of the semiconductor device through the upper conductive plate and the lower conductive plate having large areas. Here, the area of the intermediate conductive plate means the area of the intermediate conductive plate when viewed from the vertical direction. The same applies to areas of other conductive plates.

あるいは、中間導電板の面積は、上側導電板の面積及び下側導電板の面積より大きくてもよい。このような構成によると、中間導電板の熱容量が大きくなるので、中間導電板の温度上昇を抑制することができる。 Alternatively, the area of the intermediate conductive plate may be greater than the area of the upper conductive plate and the area of the lower conductive plate. With such a configuration, the heat capacity of the intermediate conductive plate is increased, so that the temperature rise of the intermediate conductive plate can be suppressed.

本技術の一実施形態において、半導体素子は、第１半導体素子及び第２半導体素子を封止するとともに、上側導電板、中間導電板及び下側導電板を一体に保持する封止体をさらに備えてもよい。この場合、特に限定されないが、上側導電板及び下側導電板は、封止体の表面に露出しているとよい。このような構成によると、各々の半導体素子の熱が、上側導電板及び下側導電板を介して、半導体装置の外部へ効率よく放出される。 In one embodiment of the present technology, the semiconductor device further includes a sealing body that seals the first semiconductor device and the second semiconductor device and holds the upper conductive plate, the intermediate conductive plate, and the lower conductive plate together. may In this case, although not particularly limited, the upper conductive plate and the lower conductive plate are preferably exposed on the surface of the sealing body. According to such a configuration, the heat of each semiconductor element is efficiently released to the outside of the semiconductor device through the upper conductive plate and the lower conductive plate.

（実施例１） 図１－図４を参照して、実施例１の半導体装置１０を説明する。本実施例の半導体装置１０は、例えば電気自動車の電力制御装置に採用され、コンバータやインバータといった電力変換回路の一部を構成することができる。なお、本明細書における電気自動車は、車輪を駆動するモータを有する自動車を広く意味し、例えば、外部の電力によって充電される電気自動車、モータに加えてエンジンを有するハイブリッド車、及び燃料電池を電源とする燃料電池車等を含む。 Example 1 A semiconductor device 10 of Example 1 will be described with reference to FIGS. 1 to 4. FIG. The semiconductor device 10 of the present embodiment is employed, for example, in a power control device for an electric vehicle, and can form part of a power conversion circuit such as a converter or an inverter. An electric vehicle in this specification broadly means a vehicle having a motor for driving the wheels. Including fuel cell vehicles, etc.

半導体装置１０は、複数の半導体素子１２、１４と、複数の導電板１６、１８、２０と、封止体３０とを備える。封止体３０は、複数の半導体素子１２、１４を封止するとともに、複数の導電板１６、１８、２０を一体に保持している。封止体３０は、絶縁性の材料で構成されている。特に限定されないが、本実施例における封止体３０は、例えばエポキシ樹脂といった、封止用の樹脂材料で構成されている。封止体３０は、概して板形状を有しており、上面３０ａ、下面３０ｂ、第１端面３０ｃ、第２端面３０ｄ、第１側面３０ｅ及び第２側面３０ｆを有する。 A semiconductor device 10 includes a plurality of semiconductor elements 12 and 14 , a plurality of conductive plates 16 , 18 and 20 and a sealing body 30 . The sealing body 30 seals the plurality of semiconductor elements 12 and 14 and holds the plurality of conductive plates 16, 18 and 20 together. The sealing body 30 is made of an insulating material. Although not particularly limited, the sealing body 30 in this embodiment is made of a sealing resin material such as epoxy resin. The sealing body 30 generally has a plate shape and has an upper surface 30a, a lower surface 30b, a first end surface 30c, a second end surface 30d, a first side surface 30e and a second side surface 30f.

複数の半導体素子１２、１４は、第１半導体素子１２と、第２半導体素子１４とを含む。第１半導体素子１２と第２半導体素子１４は、パワー半導体素子であって、互いに同一の構造を有する。各々の半導体素子１２、１４は、半導体基板１２ａ、１４ａ、第１主電極１２ｂ、１４ｂ、第２主電極１２ｃ、１４ｃ及び複数の信号電極１２ｄ、１４ｄを備える。半導体基板１２ａ、１４ａは、特に限定されないが、シリコン基板、炭化シリコン基板又は窒化物半導体基板であってもよい。 The plurality of semiconductor elements 12 , 14 includes a first semiconductor element 12 and a second semiconductor element 14 . The first semiconductor element 12 and the second semiconductor element 14 are power semiconductor elements and have the same structure. Each semiconductor element 12, 14 comprises a semiconductor substrate 12a, 14a, first main electrodes 12b, 14b, second main electrodes 12c, 14c and a plurality of signal electrodes 12d, 14d. The semiconductor substrates 12a and 14a are not particularly limited, but may be silicon substrates, silicon carbide substrates, or nitride semiconductor substrates.

第１主電極１２ｂ、１４ｂは、半導体基板１２ａ、１４ａの表面に位置しており、第２主電極１２ｃ、１４ｃは、半導体基板１２ａ、１４ａの裏面に位置している。なお、第１半導体素子１２は反転されて配置されており、図２、図３において、半導体基板１２ａの表面は下方を向いている。第１主電極１２ｂ、１４ｂと第２主電極１２ｃ、１４ｃは、半導体基板１２ａ、１４ａを介して互いに電気的に接続される。特に限定されないが、各々の半導体素子１２、１４は、スイッチング素子であり、第１主電極１２ｂ、１４ｂと第２主電極１２ｃ、１４ｃとの間を、選択的に導通及び遮断することができる。複数の信号電極１２ｄ、１４ｄは、第１主電極１２ｂ、１４ｂと同じく、半導体基板１２ａ、１４ａの表面に位置している。なお、各々の信号電極１２ｄ、１４ｄは、第１主電極１２ｂ、１４ｂ及び第２主電極１２ｃ、１４ｃよりも十分に小さい。但し、半導体基板１２ａ、１４ａの表面には、第１主電極１２ｂ、１４ｂと複数の信号電極１２ｄ、１４ｄの両者が位置するので、第１主電極１２ｂ、１４ｂの面積は、第２主電極１２ｃ、１４ｃの面積よりも小さい。第１主電極１２ｂ、１４ｂ、第２主電極１２ｃ、１４ｃ及び信号電極１２ｄ、４２ｄは、アルミニウム、ニッケル又は金といった、一又は複数種類の金属を用いて構成されることができる。 The first main electrodes 12b, 14b are located on the front surfaces of the semiconductor substrates 12a, 14a, and the second main electrodes 12c, 14c are located on the rear surfaces of the semiconductor substrates 12a, 14a. The first semiconductor element 12 is arranged upside down, and in FIGS. 2 and 3, the surface of the semiconductor substrate 12a faces downward. The first main electrodes 12b, 14b and the second main electrodes 12c, 14c are electrically connected to each other through the semiconductor substrates 12a, 14a. Although not particularly limited, each of the semiconductor elements 12 and 14 is a switching element, and can selectively turn on and off between the first main electrodes 12b and 14b and the second main electrodes 12c and 14c. The plurality of signal electrodes 12d, 14d are located on the surfaces of the semiconductor substrates 12a, 14a, like the first main electrodes 12b, 14b. Each signal electrode 12d, 14d is sufficiently smaller than the first main electrodes 12b, 14b and the second main electrodes 12c, 14c. However, since both the first main electrodes 12b, 14b and the plurality of signal electrodes 12d, 14d are located on the surface of the semiconductor substrates 12a, 14a, the area of the first main electrodes 12b, 14b is equal to that of the second main electrode 12c. , 14c. The first main electrodes 12b, 14b, the second main electrodes 12c, 14c and the signal electrodes 12d, 42d can be constructed using one or more metals such as aluminum, nickel or gold.

一例ではあるが、図４に示すように、本実施例における各々の半導体素子１２、１４は、ＩＧＢＴ（Insulated Gate Bipolar Transistor）とダイオードとが一体化されたＲＣ（Reverse Conducting）－ＩＧＢＴである。第１主電極１２ｂ、１４ｂは、ＩＧＢＴのエミッタ及びダイオードのアノードに接続されており、第２主電極１２ｃ、１４ｃは、ＩＧＢＴのコレクタ及びダイオードのカソードに接続されている。そして、複数の信号電極１２ｄ、１４ｄの一つは、ＩＧＢＴのゲートに接続されている。なお、他の実施形態として、第１半導体素子１２及び／又は第２半導体素子１４は、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）であってもよい。この場合、第１主電極１２ｂ、１４ｂは、ＭＯＳＦＥＴのソースに接続され、第２主電極１２ｃ、１４ｃは、ＭＯＳＦＥＴのドレインに接続される。そして、複数の信号電極１２ｄ、１４ｄの一つは、ＭＯＳＦＥＴのゲートに接続される。 As an example, as shown in FIG. 4, each semiconductor element 12, 14 in this embodiment is an RC (Reverse Conducting)-IGBT in which an IGBT (Insulated Gate Bipolar Transistor) and a diode are integrated. The first main electrodes 12b, 14b are connected to the emitter of the IGBT and the anode of the diode, and the second main electrodes 12c, 14c are connected to the collector of the IGBT and the cathode of the diode. One of the plurality of signal electrodes 12d and 14d is connected to the gate of the IGBT. As another embodiment, the first semiconductor element 12 and/or the second semiconductor element 14 may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In this case, the first main electrode 12b, 14b is connected to the source of the MOSFET and the second main electrode 12c, 14c is connected to the drain of the MOSFET. One of the plurality of signal electrodes 12d and 14d is connected to the gate of the MOSFET.

複数の導電板１６、１８、２０は、上側導電板１６、中間導電板２０及び下側導電板１８を含む。各々の導電板１６、２０、１８は、少なくとも部分的に導電性を有する板状の部材である。三つの導電板１６、２０、１８は積層配置されており、それらの間に複数の半導体素子１２、１４が配置されている。即ち、第１半導体素子１２は、上側導電板１６と中間導電板２０との間に位置しており、上側導電板１６と中間導電板２０とのそれぞれに電気的に接続されている。第２半導体素子１４は、中間導電板２０と下側導電板１８との間に位置しており、中間導電板２０と下側導電板１８とのそれぞれに電気的に接続されている。なお、上側導電板１６と中間導電板２０との間には、二以上の第１半導体素子１２が設けられてもよい。この場合、二以上の第１半導体素子１２は、同じ種類（即ち、同じ構造）の半導体素子であってもよいし、互いに異なる種類（即ち、異なる構造）の半導体素子であってもよい。同様に、中間導電板２０と下側導電板１８との間には、二以上の同じ種類又は異なる種類の第２半導体素子１４が設けられてもよい。 The plurality of conductive plates 16 , 18 , 20 includes upper conductive plate 16 , intermediate conductive plate 20 and lower conductive plate 18 . Each conductive plate 16, 20, 18 is a plate-like member that is at least partially conductive. Three conductive plates 16, 20, 18 are arranged in a stack, with a plurality of semiconductor elements 12, 14 arranged therebetween. That is, the first semiconductor element 12 is positioned between the upper conductive plate 16 and the intermediate conductive plate 20 and is electrically connected to the upper conductive plate 16 and the intermediate conductive plate 20, respectively. The second semiconductor element 14 is positioned between the intermediate conductive plate 20 and the lower conductive plate 18 and is electrically connected to the intermediate conductive plate 20 and the lower conductive plate 18, respectively. Two or more first semiconductor elements 12 may be provided between the upper conductive plate 16 and the intermediate conductive plate 20 . In this case, the two or more first semiconductor elements 12 may be semiconductor elements of the same type (ie, same structure) or semiconductor elements of different types (ie, different structures). Similarly, two or more second semiconductor elements 14 of the same type or different types may be provided between the intermediate conductive plate 20 and the lower conductive plate 18 .

上側導電板１６と下側導電板１８は金属板であり、例えば銅といった金属で構成されている。上側導電板１６は、接合層５２を介して、第１半導体素子１２の第２主電極１２ｃに接合されている。接合層５２は、例えばはんだ層であって、上側導電板１６と第１半導体素子１２との間を電気的に、かつ熱的に接続する。上側導電板１６は、封止体３０の上面３０ａに露出している。従って、上側導電板１６は、第１半導体素子１２に接続された電気回路の一部を構成するだけでなく、第１半導体素子１２の熱を外部へ放出する放熱板としても機能する。下側導電板１８は、接合層６２を介して、第２半導体素子１４の第２主電極１４ｃに接合されている。この接合層６２も、例えばはんだ層であって、下側導電板１８と第２半導体素子１４との間を電気的に、かつ熱的に接続する。下側導電板１８は、封止体３０の下面３０ｂに露出している。従って、下側導電板１８は、第２半導体素子１４に接続された電気回路の一部を構成するだけでなく、第２半導体素子１４の熱を外部へ放出する放熱板としても機能する。 The upper conductive plate 16 and the lower conductive plate 18 are metal plates made of metal such as copper. The upper conductive plate 16 is bonded to the second main electrode 12c of the first semiconductor element 12 via the bonding layer 52 . The bonding layer 52 is, for example, a solder layer, and electrically and thermally connects between the upper conductive plate 16 and the first semiconductor element 12 . The upper conductive plate 16 is exposed on the upper surface 30 a of the sealing body 30 . Therefore, the upper conductive plate 16 not only constitutes a part of the electric circuit connected to the first semiconductor element 12, but also functions as a heat sink for releasing the heat of the first semiconductor element 12 to the outside. The lower conductive plate 18 is bonded to the second main electrode 14c of the second semiconductor element 14 via the bonding layer 62 . This bonding layer 62 is also a solder layer, for example, and electrically and thermally connects between the lower conductive plate 18 and the second semiconductor element 14 . The lower conductive plate 18 is exposed on the lower surface 30 b of the sealing body 30 . Therefore, the lower conductive plate 18 not only constitutes a part of the electric circuit connected to the second semiconductor element 14, but also functions as a heat sink for releasing the heat of the second semiconductor element 14 to the outside.

中間導電板２０は、絶縁体基板２２と、第１金属層２４と、第２金属層２６とを含む積層構造を有する。絶縁体基板２２は、絶縁体で構成された基板であり、例えばセラミック基板であってもよい。第１金属層２４は、例えば銅といった金属で構成されており、絶縁体基板２２の上面に設けられている。第２金属層２６も、例えば銅といった金属で構成されており、絶縁体基板２２の下面に設けられている。第１金属層２４は、第１半導体素子１２と電気的に接続されており、第２金属層２６は、第２半導体素子１４と電気的に接続されている。中間導電板２０は、特に限定されないが、ＤＢＣ（Direct Bonded Cupper）基板、ＤＢＡ（Direct Bonded Aluminum）、ＡＭＣ（Active Metal Brazed Cupper）基板であってもよい。 The intermediate conductive plate 20 has a laminate structure including an insulator substrate 22 , a first metal layer 24 and a second metal layer 26 . The insulator substrate 22 is a substrate made of an insulator, and may be, for example, a ceramic substrate. The first metal layer 24 is made of metal such as copper, and is provided on the upper surface of the insulator substrate 22 . The second metal layer 26 is also made of metal such as copper, and is provided on the lower surface of the insulator substrate 22 . The first metal layer 24 is electrically connected to the first semiconductor element 12 and the second metal layer 26 is electrically connected to the second semiconductor element 14 . The intermediate conductive plate 20 is not particularly limited, but may be a DBC (Direct Bonded Cupper) substrate, a DBA (Direct Bonded Aluminum) substrate, or an AMC (Active Metal Brazed Cupper) substrate.

中間導電板２０の第１金属層２４は、第１主回路部２４ａと、複数の第１信号回路部２４ｂとを有する。第１主回路部２４ａと複数の第１信号回路部２４ｂは、互いに分離されており、互いに電気的に絶縁されている。第１主回路部２４ａは、接合層５０を介して、第１半導体素子１２の第１主電極１２ｂに接合されている。接合層５０は、例えばはんだ層であって、第１主回路部２４ａと第１半導体素子１２の第１主電極１２ｂとの間を電気的に、かつ熱的に接続している。複数の第１信号回路部２４ｂは、接合層５４を介して、第１半導体素子１２の複数の信号電極１２ｄにそれぞれ接合されている。これらの接合層５４も、例えばはんだ層であって、複数の第１信号回路部２４ｂと第１半導体素子１２の複数の信号電極１２ｄとの間を電気的に、かつ熱的に接続している。 The first metal layer 24 of the intermediate conductive plate 20 has a first main circuit portion 24a and a plurality of first signal circuit portions 24b. The first main circuit section 24a and the plurality of first signal circuit sections 24b are separated from each other and electrically insulated from each other. The first main circuit section 24a is joined to the first main electrode 12b of the first semiconductor element 12 via the joining layer 50 . The bonding layer 50 is, for example, a solder layer, and electrically and thermally connects the first main circuit section 24 a and the first main electrode 12 b of the first semiconductor element 12 . The plurality of first signal circuit portions 24b are bonded to the plurality of signal electrodes 12d of the first semiconductor element 12 via bonding layers 54, respectively. These bonding layers 54 are also solder layers, for example, and electrically and thermally connect between the plurality of first signal circuit portions 24b and the plurality of signal electrodes 12d of the first semiconductor element 12. .

同様に、中間導電板２０の第２金属層２６は、第２主回路部２６ａと、複数の第２信号回路部２６ｂとを有する。第２主回路部２６ａと複数の第２信号回路部２６ｂは、互いに分離されており、互いに電気的に絶縁されている。を有する第２主回路部２６ａは、接合層６０を介して、第２半導体素子１４の第１主電極１４ｂに接合されている。接合層６０は、例えばはんだ層であって、第２主回路部２６ａと第２半導体素子１４の第１主電極１４ｂとの間を電気的に、かつ熱的に接続している。複数の第２信号回路部２６ｂは、接合層６４を介して、第１半導体素子１２の複数の信号電極１２ｄにそれぞれ接合されている。これらの接合層６４も、例えばはんだ層であって、複数の第２信号回路部２６ｂと第２半導体素子１４の複数の信号電極１４ｄとの間を電気的に、かつ熱的に接続している。 Similarly, the second metal layer 26 of the intermediate conductive plate 20 has a second main circuit portion 26a and a plurality of second signal circuit portions 26b. The second main circuit section 26a and the plurality of second signal circuit sections 26b are separated from each other and electrically insulated from each other. is bonded to the first main electrode 14b of the second semiconductor element 14 via the bonding layer 60 . The bonding layer 60 is, for example, a solder layer, and electrically and thermally connects the second main circuit section 26a and the first main electrode 14b of the second semiconductor element 14 to each other. The plurality of second signal circuit portions 26b are bonded to the plurality of signal electrodes 12d of the first semiconductor element 12 via bonding layers 64, respectively. These bonding layers 64 are also solder layers, for example, and electrically and thermally connect between the plurality of second signal circuit portions 26b and the plurality of signal electrodes 14d of the second semiconductor element 14. .

半導体装置１０は、複数の電力端子３２、３４、３６、３８と、複数の信号端子４０、４２とを備える。これらの端子３２、３４、３６、３８、４０、４２は、特に限定されないが、銅といった金属で構成されている。複数の電力端子３２、３４、３６、３８は、封止体３０の第２端面３０ｄから突出している。複数の信号端子４０、４２は、封止体３０の第１端面３０ｃから突出している。但し、これらの端子３２、３４、３６、３８、４０、４２の位置や形状といった具体的な構造は、特に限定されない。 The semiconductor device 10 includes multiple power terminals 32 , 34 , 36 , 38 and multiple signal terminals 40 , 42 . These terminals 32 , 34 , 36 , 38 , 40 , 42 are made of metal such as copper, although not particularly limited. A plurality of power terminals 32 , 34 , 36 , 38 protrude from the second end surface 30 d of the encapsulant 30 . A plurality of signal terminals 40 and 42 protrude from the first end surface 30 c of the sealing body 30 . However, the specific structures such as the positions and shapes of these terminals 32, 34, 36, 38, 40, and 42 are not particularly limited.

複数の電力端子３２、３４、３６、３８には、第１電力端子３２、第２電力端子３４、第３電力端子３６及び第４電力端子３８が含まれる。第１電力端子３２は、封止体３０の内部において、上側導電板１６と電気的に接続されている。これにより、第１半導体素子１２の第２主電極１２ｃは、上側導電板１６を介して第１電力端子３２と電気的に接続されている。特に限定されないが、第１電力端子３２は、上側導電板１６と一体に形成されてもよい。第２電力端子３４は、封止体３０の内部において、中間導電板２０の第１金属層２４の第１主回路部２４ａと電気的に接続されている。これにより、第１半導体素子１２の第１主電極１２ｂは、中間導電板２０の第１主回路部２４ａを介して、第２電力端子３４と電気的に接続されている。特に限定されないが、第２電力端子３４は、例えばはんだ層といった接合層５６を介して、第１主回路部２４ａに接合されてもよい。 The plurality of power terminals 32 , 34 , 36 , 38 includes a first power terminal 32 , a second power terminal 34 , a third power terminal 36 and a fourth power terminal 38 . The first power terminal 32 is electrically connected to the upper conductive plate 16 inside the encapsulant 30 . Thereby, the second main electrode 12 c of the first semiconductor element 12 is electrically connected to the first power terminal 32 via the upper conductive plate 16 . Although not particularly limited, the first power terminal 32 may be formed integrally with the upper conductive plate 16 . The second power terminal 34 is electrically connected to the first main circuit portion 24 a of the first metal layer 24 of the intermediate conductive plate 20 inside the sealing body 30 . Thereby, the first main electrode 12b of the first semiconductor element 12 is electrically connected to the second power terminal 34 via the first main circuit portion 24a of the intermediate conductive plate 20. As shown in FIG. Although not particularly limited, the second power terminal 34 may be joined to the first main circuit section 24a via a joining layer 56 such as a solder layer.

第３電力端子３６は、封止体３０の内部において、中間導電板２０の第２金属層２６の第２主回路部２６ａと電気的に接続されている。これにより、第２半導体素子１４の第１主電極１４ｂは、中間導電板２０の第２主回路部２６ａを介して、第３電力端子３６と電気的に接続されている。特に限定されないが、第３電力端子３６は、例えばはんだ層といった接合層６６を介して、第２主回路部２６ａに接合されてもよい。第４電力端子３８は、封止体３０の内部において、下側導電板１８と電気的に接続されている。これにより、第２半導体素子１４の第２主電極１４ｃは、下側導電板１８を介して第４電力端子３８と電気的に接続されている。特に限定されないが、第４電力端子３８は、下側導電板１８と一体に形成されてもよい。 The third power terminal 36 is electrically connected to the second main circuit portion 26 a of the second metal layer 26 of the intermediate conductive plate 20 inside the sealing body 30 . Thus, the first main electrode 14b of the second semiconductor element 14 is electrically connected to the third power terminal 36 via the second main circuit section 26a of the intermediate conductive plate 20. As shown in FIG. Although not particularly limited, the third power terminal 36 may be joined to the second main circuit section 26a via a joining layer 66 such as a solder layer. The fourth power terminal 38 is electrically connected to the lower conductive plate 18 inside the encapsulant 30 . Thereby, the second main electrode 14 c of the second semiconductor element 14 is electrically connected to the fourth power terminal 38 via the lower conductive plate 18 . Although not particularly limited, the fourth power terminal 38 may be formed integrally with the lower conductive plate 18 .

複数の信号端子４０、４２には、複数の第１信号端子４０と複数の第２信号端子４２が含まれる。複数の第１信号端子４０は、封止体３０の内部において、中間導電板２０の第１金属層２４の複数の第１信号回路部２４ｂとそれぞれ電気的に接続されている。これにより、第１半導体素子１２の各々の信号電極１２ｄは、第１信号回路部２４ｂを介して、対応する一つの第１信号端子４０と電気的に接続されている。特に限定されないが、複数の第１信号端子４０は、例えばはんだ層といった接合層５８を介して、複数の第１信号回路部２４ｂとそれぞれ接合されてもよい。同様に、複数の第２信号端子４２は、封止体３０の内部において、中間導電板２０の第２金属層２６の複数の第２信号回路部２６ｂとそれぞれ電気的に接続されている。これにより、第２半導体素子１４の各々の信号電極１４ｄは、第２信号回路部２６ｂを介して、対応する一つの第２信号端子４２と電気的に接続されている。特に限定されないが、複数の第２信号端子４２についても、例えばはんだ層といった接合層６８を介して、複数の第２信号回路部２６ｂとそれぞれ接合されてもよい。 The plurality of signal terminals 40 , 42 includes a plurality of first signal terminals 40 and a plurality of second signal terminals 42 . The plurality of first signal terminals 40 are electrically connected to the plurality of first signal circuit portions 24b of the first metal layer 24 of the intermediate conductive plate 20 inside the sealing body 30, respectively. Thus, each signal electrode 12d of the first semiconductor element 12 is electrically connected to one corresponding first signal terminal 40 via the first signal circuit portion 24b. Although not particularly limited, the plurality of first signal terminals 40 may be bonded to the plurality of first signal circuit portions 24b via a bonding layer 58 such as a solder layer. Similarly, the plurality of second signal terminals 42 are electrically connected to the plurality of second signal circuit portions 26b of the second metal layer 26 of the intermediate conductive plate 20 inside the sealing body 30, respectively. Thereby, each signal electrode 14d of the second semiconductor element 14 is electrically connected to one corresponding second signal terminal 42 via the second signal circuit portion 26b. Although not particularly limited, the plurality of second signal terminals 42 may also be joined to the plurality of second signal circuit portions 26b via a joining layer 68 such as a solder layer, for example.

以上の構成により、本実施例の半導体装置１０は、コンバータやインバータといった電力変換回路に組み込まれ、電流を導通及び遮断するスイッチング回路を構成することができる。このとき、第２電力端子３４と第４電力端子３８とを互いに接続すると、第１半導体素子１２と第２半導体素子１４とを直列に接続することができる。あるいは、第１電力端子３２と第４電力端子３８とを互いに接続するとともに、第２電力端子３４と第３電力端子３６とを互いに接続すると、第１半導体素子１２と第２半導体素子１４とを並列に接続することができる。 With the configuration described above, the semiconductor device 10 of the present embodiment can be incorporated in a power conversion circuit such as a converter or an inverter to form a switching circuit that conducts and interrupts current. At this time, by connecting the second power terminal 34 and the fourth power terminal 38 to each other, the first semiconductor element 12 and the second semiconductor element 14 can be connected in series. Alternatively, when the first power terminal 32 and the fourth power terminal 38 are connected to each other, and the second power terminal 34 and the third power terminal 36 are connected to each other, the first semiconductor element 12 and the second semiconductor element 14 are connected. Can be connected in parallel.

第１半導体素子１２及び第２半導体素子１４に電流が流れると、第１半導体素子１２及び第２半導体素子１４がそれぞれ発熱する。第１半導体素子１２及び第２半導体素子１４が発熱すると、それらに隣接する三つの導電板１６、１８、２０の温度も上昇して、各々の導電板１６、１８、２０には熱膨張が生じる。特に、第１半導体素子１２と第２半導体素子１４との間に位置する中間導電板２０は、上側導電板１６及び下側導電板１８よりも高温となりやすい。 When a current flows through the first semiconductor element 12 and the second semiconductor element 14, the first semiconductor element 12 and the second semiconductor element 14 generate heat. When the first semiconductor element 12 and the second semiconductor element 14 generate heat, the temperature of the three conductive plates 16, 18, 20 adjacent to them also rises, and thermal expansion occurs in each of the conductive plates 16, 18, 20. . In particular, the intermediate conductive plate 20 located between the first semiconductor element 12 and the second semiconductor element 14 tends to be hotter than the upper conductive plate 16 and the lower conductive plate 18 .

そのことから、本実施例の半導体装置１０では、上側導電板１６及び下側導電板１８が金属板であるのに対して、中間導電板２０は絶縁体基板２２を含む積層構造を有している。絶縁体基板２２は例えばセラミック基板であり、絶縁体基板２２を構成する材料は、第１金属層２４を構成する材料や第２金属層２６を構成する材料よりも線膨張係数が小さい。これにより、中間導電板２０の面内方向における線膨張係数は、上側導電板１６の面内方向における線膨張係数及び下側導電板１８の面内方向における線膨張係数よりも小さくなっている。従って、中間導電板２０の温度が、上側導電板１６の温度及び下側導電板１８の温度よりも高温となったときでも、三つの導電板１６、１８、２０に不均一な熱膨張が生じることが抑制される。 Therefore, in the semiconductor device 10 of this embodiment, the upper conductive plate 16 and the lower conductive plate 18 are metal plates, while the intermediate conductive plate 20 has a laminated structure including the insulator substrate 22. there is The insulator substrate 22 is, for example, a ceramic substrate, and the material forming the insulator substrate 22 has a smaller coefficient of linear expansion than the material forming the first metal layer 24 and the material forming the second metal layer 26 . As a result, the in-plane linear expansion coefficient of the intermediate conductive plate 20 is smaller than the in-plane linear expansion coefficient of the upper conductive plate 16 and the in-plane linear expansion coefficient of the lower conductive plate 18 . Therefore, even when the temperature of the intermediate conductive plate 20 becomes higher than the temperature of the upper conductive plate 16 and the temperature of the lower conductive plate 18, uneven thermal expansion occurs in the three conductive plates 16, 18, 20. is suppressed.

ここで、中間導電板２０は、絶縁体基板２２を含む積層構造に限定されず、その構造や材料は適宜変更することができる。上側導電板１６及び下側導電板１８もまた、金属板に限定されず、その構造や材料は適宜変更することができる。中間導電板２０の面内方向における線膨張係数が、上側導電板１６の面内方向における線膨張係数及び下側導電板１８の面内方向における線膨張係数よりも小さくなる限りにおいて、三つの導電板１６、１８、２０の構造や材料は、様々に変更することができる。 Here, the intermediate conductive plate 20 is not limited to a laminated structure including the insulator substrate 22, and its structure and materials can be changed as appropriate. The upper conductive plate 16 and the lower conductive plate 18 are also not limited to metal plates, and their structures and materials can be changed as appropriate. As long as the coefficient of linear expansion in the in-plane direction of the intermediate conductive plate 20 is smaller than the coefficient of linear expansion in the in-plane direction of the upper conductive plate 16 and the coefficient of linear expansion in the in-plane direction of the lower conductive plate 18, the three conductors The construction and materials of the plates 16, 18, 20 can vary.

本実施例の半導体装置１０では、中間導電板２０の面積が、上側導電板１６の面積及び下側導電板１８の面積よりも小さい。言い換えると、上側導電板１６の面積及び下側導電板１８の面積は、中間導電板２０の面積より大きい。前述したように、上側導電板１６及び下側導電板１８は、封止体３０の上面３０ａ又は下面３０ｂに露出しており、放熱板として機能する。そのことから、上側導電板１６の面積及び下側導電板１８の面積が大きいと、各々の半導体素子１２、１４の熱が、上側導電板１６及び下側導電板１８を介して半導体装置１０の外部へ効率よく放出される。しかしながら、図５に示すように、一変形例の半導体装置１０’では、中間導電板２０の面積が、上側導電板１６の面積及び下側導電板１８の面積よりも大きくてもよい。このような構成によると、中間導電板２０の熱容量が大きくなるので、中間導電板２０の温度上昇を抑制することができる。 In the semiconductor device 10 of this embodiment, the area of the intermediate conductive plate 20 is smaller than the area of the upper conductive plate 16 and the area of the lower conductive plate 18 . In other words, the area of upper conductive plate 16 and the area of lower conductive plate 18 are greater than the area of intermediate conductive plate 20 . As described above, the upper conductive plate 16 and the lower conductive plate 18 are exposed on the upper surface 30a or the lower surface 30b of the sealing body 30 and function as heat sinks. Therefore, when the area of the upper conductive plate 16 and the area of the lower conductive plate 18 are large, the heat of the respective semiconductor elements 12 and 14 is transferred to the semiconductor device 10 via the upper conductive plate 16 and the lower conductive plate 18. Efficiently released to the outside. However, as shown in FIG. 5 , in a modified semiconductor device 10 ′, the area of the intermediate conductive plate 20 may be larger than the area of the upper conductive plate 16 and the lower conductive plate 18 . With such a configuration, the heat capacity of the intermediate conductive plate 20 is increased, so that the temperature rise of the intermediate conductive plate 20 can be suppressed.

本実施例の半導体装置１０では、第１半導体素子１２と第２半導体素子１４との両方が、第１主電極１２ｂ、１４ｂにおいて、中間導電板２０と電気的に接続されており、第２主電極１２ｃ、１４ｃにおいて、上側導電板１６又は下側導電板１８と電気的に接続されている。前述したように、第２主電極１２ｃ、１４ｃの面積は、第１主電極１２ｂ、１４ｂの面積よりも大きい。従って、各々の半導体素子１２、１４は、第１主電極１２ｂ、１４ｂよりも第２主電極１２ｃ、１４ｃを介して、より多く熱を外部へ放出する。そして、中間導電板２０は、第１半導体素子１２と第２半導体素子１４との両者から熱を受け取るので、その温度が上昇し易い。そのことから、第１半導体素子１２と第２半導体素子１４との両方が、放熱量の少ない第１主電極１２ｂ、１４ｂにおいて中間導電板２０に接続されていると、中間導電板２０の温度上昇を抑制することができる。なお、図６に示す一変形例の半導体装置１０’’のように、第２半導体素子１４（又は第１半導体素子１２）のみが、第１主電極１２ｂ、１４ｂにおいて中間導電板２０に接続されていてもよい。 In the semiconductor device 10 of this embodiment, both the first semiconductor element 12 and the second semiconductor element 14 are electrically connected to the intermediate conductive plate 20 at the first main electrodes 12b, 14b, The electrodes 12c, 14c are electrically connected to the upper conductive plate 16 or the lower conductive plate 18, respectively. As described above, the areas of the second main electrodes 12c, 14c are larger than the areas of the first main electrodes 12b, 14b. Therefore, each of the semiconductor elements 12, 14 emits more heat to the outside through the second main electrodes 12c, 14c than through the first main electrodes 12b, 14b. Since the intermediate conductive plate 20 receives heat from both the first semiconductor element 12 and the second semiconductor element 14, its temperature is likely to rise. Therefore, if both the first semiconductor element 12 and the second semiconductor element 14 are connected to the intermediate conductive plate 20 at the first main electrodes 12b, 14b with less heat dissipation, the temperature of the intermediate conductive plate 20 will rise. can be suppressed. 6, only the second semiconductor element 14 (or the first semiconductor element 12) is connected to the intermediate conductive plate 20 at the first main electrodes 12b, 14b. may be

（実施例２） 図７－図９を参照して、実施例２の半導体装置１０Ａを説明する。本実施例の半導体装置１０Ａは、二つの継手部材７０をさらに備えており、この点において実施例１の半導体装置１０と相違する。また、本実施例の半導体装置１０Ａは、第２電力端子３４を有しておらず、この点においても実施例１の半導体装置１０と相違する。本実施例の半導体装置１０Ａの他の構成については、実施例１の半導体装置１０と共通又は対応している。従って、図７－図９では、実施例１の半導体装置１０と共通又は対応する構成に同一の符号が付されており、ここでは重複する説明を省略する。 Example 2 A semiconductor device 10A of Example 2 will be described with reference to FIGS. 7 to 9. FIG. The semiconductor device 10A of the present embodiment further includes two joint members 70, and differs from the semiconductor device 10 of the first embodiment in this respect. Further, the semiconductor device 10A of the present embodiment does not have the second power terminal 34, and is different from the semiconductor device 10 of the first embodiment in this respect as well. Other configurations of the semiconductor device 10A of this embodiment are common to or correspond to those of the semiconductor device 10 of the first embodiment. Therefore, in FIGS. 7 to 9, the same reference numerals are given to the configurations that are common or correspond to those of the semiconductor device 10 of the first embodiment, and overlapping explanations are omitted here.

各々の継手部材７０は、封止体３０の内部に位置しており、金属といった導電体で構成されている。継手部材７０の一端は、中間導電板２０の第１金属層２４の第１主回路部２４ａに接続されている。継手部材７０の他端は、下側導電板１８に接続されている。これにより、中間導電板２０の第１主回路部２４ａが、各々の継手部材７０を介して、下側導電板１８に電気的に接続されている。このような構成によると、図９に示すように、第１半導体素子１２と第２半導体素子１４を、封止体３０の内部で直列に接続することができる。従って、第２電力端子３４が省略されている。なお、第２電力端子３４に代えて、第４電力端子３８を省略してもよい。 Each joint member 70 is positioned inside the sealing body 30 and is made of a conductor such as metal. One end of the joint member 70 is connected to the first main circuit portion 24 a of the first metal layer 24 of the intermediate conductive plate 20 . The other end of the joint member 70 is connected to the lower conductive plate 18 . Thereby, the first main circuit portion 24 a of the intermediate conductive plate 20 is electrically connected to the lower conductive plate 18 via each joint member 70 . According to such a configuration, as shown in FIG. 9, the first semiconductor element 12 and the second semiconductor element 14 can be connected in series inside the sealing body 30 . Therefore, the second power terminal 34 is omitted. Note that the fourth power terminal 38 may be omitted instead of the second power terminal 34 .

本実施例の半導体装置１０Ａは、二つの継手部材７０を備えるが、継手部材７０の数は二つに限定されない。半導体装置１０Ａは、単一の、又は三つ以上の継手部材７０を備えてもよい。また、継手部材７０による接続箇所を変更することによって、第１半導体素子１２と第２半導体素子１４を、封止体３０の内部で並列に接続してもよい。 The semiconductor device 10A of this embodiment includes two joint members 70, but the number of joint members 70 is not limited to two. The semiconductor device 10A may include a single joint member or three or more joint members 70 . Alternatively, the first semiconductor element 12 and the second semiconductor element 14 may be connected in parallel inside the sealing body 30 by changing the connection location of the joint member 70 .

以上、本明細書が開示する技術の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書、又は、図面に説明した技術要素は、単独で、あるいは各種の組合せによって技術的有用性を発揮するものであり、出願時の請求項に記載の組合せに限定されるものではない。本明細書又は図面に例示した技術は、複数の目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Although specific examples of the technology disclosed in this specification have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims as filed. The techniques exemplified in this specification or drawings can achieve a plurality of purposes at the same time, and achieving one of them has technical utility in itself.

１０：半導体装置
１２：第１半導体素子
１４：第２半導体素子
１６：上側導電板
１８：下側導電板
２０；中間導電板
２２：中間導電板の絶縁体基板
２４：中間導電板の第１金属層
２４ａ：第１金属層の第１主回路部
２４ｂ：第１金属層の第１信号回路部
２６：中間導電板の第２金属層
２６ａ：第１金属層の第１主回路部
２６ｂ：第１金属層の第１信号回路部
３０：封止体
３２、３４、３６、３８：電力端子
４０、４２：信号端子
７０：継手部材 10: Semiconductor Device 12: First Semiconductor Element 14: Second Semiconductor Element 16: Upper Conductive Plate 18: Lower Conductive Plate 20; Intermediate Conductive Plate 22: Insulator Substrate of Intermediate Conductive Plate 24: First Metal of Intermediate Conductive Plate Layer 24a: first main circuit portion 24b of first metal layer: first signal circuit portion 26 of first metal layer: second metal layer 26a of intermediate conductive plate: first main circuit portion 26b of first metal layer: second First signal circuit part 30 of one metal layer: sealing bodies 32, 34, 36, 38: power terminals 40, 42: signal terminals 70: joint members

Claims (10)

積層配置された上側導電板、中間導電板及び下側導電板と、
前記上側導電板と前記中間導電板との間に位置しており、前記上側導電板と前記中間導電板とのそれぞれに電気的に接続された第１半導体素子と、
前記中間導電板と前記下側導電板との間に位置しており、前記中間導電板と前記下側導電板とのそれぞれに電気的に接続された第２半導体素子と、
前記第１半導体素子及び前記第２半導体素子を封止するとともに、前記上側導電板、前記中間導電板及び前記下側導電板を一体に保持する封止体と、
前記封止体の内部に位置するとともに、前記第１半導体素子と前記第２半導体素子とを電気的に接続する継手部材と、
を備え、
前記中間導電板の面内方向における線膨張係数は、前記上側導電板の面内方向における線膨張係数及び前記下側導電板の面内方向における線膨張係数よりも小さく、
前記中間導電板は、絶縁体基板と、前記絶縁体基板の上面に設けられているとともに前記第１半導体素子と電気的に接続された第１金属層と、前記絶縁体基板の下面に設けられているとともに前記第２半導体素子と電気的に接続された第２金属層とを有し、
前記継手部材の一端は前記中間導電板の前記第１金属層に接続されており、前記継手部材の他端は前記下側導電板に接続されている、
半導体装置。 an upper conductive plate, an intermediate conductive plate, and a lower conductive plate that are laminated;
a first semiconductor element positioned between the upper conductive plate and the intermediate conductive plate and electrically connected to each of the upper conductive plate and the intermediate conductive plate;
a second semiconductor element positioned between the intermediate conductive plate and the lower conductive plate and electrically connected to each of the intermediate conductive plate and the lower conductive plate;
a sealing body that seals the first semiconductor element and the second semiconductor element and integrally holds the upper conductive plate, the intermediate conductive plate, and the lower conductive plate;
a joint member located inside the sealing body and electrically connecting the first semiconductor element and the second semiconductor element;
with
the coefficient of linear expansion in the in-plane direction of the intermediate conductive plate is smaller than the coefficient of linear expansion in the in-plane direction of the upper conductive plate and the coefficient of linear expansion in the in-plane direction of the lower conductive plate;
The intermediate conductive plate includes an insulator substrate, a first metal layer provided on an upper surface of the insulator substrate and electrically connected to the first semiconductor element, and an undersurface of the insulator substrate. and a second metal layer electrically connected to the second semiconductor element,
one end of the joint member is connected to the first metal layer of the intermediate conductive plate, and the other end of the joint member is connected to the lower conductive plate;
semiconductor equipment. 前記絶縁体基板を構成する絶縁体の線膨張係数は、前記第１金属層を構成する金属の線膨張係数及び前記第２金属層を構成する金属の線膨張係数よりも小さい、請求項１に記載の半導体装置。 2. The method according to claim 1, wherein the linear expansion coefficient of the insulator forming the insulator substrate is smaller than the linear expansion coefficient of the metal forming the first metal layer and the linear expansion coefficient of the metal forming the second metal layer. The semiconductor device described. 前記絶縁体基板は、セラミック基板である、請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1 , wherein said insulator substrate is a ceramic substrate. 前記上側導電板及び前記下側導電板は、金属板である、請求項１から３のいずれか一項に記載の半導体装置。 4. The semiconductor device according to claim 1 , wherein said upper conductive plate and said lower conductive plate are metal plates. 前記第１半導体素子と前記第２半導体素子の各々は、第１主電極と、前記第１主電極よりも面積の大きい第２主電極とを有し、
前記第１半導体素子と前記第２半導体素子の少なくとも一方は、前記第１主電極において前記中間導電板の前記第１金属層又は前記第２金属層と電気的に接続されているとともに、前記第２主電極において前記上側導電板又は前記下側導電板と電気的に接続されている、請求項１から４のいずれか一項に記載の半導体装置。 each of the first semiconductor element and the second semiconductor element has a first main electrode and a second main electrode having an area larger than that of the first main electrode;
At least one of the first semiconductor element and the second semiconductor element is electrically connected to the first metal layer or the second metal layer of the intermediate conductive plate at the first main electrode, 5. The semiconductor device according to claim 1 , wherein two main electrodes are electrically connected to said upper conductive plate or said lower conductive plate. 前記第１半導体素子と前記第２半導体素子の両方は、前記第１主電極において前記中間導電板の前記第１金属層又は前記第２金属層と電気的に接続されているとともに、前記第２主電極において前記上側導電板又は前記下側導電板と電気的に接続されている、請求項５に記載の半導体装置。 Both the first semiconductor element and the second semiconductor element are electrically connected to the first metal layer or the second metal layer of the intermediate conductive plate at the first main electrode. 6. The semiconductor device according to claim 5, wherein a main electrode is electrically connected to said upper conductive plate or said lower conductive plate. 前記第１半導体素子と前記第２半導体素子の各々は、前記第１主電極と同じ側に設けられた信号電極をさらに有し、
前記中間導電板の前記第１金属層は、前記第１半導体素子の前記第１主電極と電気的に接続された第１主回路部と、前記第１主回路部から分離されているとともに、前記第１半導体素子の前記信号電極と電気的に接続された第１信号回路部とを有し、
前記中間導電板の前記第２金属層は、前記第２半導体素子の前記第１主電極と電気的に接続された第２主回路部と、前記第２主回路部から分離されているとともに、前記第２半導体素子の前記信号電極と電気的に接続された第２信号回路部とを有する、
請求項６に記載の半導体装置。 each of the first semiconductor element and the second semiconductor element further has a signal electrode provided on the same side as the first main electrode;
The first metal layer of the intermediate conductive plate is separated from a first main circuit section electrically connected to the first main electrode of the first semiconductor element, and from the first main circuit section, a first signal circuit section electrically connected to the signal electrode of the first semiconductor element;
The second metal layer of the intermediate conductive plate is separated from a second main circuit section electrically connected to the first main electrode of the second semiconductor element, and from the second main circuit section, a second signal circuit section electrically connected to the signal electrode of the second semiconductor element;
7. The semiconductor device according to claim 6. 前記継手部材の前記一端は、前記第１金属層の前記第１主回路部に接続されている、請求項７に記載の半導体装置。8. The semiconductor device according to claim 7, wherein said one end of said joint member is connected to said first main circuit section of said first metal layer. 前記中間導電板の面積は、前記上側導電板の面積及び前記下側導電板の面積よりも小さい、請求項１から８のいずれか一項に記載の半導体装置。 9. The semiconductor device according to claim 1 , wherein the area of said intermediate conductive plate is smaller than the area of said upper conductive plate and the area of said lower conductive plate. 前記中間導電板の面積は、前記上側導電板の面積及び前記下側導電板の面積よりも大きい、請求項１から８のいずれか一項に記載の半導体装置。 9. The semiconductor device according to claim 1 , wherein the area of said intermediate conductive plate is larger than the area of said upper conductive plate and the area of said lower conductive plate.
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