JP2016181573A

JP2016181573A - Wiring board manufacturing method

Info

Publication number: JP2016181573A
Application number: JP2015060282A
Authority: JP
Inventors: 誠中居; Makoto Nakai; 秀洋高山; Hidehiro Takayama
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2015-03-24
Filing date: 2015-03-24
Publication date: 2016-10-13

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board in which wiring conductors provided on both upper and lower surfaces of an insulation layer having a through hole have no dent.SOLUTION: A wiring board manufacturing method comprises: a first step of forming a through hole 2 in an insulation layer 1; a second step of forming a first plating conductor 3 to fill the through hole 2 in the through hole 2 and on upper and lower surfaces of the insulation layer 1 around the through hole; a third step of etching the first plating conductor 3 to remove the first plating conductor 3 on the upper and lower surfaces and leaving the first plating conductor 3 so as to fill a central part of the through hole 2 in a penetrating direction; and a fourth step of forming by a semi-additive method, a second plating conductor 6 which fills portions in the through hole 2 and outside the first plating conductor 3 and forms wiring conductors 7 on the upper and lower surfaces of the insulation layer 1. In the third step, the first plating conductor is etched to leave part of the first plating conductor 3 at a central part of the through hole 2 in a radial direction so as to have projections 3a each projecting from the upper or lower surfaces of the insulation layer 1.SELECTED DRAWING: Figure 1

Description

本発明は、配線基板の製造方法に関するものである。 The present invention relates to a method for manufacturing a wiring board.

従来、薄型の配線基板として、薄い絶縁層に例えばテーパ状の複数の貫通孔を設け、これらの貫通孔内をめっき導体で充填するとともに絶縁層の上下面にめっき導体から成る配線導体を形成した配線基板が知られている。 Conventionally, as a thin wiring board, for example, a plurality of tapered through holes are provided in a thin insulating layer, the insides of these through holes are filled with plated conductors, and wiring conductors made of plated conductors are formed on the upper and lower surfaces of the insulating layer. A wiring board is known.

このような配線基板において、絶縁層の上下面に高密度配線を形成する従来の配線基板の製造方法を図２（ａ）〜（ｅ）を基にして説明する。まず、図２（ａ）に示すように、絶縁層１１に貫通孔１２を形成する。次に図２（ｂ）に示すように、貫通孔１２内および絶縁層１１の上下面に第１のめっき導体１３を析出させる。これにより、貫通孔１２の内部を第１のめっき導体１３で完全に充填するとともに、絶縁層１１の上下面に第１のめっき導体１３を被着する。次に、図２（ｃ）に示すように、第１のめっき導体１３をエッチングする。これにより、絶縁層１１上下面の第１のめっき導体１３を除去するとともに、貫通孔１２の中央部を充填するようにして第１のめっき導体１３を残す。このとき、貫通孔１２内に残った第１のめっき導体１３は、その上下端が絶縁層１１の上下面から凹んだ状態となる。次に、図２（ｄ）に示すように、絶縁層１１の上下面にめっきレジスト１４を形成するとともに、めっきレジスト１４から露出する絶縁層１１の表面および第１のめっき導体１３の表面に第２のめっき導体１５を析出させる。これにより貫通孔１２内が完全に充填されるとともに、絶縁層１１の上下面に配線導体１６のパターンが形成される。最後に図２（ｅ）に示すように、めっきレジスト１４を除去することにより、貫通孔１２内部が第１のめっき導体１３および第２のめっき導体１５で充填されているとともに絶縁層１１の上下面に第２のめっき導体１５から成る配線導体１６を有する配線基板が完成する。 In such a wiring board, a conventional method of manufacturing a wiring board in which high-density wiring is formed on the upper and lower surfaces of the insulating layer will be described with reference to FIGS. First, as shown in FIG. 2A, the through hole 12 is formed in the insulating layer 11. Next, as shown in FIG. 2B, first plated conductors 13 are deposited in the through holes 12 and on the upper and lower surfaces of the insulating layer 11. Thereby, the inside of the through hole 12 is completely filled with the first plating conductor 13, and the first plating conductor 13 is attached to the upper and lower surfaces of the insulating layer 11. Next, as shown in FIG. 2C, the first plated conductor 13 is etched. As a result, the first plated conductors 13 on the upper and lower surfaces of the insulating layer 11 are removed, and the first plated conductors 13 are left so as to fill the central portion of the through holes 12. At this time, the upper and lower ends of the first plated conductor 13 remaining in the through hole 12 are recessed from the upper and lower surfaces of the insulating layer 11. Next, as shown in FIG. 2D, the plating resist 14 is formed on the upper and lower surfaces of the insulating layer 11, and the surface of the insulating layer 11 exposed from the plating resist 14 and the surface of the first plating conductor 13 are 2 plating conductors 15 are deposited. Thereby, the inside of the through hole 12 is completely filled, and the pattern of the wiring conductor 16 is formed on the upper and lower surfaces of the insulating layer 11. Finally, as shown in FIG. 2 (e), by removing the plating resist 14, the inside of the through hole 12 is filled with the first plating conductor 13 and the second plating conductor 15, and the insulating layer 11 is formed. A wiring board having the wiring conductor 16 composed of the second plating conductor 15 on the lower surface is completed.

しかしながら、この従来の配線基板の製造方法によると、めっきレジスト１４のから露出する絶縁層１１の表面および第１のめっき導体１３の表面に第２のめっき導体１５を析出させる際、貫通孔１２の直上、直下の第２のめっき導体１５に凹みＤが発生することがあった。このような凹みＤは、第１のめっき導体１３をエッチングした際に、貫通孔１２内に残った第１のめっき導体１３の上下端が絶縁層１１の上下面から大きく凹みすぎることに起因する。このような凹みＤが発生した場合、例えばこの凹みＤ上に電子部品を搭載しようとすると、電子部品と配線導体１６とを良好に接続できなくなる。あるいは、配線基板上にさらにビルドアップ絶縁層およびビルドアップ配線導体を形成して多層化しようとする場合に、この凹みＤにより配線導体１６とビルドアップ配線導体とを良好に接続することができなくなる。 However, according to this conventional method of manufacturing a wiring board, when the second plating conductor 15 is deposited on the surface of the insulating layer 11 exposed from the plating resist 14 and the surface of the first plating conductor 13, A dent D may occur in the second plated conductor 15 immediately above and below. Such a recess D is caused by the fact that the upper and lower ends of the first plated conductor 13 remaining in the through hole 12 are greatly recessed from the upper and lower surfaces of the insulating layer 11 when the first plated conductor 13 is etched. . When such a dent D occurs, for example, if an electronic component is to be mounted on the dent D, the electronic component and the wiring conductor 16 cannot be connected well. Alternatively, when the build-up insulating layer and the build-up wiring conductor are further formed on the wiring board to increase the number of layers, the recesses D cannot connect the wiring conductor 16 and the build-up wiring conductor satisfactorily. .

特開２０１２−４４０８１号公報JP 2012-44081 A

本発明は、貫通孔を有する絶縁層の上下面に設けた配線導体に凹みが発生することがなく、電子部品や他のビルドアップ配線導体との接続が良好な配線基板の製造方法を提供することを課題とするものである。 The present invention provides a method for manufacturing a wiring board that is free from dents in wiring conductors provided on the upper and lower surfaces of an insulating layer having a through-hole, and that is well connected to electronic components and other build-up wiring conductors. This is a problem.

本発明の配線基板の製造方法は、上下面を有する絶縁層に前記上下面間を貫通する貫通孔を設ける第１の工程と、少なくとも前記貫通孔内およびその周囲の前記上下面に前記貫通孔を充填する第１のめっき導体を形成する第２の工程と、前記第１のめっき導体をエッチングして前記上下面の前記第１のめっき導体を除去するとともに、少なくとも前記貫通孔の上下方向の中央部を充填するように前記第１のめっき導体を残す第３の工程と、前記貫通孔内の前記第１のめっき導体よりも外側の部分を充填するとともに前記上下面において配線導体を形成する第２のめっき導体をセミアディティブ法により形成する第４工程とを行なう配線基板の製造方法であって、前記第３の工程において、前記第１のめっき導体の一部が前記貫通孔の径方向の中央部において前記上下面から突出する突出部を有して残るようにエッチングすることを特徴とするものである。 The method for manufacturing a wiring board according to the present invention includes a first step of providing a through hole penetrating between the upper and lower surfaces in an insulating layer having upper and lower surfaces, and at least the through holes in the upper and lower surfaces in and around the through holes. A first step of forming a first plating conductor filling the first plating conductor, and removing the first plating conductor on the upper and lower surfaces by etching the first plating conductor, and at least in the vertical direction of the through hole A third step of leaving the first plated conductor so as to fill a central portion; filling a portion outside the first plated conductor in the through hole; and forming a wiring conductor on the upper and lower surfaces. A method of manufacturing a wiring board, comprising: a fourth step of forming a second plated conductor by a semi-additive method, wherein in the third step, a part of the first plated conductor is in a radial direction of the through hole. of It is characterized in that the etching to remain a protrusion protruding from the upper and lower surfaces at the central portion.

本発明の配線基板の製造方法によれば、第１のめっき導体が貫通孔内の上下方向の中央部を充填するとともに径方向の中央部において絶縁層の上下面から突出する突出部を有して残るように第１のめっき導体をエッチングした後、貫通孔内の第１のめっき導体よりも外側の部分を充填するとともに絶縁層の上下面で配線導体を形成する第２のめっき導体をセミアディティブ法により形成することから、絶縁層の上下面から突出する突出部の表面に第２のめっき導体が析出することで、貫通孔の上下端部が第２のめっき導体により良好に充填されるとともに、貫通孔の直上および直下に凹みのない配線導体を形成することができる。したがって、この配線基板上に電子部品を搭載する場合であれば、電子部品と配線導体とを良好に接続することが可能な配線基板を提供することができる。また、この配線基板上にさらにビルドアップ絶縁層およびビルドアップ配線導体を形成して多層化する場合であれば、配線導体とビルドアップ配線導体とを良好に接続することが可能な配線基板を提供することができる。 According to the method for manufacturing a wiring board of the present invention, the first plated conductor has a protrusion that protrudes from the upper and lower surfaces of the insulating layer in the central portion in the radial direction while filling the vertical central portion in the through hole. After etching the first plating conductor so as to remain, the second plating conductor that fills the portion outside the first plating conductor in the through hole and forms the wiring conductor on the upper and lower surfaces of the insulating layer is semi-finished. Since the second plating conductor is deposited on the surface of the protruding portion protruding from the upper and lower surfaces of the insulating layer, the upper and lower end portions of the through hole are satisfactorily filled with the second plating conductor because it is formed by the additive method. In addition, a wiring conductor having no dent can be formed immediately above and below the through hole. Therefore, if an electronic component is mounted on this wiring board, a wiring board capable of satisfactorily connecting the electronic component and the wiring conductor can be provided. In addition, when a build-up insulating layer and a build-up wiring conductor are further formed on the wiring board to form a multilayer, a wiring board capable of satisfactorily connecting the wiring conductor and the build-up wiring conductor is provided. can do.

図１（ａ）〜（ｉ）は、本発明の配線基板の製造方法における実施形態の一例を説明するための工程毎の要部概略断面図である。FIGS. 1A to 1I are main part schematic cross-sectional views for each process for explaining an example of an embodiment in a method for manufacturing a wiring board of the present invention. 図２（ａ）〜（ｅ）は、従来の配線基板の製造方法を説明するための工程毎の要部概略断面図である。2 (a) to 2 (e) are schematic cross-sectional views of main parts for each process for explaining a conventional method for manufacturing a wiring board.

次に、本発明の配線基板の製造方法における実施形態の一例を添付の図１（ａ）〜（ｉ）を基に説明する。なお、図１（ａ）〜（ｉ）は、配線基板となる領域の一部のみを示している。 Next, an example of an embodiment of the method for manufacturing a wiring board according to the present invention will be described with reference to FIGS. 1A to 1I show only a part of a region to be a wiring board.

まず、図１（ａ）に示すように、上面および下面を有する絶縁層１の上面から下面にかけて貫通孔２を形成する。絶縁層１は、例えばガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る。絶縁層１の厚みは１５０〜２５０μｍ程度である。このような絶縁層１は、ガラスクロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて半硬化させたプリプレグの両面に厚みが２〜１８μｍ程度の金属箔を被着させたものを熱硬化させた後、両面の金属箔をエッチング除去することにより得られる。このとき、金属箔の絶縁層１側の面に微細な凹凸を設けておくと、絶縁層１の露出面にも微細な凹凸を形成することができ、それにより絶縁層１の上下面にめっき導体を極めて強固に被着させることができる。 First, as shown in FIG. 1A, a through hole 2 is formed from the upper surface to the lower surface of an insulating layer 1 having an upper surface and a lower surface. The insulating layer 1 is made of, for example, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The thickness of the insulating layer 1 is about 150 to 250 μm. In such an insulating layer 1, a metal foil having a thickness of about 2 to 18 μm was deposited on both surfaces of a prepreg obtained by impregnating a glass cloth with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. It can be obtained by thermosetting the product and then etching away the metal foils on both sides. At this time, if fine irregularities are provided on the surface of the metal foil on the insulating layer 1 side, fine irregularities can be formed on the exposed surface of the insulating layer 1, thereby plating the upper and lower surfaces of the insulating layer 1. The conductor can be deposited very firmly.

貫通孔２は、レーザ加工により形成される。レーザ加工では、貫通孔２におけるレーザの入射側の開口径が出射側の開口径よりも大きくなる。貫通孔２の開口径は、レーザの入射側で８０〜１００μｍ程度、出射側で３０〜６０μｍ程度である。したがって、貫通孔２はテーパ形状となる。貫通孔２がこのようにテーパ形状であると、貫通孔２の内部をめっき導体で良好に充填することが容易となる。なお、貫通孔２を形成した後には、デスミア処理をすることが好ましい。 The through hole 2 is formed by laser processing. In laser processing, the opening diameter on the incident side of the laser in the through hole 2 is larger than the opening diameter on the emission side. The opening diameter of the through hole 2 is about 80 to 100 μm on the laser incident side and about 30 to 60 μm on the emission side. Accordingly, the through hole 2 is tapered. When the through hole 2 has such a tapered shape, it becomes easy to satisfactorily fill the inside of the through hole 2 with a plated conductor. In addition, after forming the through-hole 2, it is preferable to perform a desmear process.

次に、絶縁層１の上下面および貫通孔２内壁に厚みが０．１〜１μｍ程度の薄い無電解めっき層（不図示）を被着させた後、図１（ｂ）に示すように、貫通孔２内および絶縁層１の上下面に電解めっき法により第１のめっき導体３を析出させる。これにより、貫通孔２の内部を第１のめっき導体３で完全に充填するとともに、絶縁層１の上下面に厚みが４０μｍ程度の第１のめっき導体３が被着される。なお、第１のめっき導体３としては、電解銅めっきが好適に用いられる。 Next, after depositing a thin electroless plating layer (not shown) having a thickness of about 0.1 to 1 μm on the upper and lower surfaces of the insulating layer 1 and the inner wall of the through hole 2, as shown in FIG. A first plated conductor 3 is deposited in the through hole 2 and on the upper and lower surfaces of the insulating layer 1 by electrolytic plating. As a result, the inside of the through hole 2 is completely filled with the first plating conductor 3, and the first plating conductor 3 having a thickness of about 40 μm is deposited on the upper and lower surfaces of the insulating layer 1. In addition, as the 1st plating conductor 3, electrolytic copper plating is used suitably.

次に、図１（ｃ）に示すように、第１のめっき導体３をエッチングしてその厚みを薄くする。薄くなった第１のめっき導体３の厚みは、絶縁層１上下面において５〜２０μｍ程度とする。 Next, as shown in FIG. 1C, the first plated conductor 3 is etched to reduce its thickness. The thickness of the thinned first plating conductor 3 is about 5 to 20 μm on the upper and lower surfaces of the insulating layer 1.

次に、図１（ｄ）に示すように、厚みが薄くなった第１のめっき導体３における貫通孔２の直上直下の表面にエッチングレジスト４を形成する。エッチングレジスト４は、貫通孔２よりも直径が０〜４０μｍ程度小さな円形のパターンで構成する。貫通孔２の開口とエッチングレジスト４のパターンとは、その中心同士が互いに１０μｍ以下ずれていてもよい。 Next, as shown in FIG. 1D, an etching resist 4 is formed on the surface immediately below the through hole 2 in the first plated conductor 3 having a reduced thickness. The etching resist 4 is composed of a circular pattern whose diameter is smaller by about 0 to 40 μm than the through hole 2. The center of the opening of the through hole 2 and the pattern of the etching resist 4 may be shifted from each other by 10 μm or less.

次に、図１（ｅ）に示すように、エッチングレジスト４から露出する第１のめっき導体３をエッチングして絶縁層１上下面の第１のめっき導体３を除去する。このとき、第１のめっき導体３が貫通孔２の上下方向の中央部を充填するとともに、その一部が貫通孔２の径方向の中央部において絶縁層１の上下面から突出する突出部３ａを有して残るようにエッチングする。なお、第１のめっき導体３における突起部３ａの周囲は、絶縁層１の上下面から５〜４０μｍ程度凹んだ状態となる。 Next, as shown in FIG. 1E, the first plating conductor 3 exposed from the etching resist 4 is etched to remove the first plating conductor 3 on the upper and lower surfaces of the insulating layer 1. At this time, the first plating conductor 3 fills the vertical center portion of the through hole 2, and a part thereof protrudes from the upper and lower surfaces of the insulating layer 1 at the radial center portion of the through hole 2. Etching so as to remain. In addition, the circumference | surroundings of the protrusion part 3a in the 1st plating conductor 3 will be in the state dented about 5-40 micrometers from the upper-lower surface of the insulating layer 1.

次に、図１（ｆ）に示すように、エッチングレジスト４を除去した後、その表面に、厚みが０．１〜１μｍ程度の薄い無電解めっき層（不図示）を被着させる。この無電解めっき層は後述する第２のめっき導体６の下地金属として機能し、例えば、無電解銅めっき層が好適に用いられる。 Next, as shown in FIG. 1 (f), after removing the etching resist 4, a thin electroless plating layer (not shown) having a thickness of about 0.1 to 1 μm is deposited on the surface. This electroless plating layer functions as a base metal of the second plating conductor 6 described later, and for example, an electroless copper plating layer is suitably used.

次に、図１（ｇ）に示すように、絶縁層１の上下面に配線導体のパターンに対応する開口パターンを有するめっきレジスト５を形成する。 Next, as shown in FIG. 1G, a plating resist 5 having an opening pattern corresponding to the wiring conductor pattern is formed on the upper and lower surfaces of the insulating layer 1.

次に、図１（ｈ）に示すように、めっきレジスト５から露出する絶縁層１および第１のめっき導体３の表面に、電解めっき法により第２のめっき導体６を析出させる。この第２のめっき導体６は、貫通孔２の第１のめっき導体３よりも外側の部分を充填するとともに絶縁層１の上下面で１０〜２０μｍ程度の厚みとなるように形成する。この場合、貫通孔２の厚み方向の中央部は既に第１のめっき導体３により充填されているので、第２のめっき導体６は、貫通孔２の上下端部のみを充填する厚みに被着させればよいので、絶縁層１の上下面に厚みが１０〜２０μｍの薄い第２のめっき導体６を形成することができる。さらに、第１のめっき導体３は、その径方向の中央部に絶縁層１の上下面から突出する突出部３ａを有していることから、この突出部３ａの表面に第２のめっき導体６が析出することで、貫通孔２の上下端部が第２のめっき導体６により良好に充填されるとともに、貫通孔２の直上および直下に凹みのない配線導体７を形成することができる。なお、第２のめっき導体６としては、電解銅めっきが好適に用いられる。 Next, as shown in FIG. 1 (h), the second plated conductor 6 is deposited on the surfaces of the insulating layer 1 and the first plated conductor 3 exposed from the plating resist 5 by electrolytic plating. The second plated conductor 6 is formed so as to fill a portion outside the first plated conductor 3 of the through hole 2 and to have a thickness of about 10 to 20 μm on the upper and lower surfaces of the insulating layer 1. In this case, since the central portion of the through hole 2 in the thickness direction is already filled with the first plated conductor 3, the second plated conductor 6 is deposited to a thickness that fills only the upper and lower end portions of the through hole 2. Therefore, the thin second plating conductor 6 having a thickness of 10 to 20 μm can be formed on the upper and lower surfaces of the insulating layer 1. Further, since the first plated conductor 3 has a protruding portion 3a protruding from the upper and lower surfaces of the insulating layer 1 at the central portion in the radial direction, the second plated conductor 6 is formed on the surface of the protruding portion 3a. As a result of precipitation, the upper and lower end portions of the through hole 2 can be satisfactorily filled with the second plated conductor 6, and the wiring conductor 7 having no recess can be formed immediately above and directly below the through hole 2. In addition, as the 2nd plating conductor 6, electrolytic copper plating is used suitably.

最後に、図１（ｉ）に示すように、絶縁層１の上下面からめっきレジスト５を除去するとともに第２のめっき導体６から露出する無電解めっき層（不図示）をエッチング除去する。これによって、貫通孔２内が第１のめっき導体３および第２のめっき導体６で充填されているとともに絶縁層１の上下面に第２のめっき導体６から成る配線導体７が形成された配線基板が完成する。この場合、上述したように、この第２のめっき導体６から成る配線導体７の形成方法は、セミアディティブ法と呼ばれるものであり、下地金属である無電解めっき層の上に、配線導体７に対応したパターンの第２のめっき導体６を選択的に析出させた後、第２のめっき導体６から露出する下地の無電解めっき層をエッチング除去することにより配線導体７を形成するので、配線導体７を形成する第２のめっき導体６が大きくエッチングされることがない。したがって、セミアディティブ法によれば、微細な幅および間隔の配線導体７であっても形成可能である。 Finally, as shown in FIG. 1I, the plating resist 5 is removed from the upper and lower surfaces of the insulating layer 1, and the electroless plating layer (not shown) exposed from the second plating conductor 6 is removed by etching. Thereby, the inside of the through hole 2 is filled with the first plating conductor 3 and the second plating conductor 6 and the wiring conductor 7 composed of the second plating conductor 6 is formed on the upper and lower surfaces of the insulating layer 1. The substrate is completed. In this case, as described above, the method of forming the wiring conductor 7 composed of the second plating conductor 6 is called a semi-additive method, and the wiring conductor 7 is formed on the electroless plating layer as a base metal. After the second plating conductor 6 having a corresponding pattern is selectively deposited, the wiring conductor 7 is formed by etching away the underlying electroless plating layer exposed from the second plating conductor 6. The second plated conductor 6 that forms 7 is not greatly etched. Therefore, according to the semi-additive method, it is possible to form even the wiring conductor 7 having a fine width and interval.

また、上述したように、貫通孔２の直上および直下に凹みのない配線導体７を形成することができる。したがって、本発明の配線基板の製造方法によれば、この配線基板上に電子部品を搭載する場合であれば、電子部品と配線導体７とを良好に接続することが可能な配線基板を提供することができる。また、この配線基板上にさらにビルドアップ絶縁層およびビルドアップ配線導体を形成して多層化する場合であれば、配線導体７とビルドアップ配線導体とを良好に接続することが可能な配線基板を提供することができる。 Further, as described above, the wiring conductor 7 having no dent can be formed immediately above and below the through hole 2. Therefore, according to the method for manufacturing a wiring board of the present invention, there is provided a wiring board capable of satisfactorily connecting the electronic component and the wiring conductor 7 when the electronic component is mounted on the wiring board. be able to. Further, if a buildup insulating layer and a buildup wiring conductor are further formed on the wiring board to form a multilayer, a wiring board capable of satisfactorily connecting the wiring conductor 7 and the buildup wiring conductor is provided. Can be provided.

１絶縁層
２貫通孔
３第１のめっき導体
３ａ突出部
６第２のめっき導体
７配線導体 DESCRIPTION OF SYMBOLS 1 Insulation layer 2 Through-hole 3 1st plating conductor 3a Protrusion part 6 2nd plating conductor 7 Wiring conductor

Claims

上下面を有する絶縁層に前記上下面間を貫通する貫通孔を設ける第１の工程と、少なくとも前記貫通孔内およびその周囲の前記上下面に前記貫通孔を充填する第１のめっき導体を形成する第２の工程と、前記第１のめっき導体をエッチングして前記上下面の前記第１のめっき導体を除去するとともに、少なくとも前記貫通孔の上下方向の中央部を充填するように前記第１のめっき導体を残す第３の工程と、前記貫通孔内の前記第１のめっき導体よりも外側の部分を充填するとともに前記上下面で配線導体を形成する第２のめっき導体をセミアディティブ法により形成する第４工程とを行なう配線基板の製造方法であって、前記第３の工程において、前記第１のめっき導体の一部が前記貫通孔の径方向の中央部において前記上下面から突出する突出部を有して残るようにエッチングすることを特徴とする配線基板の製造方法。 A first step of providing a through hole penetrating between the upper and lower surfaces in an insulating layer having upper and lower surfaces; and forming a first plated conductor filling the through hole in at least the upper and lower surfaces in and around the through hole A second step of etching the first plated conductor to remove the first plated conductor on the upper and lower surfaces, and at least fill the vertical center of the through-hole. And a second plating conductor that fills a portion outside the first plating conductor in the through hole and forms a wiring conductor on the upper and lower surfaces by a semi-additive method. In the third step, a part of the first plating conductor protrudes from the upper and lower surfaces at the radial center portion of the through hole in the third step. Method for manufacturing a wiring substrate, characterized by etching to leave a detecting section.