JP2016122758A - Multilayer wiring board - Google Patents

Multilayer wiring board Download PDF

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JP2016122758A
JP2016122758A JP2014262607A JP2014262607A JP2016122758A JP 2016122758 A JP2016122758 A JP 2016122758A JP 2014262607 A JP2014262607 A JP 2014262607A JP 2014262607 A JP2014262607 A JP 2014262607A JP 2016122758 A JP2016122758 A JP 2016122758A
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wiring board
main
sub
mounting
layer
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JP6469441B2 (en
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一 坂本
Hajime Sakamoto
一 坂本
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Ibiden Co Ltd
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Ibiden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board capable of preventing occurrence of a crack caused by stress concentration.SOLUTION: A multilayer wiring board 1 comprises a main wiring board 20 and a wiring structure 10 embedded inside the main wiring board 20, and is mounted with an adjacent first semiconductor element 2 and second semiconductor element 3. An upper surface 208a of a fourth main insulating layer 208 of the main wiring board 20 is formed with a plurality of first mounting pads 213 for mounting the first semiconductor element 2 and a plurality of second mounting pads 214 for mounting the second semiconductor element 3. The upper surface 208a of the fourth main insulating layer 208 located between the first mounting pad 213 and the second mounting pad 214 is provided with a stress relaxation member 221. A stress relaxation member 110 is provided on a third sub-insulating layer 104 of the wiring structure 10.SELECTED DRAWING: Figure 2

Description

本発明は、複数の半導体素子を実装するための多層配線板に関する。   The present invention relates to a multilayer wiring board for mounting a plurality of semiconductor elements.

従来、このような分野の技術として、例えば特許文献１に記載のものがある。この公報に記載された多層配線板は、主絶縁層と主導体層とを交互に積層してなる主配線板と、該主配線板の内部に埋設される配線構造体とを備えている。配線構造体は、主導体層の配線幅よりも狭い配線幅の副導体層を有する。また、主配線板の表面には、ＭＰＵ（Micro-Processing Unit）（第１半導体素子）を実装するための第１実装パッドと、ＤＲＡＭ（Dynamic Random Access Memory）（第２半導体素子）を実装するための第２実装パッドとがそれぞれ複数形成されている。   Conventionally, as a technique in such a field, for example, there is one described in Patent Document 1. The multilayer wiring board described in this publication includes a main wiring board formed by alternately laminating main insulating layers and main conductor layers, and a wiring structure embedded in the main wiring board. The wiring structure has a sub conductor layer having a wiring width narrower than that of the main conductor layer. A first mounting pad for mounting an MPU (Micro-Processing Unit) (first semiconductor element) and a DRAM (Dynamic Random Access Memory) (second semiconductor element) are mounted on the surface of the main wiring board. For this reason, a plurality of second mounting pads are formed.

特開２０１３−２１４５７８号公報JP 2013-214578 A

しかしながら、上述した多層配線板に第１及び第２半導体素子を実装する場合、多層配線板と半導体素子双方の材料の熱膨張率の違いによって、熱応力が生じる可能性があると考えられる。特に、第１実装パッド及び第２実装パッド間の多層配線板の表面は、隣接して実装された第１及び第２半導体素子による熱膨張や収縮の影響を最も大きく受けるので、熱応力が生じやすいと推察される。このため、熱応力による応力集中が発生し、該表面にクラックが生じ、該表面の近くに埋設される配線構造体の副導体層の断線を引き起こしかねないと考えられる。   However, when the first and second semiconductor elements are mounted on the multilayer wiring board described above, it is considered that thermal stress may be generated due to the difference in the thermal expansion coefficient between the materials of both the multilayer wiring board and the semiconductor element. In particular, the surface of the multilayer wiring board between the first mounting pad and the second mounting pad is most affected by thermal expansion and contraction due to the first and second semiconductor elements mounted adjacent to each other, so that thermal stress is generated. It is assumed that it is easy. For this reason, stress concentration due to thermal stress occurs, cracks are generated on the surface, and it is considered that the sub conductor layer of the wiring structure embedded near the surface may be disconnected.

本発明は、応力集中に起因するクラックの発生を防止することができる多層配線板を提供することを目的とする。   An object of this invention is to provide the multilayer wiring board which can prevent generation | occurrence | production of the crack resulting from stress concentration.

上記課題を解決する本発明の多層配線板は、主絶縁層と主導体層とを交互に積層してなる主配線板と、前記主配線板に搭載されるとともに前記主導体層の配線幅よりも狭い配線幅の副導体層を有する配線構造体とを備え、隣接する第１半導体素子及び第２半導体素子を実装するための多層配線板であって、前記多層配線板の表面には、前記配線構造体の前記副導体層とそれぞれ電気的に接続され、前記第１半導体素子を実装するための複数の第１実装パッドと、前記第２半導体素子を実装するための複数の第２実装パッドとが形成され、前記複数の第１実装パッドと前記複数の第２の実装パッドとの間には、前記表面及び該表面の下方の少なくとも一方に形成される応力緩和部材が配置されている。   The multilayer wiring board of the present invention that solves the above-mentioned problems is based on a main wiring board formed by alternately laminating a main insulating layer and a main conductor layer, and a wiring width of the main conductor layer mounted on the main wiring board. And a wiring structure having a sub-conductor layer with a narrow wiring width, and a multilayer wiring board for mounting the adjacent first semiconductor element and second semiconductor element, A plurality of first mounting pads for mounting the first semiconductor element, and a plurality of second mounting pads for mounting the second semiconductor element, each electrically connected to the sub-conductor layer of the wiring structure. Between the plurality of first mounting pads and the plurality of second mounting pads, a stress relaxation member formed on at least one of the surface and the lower side of the surface is disposed.

本発明の実施形態によれば、応力集中に起因するクラックの発生を防止することができる。   According to the embodiment of the present invention, it is possible to prevent the occurrence of cracks due to stress concentration.

第１実施形態に係る多層配線板を示す部分断面図である。It is a fragmentary sectional view showing the multilayer wiring board concerning a 1st embodiment. 図１の配線構造体を示す拡大断面図である。It is an expanded sectional view which shows the wiring structure of FIG. 第１実施形態に係る多層配線板の模式的平面図である。1 is a schematic plan view of a multilayer wiring board according to a first embodiment. 第２実施形態に係る多層配線板を示す部分断面図である。It is a fragmentary sectional view showing the multilayer wiring board concerning a 2nd embodiment. 図４の配線構造体を示す拡大断面図である。It is an expanded sectional view which shows the wiring structure of FIG. 第３実施形態に係る多層配線板を示す部分断面図である。It is a fragmentary sectional view showing a multilayer wiring board concerning a 3rd embodiment. 図６の配線構造体を示す拡大断面図である。It is an expanded sectional view which shows the wiring structure of FIG. 第４実施形態に係る多層配線板を示す拡大断面図である。It is an expanded sectional view showing the multilayer wiring board concerning a 4th embodiment. 第５実施形態に係る多層配線板を示す拡大断面図である。It is an expanded sectional view showing the multilayer wiring board concerning a 5th embodiment. 第６実施形態に係る多層配線板を示す拡大断面図である。It is an expanded sectional view showing a multilayer wiring board concerning a 6th embodiment. 第７実施形態に係る多層配線板を示す拡大断面図である。It is an expanded sectional view showing a multilayer wiring board concerning a 7th embodiment. 第８実施形態に係る多層配線板を示す拡大断面図である。It is an expanded sectional view showing the multilayer wiring board concerning an 8th embodiment. アンダーフィル材が充填された状態を示す部分断面図である。It is a fragmentary sectional view which shows the state with which the underfill material was filled. 多層配線板の模式的平面図である。It is a schematic plan view of a multilayer wiring board.

以下、図面を参照して本発明に係る多層配線板の実施形態について説明する。図面の説明において同一の要素には同一符号を付し、重複する説明は省略する。   Hereinafter, embodiments of a multilayer wiring board according to the present invention will be described with reference to the drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

＜第１実施形態＞
図１に示すように、第１実施形態に係る多層配線板１は、主配線板２０と主配線板２０に搭載される配線構造体１０とを備えている。主配線板２０は、その中央位置に配置されたコア基板２００を挟んで、コア基板２００の主面Ｆ１及び主面Ｆ１の反対側の主面Ｆ２の上にそれぞれ主絶縁層と主導体層とを交互に積層してなるビルドアップ積層配線板である。主配線板２０は、配線構造体１０の埋設部分を除いて、コア基板２００の中心軸Ｌを挟んで同じ工程により同様の機能を有する層を順次積層することで形成されている。従って、以下の説明においては、片側（コア基板２００の主面Ｆ１側）のみを用いて説明する。 <First Embodiment>
As shown in FIG. 1, the multilayer wiring board 1 according to the first embodiment includes a main wiring board 20 and a wiring structure 10 mounted on the main wiring board 20. The main wiring board 20 has a main insulating layer and a main conductor layer on the main surface F1 on the opposite side of the main surface F1 and the main surface F1 of the core substrate 200, with the core substrate 200 disposed at the center position therebetween. This is a build-up laminated wiring board obtained by alternately laminating layers. The main wiring board 20 is formed by sequentially laminating layers having the same function through the same process with the central axis L of the core substrate 200 interposed therebetween except for the embedded portion of the wiring structure 10. Therefore, in the following description, only one side (the main surface F1 side of the core substrate 200) will be described.

コア基板２００の上には、無電解めっき層２０１ａ及び電解めっき層２０１ｂを有する第１主導体層２０１が形成されている。第１主導体層２０１は、その上に形成された第１主絶縁層２０２によって覆われている。第１主絶縁層２０２は、例えば熱硬化性エポキシ樹脂により形成されている。なお、本実施形態において、主導体層及び後述の副導体層は、電気回路を構成する配線層であり、その位置によってパッドと配線パターン等とを含む場合もあれば、電子部品を実装するための実装パッドのみを含む場合もある。   On the core substrate 200, a first main conductor layer 201 having an electroless plating layer 201a and an electrolytic plating layer 201b is formed. The first main conductor layer 201 is covered with a first main insulating layer 202 formed thereon. The first main insulating layer 202 is made of, for example, a thermosetting epoxy resin. In the present embodiment, a main conductor layer and a sub conductor layer described later are wiring layers that constitute an electric circuit, and may include a pad, a wiring pattern, and the like depending on the position, or for mounting electronic components. In some cases, only the mounting pads are included.

第１主絶縁層２０２の上には、更に、第２主導体層２０３、第２主導体層２０３を覆う第２主絶縁層２０４、第３主導体層２０５、第３主導体層２０５を覆う第３主絶縁層２０６、第４主導体層２０７、第４主導体層２０７を覆う第４主絶縁層２０８が、この順番で積層されている。第２主導体層２０３、第３主導体層２０５及び第４主導体層２０７は、第１主導体層２０１と同様に無電解めっき層及び電解めっき層によって構成されている。一方、第２主絶縁層２０４、第３主絶縁層２０６及び第４主絶縁層２０８は、第１主絶縁層２０２と同様に熱硬化性エポキシ樹脂により形成されている。   On the first main insulating layer 202, the second main conductor layer 203, the second main conductor layer 204 covering the second main conductor layer 203, the third main conductor layer 205, and the third main conductor layer 205 are further covered. A third main insulating layer 206, a fourth main conductor layer 207, and a fourth main insulating layer 208 covering the fourth main conductor layer 207 are laminated in this order. Similar to the first main conductor layer 201, the second main conductor layer 203, the third main conductor layer 205, and the fourth main conductor layer 207 are composed of an electroless plating layer and an electrolytic plating layer. On the other hand, the second main insulating layer 204, the third main insulating layer 206, and the fourth main insulating layer 208 are formed of a thermosetting epoxy resin in the same manner as the first main insulating layer 202.

また、第１主絶縁層２０２の内部には第１主ビア導体２１０、第２主絶縁層２０４の内部には第２主ビア導体２１１、第３主絶縁層２０６の内部には第３主ビア導体２１２が、それぞれ複数形成されている。これらの主ビア導体２１０，２１１，２１２は、それぞれ円錐台形状を呈し、コア基板２００の主面Ｆ２から主面Ｆ１に向かう方向に拡径されている。そして、第１主導体層２０１及び第２主導体層２０３はその間に配置された第１主ビア導体２１０、第２主導体層２０３及び第３主導体層２０５はその間に配置された第２主ビア導体２１１、第３主導体層２０５及び第４主導体層２０７はその間に配置された第３主ビア導体２１２によってそれぞれ電気的に接続されている。なお、コア基板２００の主面Ｆ１に形成された第１主導体層２０１は、コア基板２００の内部に設けられたスルーホール導体２０９を介して、反対側の主面Ｆ２に形成された第１主導体層２０１と電気的に接続されている。   The first main insulating layer 202 has a first main via conductor 210, the second main insulating layer 204 has a second main via conductor 211, and the third main insulating layer 206 has a third main via. A plurality of conductors 212 are formed. These main via conductors 210, 211, and 212 each have a truncated cone shape and are expanded in the direction from the main surface F <b> 2 of the core substrate 200 to the main surface F <b> 1. The first main conductor layer 201 and the second main conductor layer 203 are disposed between the first main via conductor 210, the second main conductor layer 203, and the third main conductor layer 205 are disposed between them. The via conductor 211, the third main conductor layer 205, and the fourth main conductor layer 207 are electrically connected by a third main via conductor 212 disposed therebetween. The first main conductor layer 201 formed on the main surface F1 of the core substrate 200 is formed on the opposite main surface F2 via the through-hole conductor 209 provided inside the core substrate 200. The main conductor layer 201 is electrically connected.

主配線板２０の内部には、配線構造体１０が埋設されている。配線構造体１０は、主配線板２０の第３主導体層２０５の上に配置され、第４主導体層２０７及び第３主ビア導体２１２と並設されている。配線構造体１０は、第４主導体層２０７とともに第４主絶縁層２０８によって覆われ、配線構造体１０の内部に封止されている。第４主絶縁層２０８は、多層配線板１の最も外側に配置され、多層配線板１の最外層を構成する。そして、第４主絶縁層２０８の上表面２０８ａは、特許請求の範囲に記載の「多層配線板の表面」に相当するものである。   A wiring structure 10 is embedded in the main wiring board 20. The wiring structure 10 is disposed on the third main conductor layer 205 of the main wiring board 20 and is juxtaposed with the fourth main conductor layer 207 and the third main via conductor 212. The wiring structure 10 is covered by the fourth main insulating layer 208 together with the fourth main conductor layer 207 and sealed inside the wiring structure 10. The fourth main insulating layer 208 is disposed on the outermost side of the multilayer wiring board 1 and constitutes the outermost layer of the multilayer wiring board 1. The upper surface 208a of the fourth main insulating layer 208 corresponds to the “surface of the multilayer wiring board” recited in the claims.

第４主絶縁層２０８の上表面２０８ａには、隣接する第１半導体素子２及び第２半導体素子３を実装するための第１実装パッド２１３、第２実装パッド２１４、第３実装パッド２１５及び第４実装パッド２１６がそれぞれ複数形成されている。これらの複数の第１実装パッド２１３、第２実装パッド２１４、第３実装パッド２１５及び第４実装パッド２１６は、所定の間隔を開けて並設されている（図３参照）。そして、これらの第１実装パッド２１３、第２実装パッド２１４、第３実装パッド２１５及び第４実装パッド２１６の上表面は、同一平面に位置している。   On the upper surface 208a of the fourth main insulating layer 208, a first mounting pad 213, a second mounting pad 214, a third mounting pad 215, and a second mounting pad for mounting the adjacent first semiconductor element 2 and second semiconductor element 3 are provided. A plurality of four mounting pads 216 are formed. The plurality of first mounting pads 213, second mounting pads 214, third mounting pads 215, and fourth mounting pads 216 are arranged in parallel at predetermined intervals (see FIG. 3). The upper surfaces of the first mounting pad 213, the second mounting pad 214, the third mounting pad 215, and the fourth mounting pad 216 are located on the same plane.

第１実装パッド２１３は、第１半導体素子２を実装するためのパッドであり、第４主絶縁層２０８の上表面２０８ａであって埋設された配線構造体１０に対応するエリアＡ（すなわち、配線構造体１０の直上位置）に配置されている。第２実装パッド２１４は、第２半導体素子３を実装するためのパッドであり、第４主絶縁層２０８の上表面２０８ａであって埋設された配線構造体１０に対応するエリアＡに配置され、第１実装パッド２１３と並設されている。これらの第１実装パッド２１３及び第２実装パッド２１４は、それぞれ所定の間隔を開けて上表面２０８ａ上に配列されている。そして、第１実装パッド２１３は、第４主絶縁層２０８の内部に設けられた第４主ビア導体２１７を介して、その下方に配置された配線構造体１０と電気的に接続されている。一方、第２実装パッド２１４は、第４主絶縁層２０８の内部に設けられた第５主ビア導体２１８を介して、その下方に配置された配線構造体１０と電気的に接続されている。   The first mounting pad 213 is a pad for mounting the first semiconductor element 2. The first mounting pad 213 is an area A (that is, a wiring) corresponding to the embedded wiring structure 10 on the upper surface 208 a of the fourth main insulating layer 208. (Position just above the structure 10). The second mounting pad 214 is a pad for mounting the second semiconductor element 3 and is disposed in the area A corresponding to the embedded wiring structure 10 on the upper surface 208a of the fourth main insulating layer 208, The first mounting pad 213 is juxtaposed. The first mounting pad 213 and the second mounting pad 214 are arranged on the upper surface 208a with a predetermined gap therebetween. The first mounting pad 213 is electrically connected to the wiring structure 10 disposed below the fourth main via conductor 217 provided inside the fourth main insulating layer 208. On the other hand, the second mounting pad 214 is electrically connected to the wiring structure 10 arranged below the fifth main via conductor 218 provided in the fourth main insulating layer 208.

第３実装パッド２１５は、第４主絶縁層２０８の上表面２０８ａであってエリアＡを挟んで一方側（図１では、エリアＡの左側）のエリアＢに配置されている。第３実装パッド２１５は、第１実装パッド２１３と同様に第１半導体素子２を実装するためのパッドであるが、その配線幅が第１実装パッド２１３よりも広い。言い換えれば、第１実装パッド２１３の配線幅は、第３実装パッド２１５の配線幅よりも狭い。この第３実装パッド２１５は、第４主絶縁層２０８の内部に設けられた第６主ビア導体２１９を介して、主配線板２０の第４主導体層２０７と電気的に接続されている。そして、第１半導体素子２が多層配線板１に実装される場合、第３実装パッド２１５及び第１実装パッド２１３は、半田バンプ４を介してそれぞれ第１半導体素子２の電極と電気的に接続される。   The third mounting pad 215 is disposed on the area B on the one surface (the left side of the area A in FIG. 1) on the upper surface 208a of the fourth main insulating layer 208 with the area A interposed therebetween. The third mounting pad 215 is a pad for mounting the first semiconductor element 2 similarly to the first mounting pad 213, but the wiring width is wider than that of the first mounting pad 213. In other words, the wiring width of the first mounting pad 213 is narrower than the wiring width of the third mounting pad 215. The third mounting pad 215 is electrically connected to the fourth main conductor layer 207 of the main wiring board 20 via a sixth main via conductor 219 provided inside the fourth main insulating layer 208. When the first semiconductor element 2 is mounted on the multilayer wiring board 1, the third mounting pad 215 and the first mounting pad 213 are electrically connected to the electrodes of the first semiconductor element 2 through the solder bumps 4, respectively. Is done.

第４実装パッド２１６は、第４主絶縁層２０８の上表面２０８ａであってエリアＡを挟んで他方側（図１では、エリアＡの右側）のエリアＣに配置されている。第４実装パッド２１６は、第２実装パッド２１４と同様に第２半導体素子３を実装するためのパッドであるが、その配線幅が第２実装パッド２１４よりも広い。言い換えれば、第２実装パッド２１４の配線幅は、第４実装パッド２１６の配線幅よりも狭い。この第４実装パッド２１６は、第４主絶縁層２０８の内部に設けられた第７主ビア導体２２０を介して、主配線板２０の第４主導体層２０７と電気的に接続されている。そして、第２半導体素子３が多層配線板１に実装される場合、第４実装パッド２１６及び第２実装パッド２１４は、半田バンプ４を介してそれぞれ第２半導体素子３の電極と電気的に接続される。   The fourth mounting pad 216 is disposed on the area C on the other side (the right side of the area A in FIG. 1) on the other surface (in FIG. 1, the right side of the area A) on the upper surface 208a of the fourth main insulating layer 208. The fourth mounting pad 216 is a pad for mounting the second semiconductor element 3 similarly to the second mounting pad 214, but the wiring width is wider than that of the second mounting pad 214. In other words, the wiring width of the second mounting pad 214 is narrower than the wiring width of the fourth mounting pad 216. The fourth mounting pad 216 is electrically connected to the fourth main conductor layer 207 of the main wiring board 20 via a seventh main via conductor 220 provided inside the fourth main insulating layer 208. When the second semiconductor element 3 is mounted on the multilayer wiring board 1, the fourth mounting pad 216 and the second mounting pad 214 are electrically connected to the electrodes of the second semiconductor element 3 through the solder bumps 4, respectively. Is done.

図２に示すように、配線構造体１０は、断面矩形を呈し、三次元的には直方体に形成されており、その底部に配置されたダイアタッチフィルム（接着層）１０９を介して主配線板２０の第３主導体層２０５に固定されている。ダイアタッチフィルム１０９の上には、第１副絶縁層１００が配置されている。第１副絶縁層１００の上には、第１副導体層１０１、第２副絶縁層１０２、第２副導体層１０３及び第３副絶縁層１０４がこの順番で積層されている。   As shown in FIG. 2, the wiring structure 10 has a rectangular cross section, is three-dimensionally formed in a rectangular parallelepiped, and is connected to the main wiring board via a die attach film (adhesive layer) 109 disposed on the bottom thereof. Twenty third main conductor layers 205 are fixed. A first sub-insulating layer 100 is disposed on the die attach film 109. On the first sub-insulating layer 100, a first sub-conductor layer 101, a second sub-insulating layer 102, a second sub-conductor layer 103, and a third sub-insulating layer 104 are laminated in this order.

第１副絶縁層１００、第２副絶縁層１０２及び第３副絶縁層１０４は、感光性樹脂からなる絶縁層である。このように感光性樹脂層を用いることで、副絶縁層に小径のビア孔及び狭い配線幅の副導体層を容易に形成することができる。第１副導体層１０１及び第２副導体層１０３は、シード層と銅めっき層によって構成され、主配線板２０の主導体層２０１，２０３，２０５，２０７の配線幅よりも狭い配線幅で形成されている。また、第２副絶縁層１０２の内部には第１副ビア導体１０７、第３副絶縁層１０４の内部には第２副ビア導体１０８が、それぞれ複数形成されている。   The first sub-insulating layer 100, the second sub-insulating layer 102, and the third sub-insulating layer 104 are insulating layers made of a photosensitive resin. By using the photosensitive resin layer in this way, a small-diameter via hole and a sub-conductor layer with a narrow wiring width can be easily formed in the sub-insulating layer. The first sub conductor layer 101 and the second sub conductor layer 103 are constituted by a seed layer and a copper plating layer, and are formed with a wiring width narrower than that of the main conductor layers 201, 203, 205, and 207 of the main wiring board 20. Has been. A plurality of first sub via conductors 107 are formed inside the second sub insulating layer 102, and a plurality of second sub via conductors 108 are formed inside the third sub insulating layer 104.

第３副絶縁層１０４は、配線構造体１０の最も外側に配置されている。第３副絶縁層１０４の上表面１０４ａには、第１実装パッド２１３に対応する第１副導電パッド１０５、第２実装パッド２１４に対応する第２副導電パッド１０６がそれぞれ複数形成されている。すなわち、第１副導電パッド１０５は、第１実装パッド２１３の直下位置に配置され、第１実装パッド２１３と同じ配線幅で配列されている。第２副導電パッド１０６は、第２実装パッド２１４の直下位置に配置され、第２実装パッド２１４と同じ配線幅で配列されている。第１副導電パッド１０５は、第４主ビア導体２１７を介して第１実装パッド２１３と電気的に接続されており、第２副導電パッド１０６は、第５主ビア導体２１８を介して第２実装パッド２１４と電気的に接続されている。   The third sub-insulating layer 104 is disposed on the outermost side of the wiring structure 10. A plurality of first sub conductive pads 105 corresponding to the first mounting pads 213 and a plurality of second sub conductive pads 106 corresponding to the second mounting pads 214 are formed on the upper surface 104 a of the third sub insulating layer 104. That is, the first sub-conductive pads 105 are disposed immediately below the first mounting pads 213 and are arranged with the same wiring width as the first mounting pads 213. The second sub conductive pads 106 are disposed immediately below the second mounting pads 214 and are arranged with the same wiring width as the second mounting pads 214. The first sub conductive pad 105 is electrically connected to the first mounting pad 213 through the fourth main via conductor 217, and the second sub conductive pad 106 is connected to the second main conductive pad 218 through the fifth main via conductor 218. It is electrically connected to the mounting pad 214.

図２に示すように、第１副導電パッド１０５及び第２副導電パッド１０６は、第３副絶縁層１０４の内部に設けられた第２副ビア導体１０８を介して第２副導体層１０３とそれぞれ電気的に接続されている。第２副導体層１０３は、更に第１副ビア導体１０７を介して第１副導体層１０１と電気的に接続されている。また、図示しないが、第１副導電パッド１０５及び第２副導電パッド１０６は、配線構造体１０内部に設けられた配線によって互いに電気的に接続されている。このため、第１実装パッド２１３に実装される第１半導体素子２、及び第２実装パッド２１４に実装される第２半導体素子３は、主ビア導体２１７，２１８及び配線構造体１０を介して互いに電気的に接続される。   As shown in FIG. 2, the first sub-conductive pad 105 and the second sub-conductive pad 106 are connected to the second sub-conductor layer 103 via the second sub-via conductor 108 provided in the third sub-insulating layer 104. Each is electrically connected. The second sub conductor layer 103 is further electrically connected to the first sub conductor layer 101 via the first sub via conductor 107. Although not shown, the first sub-conductive pad 105 and the second sub-conductive pad 106 are electrically connected to each other by wiring provided inside the wiring structure 10. Therefore, the first semiconductor element 2 mounted on the first mounting pad 213 and the second semiconductor element 3 mounted on the second mounting pad 214 are mutually connected via the main via conductors 217 and 218 and the wiring structure 10. Electrically connected.

本実施形態において、複数の第１実装パッド２１３と複数の第２実装パッド２１４との間には、第４主絶縁層２０８の上表面２０８ａに形成される応力緩和部材２２１、及び該上表面２０８ａの下方に形成される応力緩和部材１１０が配置されている。具体的には、図２に示すように、第１実装パッド２１３と第２実装パッド２１４との間に位置する第４主絶縁層２０８の上表面２０８ａには、ダミー配線からなる応力緩和部材２２１が設けられている。この応力緩和部材２２１は、隣接する第１実装パッド２１３及び第２実装パッド２１４と同様に無電解めっき層及び電解めっき層によって構成されているが、その周囲に配置される第１実装パッド２１３、第２実装パッド２１４及び配線構造体１０のいずれも電気的に接続されていない。すなわち、応力緩和部材２２１は、電気接続に寄与しない配線である。なお、応力緩和部材２２１の上表面は、第１実装パッド２１３の上表面及び第２実装パッド２１４の上表面と同一平面に位置している。   In the present embodiment, between the plurality of first mounting pads 213 and the plurality of second mounting pads 214, the stress relaxation member 221 formed on the upper surface 208a of the fourth main insulating layer 208, and the upper surface 208a. The stress relaxation member 110 formed below is disposed. Specifically, as shown in FIG. 2, the upper surface 208a of the fourth main insulating layer 208 located between the first mounting pad 213 and the second mounting pad 214 has a stress relaxation member 221 made of dummy wiring. Is provided. The stress relieving member 221 is composed of an electroless plating layer and an electrolytic plating layer as in the case of the adjacent first mounting pad 213 and second mounting pad 214, but the first mounting pad 213 disposed around the electroless plating layer, Neither the second mounting pad 214 nor the wiring structure 10 is electrically connected. That is, the stress relaxation member 221 is a wiring that does not contribute to electrical connection. The upper surface of the stress relaxation member 221 is located on the same plane as the upper surface of the first mounting pad 213 and the upper surface of the second mounting pad 214.

また、第１実装パッド２１３と第２実装パッド２１４との間に位置する第４主絶縁層２０８の上表面２０８ａの下方（すなわち、上表面２０８ａより主配線板２０の内部側）には、ダミー配線からなる応力緩和部材１１０が更に設けられている。この応力緩和部材１１０は、配線構造体１０の第３副絶縁層１０４の上表面１０４ａに設けられ、応力緩和部材２２１の略直下位置に配置されている。応力緩和部材１１０は、隣接する第１副導電パッド１０５及び第２副導電パッド１０６と同様にシールド層と銅めっき層によって構成されているが、その周囲に配置される第１副導電パッド１０５、第２副導電パッド１０６、第２副導体層１０３及び第１副導体層１０１のいずれも電気的に接続されていない。すなわち、応力緩和部材１１０は、電気接続に寄与しない配線である。なお、応力緩和部材１１０の上表面は、第１副導電パッド１０５の上表面及び第２副導電パッド１０６の上表面と同一平面に位置している。   In addition, a dummy is provided below the upper surface 208a of the fourth main insulating layer 208 located between the first mounting pad 213 and the second mounting pad 214 (that is, inside the main wiring board 20 from the upper surface 208a). A stress relaxation member 110 made of wiring is further provided. The stress relaxation member 110 is provided on the upper surface 104 a of the third sub-insulating layer 104 of the wiring structure 10 and is disposed at a position almost directly below the stress relaxation member 221. The stress relaxation member 110 is composed of a shield layer and a copper plating layer, like the adjacent first sub-conductive pad 105 and second sub-conductive pad 106, but the first sub-conductive pad 105 disposed around the stress-relieving member 110, None of the second sub-conductive pad 106, the second sub-conductor layer 103, and the first sub-conductor layer 101 are electrically connected. That is, the stress relaxation member 110 is a wiring that does not contribute to electrical connection. Note that the upper surface of the stress relaxation member 110 is located on the same plane as the upper surface of the first sub-conductive pad 105 and the upper surface of the second sub-conductive pad 106.

以上の構成を有する多層配線板１では、第１実装パッド２１３と第２実装パッド２１４との間に、第４主絶縁層２０８の上表面２０８ａに形成される応力緩和部材２２１、及び該上表面２０８ａの下方に形成される応力緩和部材１１０が配置されている。このように、隣接して実装された第１半導体素子２及び第２半導体素子３による熱膨張や収縮の影響を最も受けやすい場所に応力緩和部材１１０，２２１を設けることで、多層配線板１と半導体素子２，３双方の材料の熱膨張率の違いによって生じる熱応力を緩和し、熱応力による応力集中の発生を抑制することができる。従って、応力集中に起因して第１実装パッド２１３と第２実装パッド２１４との間位置する第４主絶縁層２０８の上表面２０８ａでのクラックの発生を防止することができる。そして、クラックの発生を防止することにより、内部に埋設された配線構造体１０の副導体層１０１，１０３の断線を確実に抑えることができ、多層配線板１の信頼性を高める効果を奏する。   In the multilayer wiring board 1 having the above configuration, the stress relaxation member 221 formed on the upper surface 208a of the fourth main insulating layer 208 between the first mounting pad 213 and the second mounting pad 214, and the upper surface A stress relaxation member 110 formed below 208a is disposed. As described above, by providing the stress relaxation members 110 and 221 in the place most susceptible to thermal expansion and contraction by the first semiconductor element 2 and the second semiconductor element 3 mounted adjacent to each other, the multilayer wiring board 1 and It is possible to relieve the thermal stress caused by the difference in thermal expansion coefficient between the materials of the semiconductor elements 2 and 3, and to suppress the occurrence of stress concentration due to the thermal stress. Therefore, it is possible to prevent the occurrence of cracks on the upper surface 208a of the fourth main insulating layer 208 located between the first mounting pad 213 and the second mounting pad 214 due to the stress concentration. By preventing the occurrence of cracks, disconnection of the sub-conductor layers 101 and 103 of the wiring structure 10 embedded therein can be reliably suppressed, and the effect of improving the reliability of the multilayer wiring board 1 can be achieved.

加えて、応力緩和部材１１０がその隣接する第１副導電パッド１０５、第２副導電パッド１０６と同様に第３副絶縁層１０４の上に形成され、しかも同じ材料によって構成されているため、第１副導電パッド１０５及び第２副導電パッド１０６の形成と同時に応力緩和部材１１０を形成することが可能になる。従って、応力緩和部材１１０の設置に伴う製造工数を増やすことがなく、製造コストを抑制することができる。同様に、応力緩和部材２２１もその隣接する第１実装パッド２１３、第２実装パッド２１４と同様に第４主絶縁層２０８の上に形成され、且つ同じ材料によって構成されているため、第１実装パッド２１３及び第２実装パッド２１４の形成と同時に応力緩和部材２２１を形成することが可能になり、製造コストを抑制することができる。   In addition, since the stress relaxation member 110 is formed on the third sub-insulating layer 104 similarly to the adjacent first sub-conductive pad 105 and the second sub-conductive pad 106, and is made of the same material, The stress relaxation member 110 can be formed simultaneously with the formation of the first sub-conductive pad 105 and the second sub-conductive pad 106. Therefore, the manufacturing cost associated with the installation of the stress relaxation member 110 is not increased, and the manufacturing cost can be suppressed. Similarly, the stress relieving member 221 is formed on the fourth main insulating layer 208 in the same manner as the adjacent first mounting pad 213 and second mounting pad 214 and is made of the same material. The stress relaxation member 221 can be formed simultaneously with the formation of the pad 213 and the second mounting pad 214, and the manufacturing cost can be suppressed.

＜第２実施形態＞
以下、図４及び５を参照して本発明の第２実施形態を説明する。この実施形態に係る多層配線板５と上述した第１実施形態との相違点は、配線構造体１０が主配線板２１の内部に埋設されずに外部に露出すること、及び応力緩和部材１１０だけを設けることである。 Second Embodiment
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. The difference between the multilayer wiring board 5 according to this embodiment and the above-described first embodiment is that the wiring structure 10 is not embedded in the main wiring board 21 but exposed to the outside, and only the stress relaxation member 110. It is to provide.

具体的には、配線構造体１０は、主配線板２１の第３主絶縁層２０６部に設けられた凹部２２２内に配置され、ダイアタッチフィルム１０９を介して第３主導体層２０５に固定されている（図５参照）。本実施形態に係る配線構造体１０は、主絶縁層に覆われておらず、外部に露出している。このため、配線構造体１０の第３副絶縁層１０４は、多層配線板５の最外層を構成することになる。従って、第３副絶縁層１０４の上表面１０４ａは、特許請求の範囲に記載の「多層配線板の表面」に相当する。なお、第３副絶縁層１０４の上表面１０４ａは、主配線板２１の第３主絶縁層２０６の上表面２０６ａと同一平面に位置している。   Specifically, the wiring structure 10 is disposed in the recess 222 provided in the third main insulating layer 206 of the main wiring board 21 and is fixed to the third main conductor layer 205 via the die attach film 109. (See FIG. 5). The wiring structure 10 according to the present embodiment is not covered with the main insulating layer and is exposed to the outside. For this reason, the third sub-insulating layer 104 of the wiring structure 10 constitutes the outermost layer of the multilayer wiring board 5. Accordingly, the upper surface 104a of the third sub-insulating layer 104 corresponds to the “surface of the multilayer wiring board” recited in the claims. The upper surface 104a of the third sub-insulating layer 104 is located on the same plane as the upper surface 206a of the third main insulating layer 206 of the main wiring board 21.

第３副絶縁層１０４の上表面１０４ａに形成された複数の第１副導電パッド１０５及び複数の第２副導電パッド１０６は、外部に露出し、第１半導体素子２を実装するための第１実装パッド、第２半導体素子３を実装するための第２実装パッドをそれぞれ構成する。そして、第１半導体素子２と第２半導体素子３とが実装される際に、第１副導電パッド１０５は半田バンプ４を介して直接に第１半導体素子２の電極と電気的に接続され、第２副導電パッド１０６は半田バンプ４を介して直接に第２半導体素子３の電極と電気的に接続される。   The plurality of first sub-conductive pads 105 and the plurality of second sub-conductive pads 106 formed on the upper surface 104a of the third sub-insulating layer 104 are exposed to the outside, and are used for mounting the first semiconductor element 2. A mounting pad and a second mounting pad for mounting the second semiconductor element 3 are configured. Then, when the first semiconductor element 2 and the second semiconductor element 3 are mounted, the first sub-conductive pad 105 is electrically connected to the electrode of the first semiconductor element 2 directly via the solder bump 4, The second sub conductive pad 106 is electrically connected to the electrode of the second semiconductor element 3 directly via the solder bump 4.

配線構造体１０を挟んで第３主絶縁層２０６の上表面２０６ａの一方側（図４では、左側）には、第１半導体素子２を実装するための第３実装パッド２１５が複数形成されている。一方、配線構造体１０を挟んで第３主絶縁層２０６の上表面２０６ａの他方側（図４では、右側）には、第２半導体素子３を実装するための第４実装パッド２１６が複数形成されている。第３実装パッド２１５は第３主絶縁層２０６の内部に設けられた第６主ビア導体２１９を介し、第４実装パッド２１６は第３主絶縁層２０６の内部に設けられた第７主ビア導体２２０を介し、第３主導体層２０５とそれぞれ電気的に接続されている。なお、第３実装パッド２１５、第４実装パッド２１６、第１副導電パッド１０５及び第２副導電パッド１０６の上表面は、同一平面に位置している。   A plurality of third mounting pads 215 for mounting the first semiconductor element 2 are formed on one side (left side in FIG. 4) of the upper surface 206a of the third main insulating layer 206 with the wiring structure 10 interposed therebetween. Yes. On the other hand, a plurality of fourth mounting pads 216 for mounting the second semiconductor element 3 are formed on the other side (right side in FIG. 4) of the upper surface 206a of the third main insulating layer 206 with the wiring structure 10 interposed therebetween. Has been. The third mounting pad 215 is provided via a sixth main via conductor 219 provided in the third main insulating layer 206, and the fourth mounting pad 216 is provided as a seventh main via conductor provided in the third main insulating layer 206. Each of the third main conductor layers 205 is electrically connected via 220. The upper surfaces of the third mounting pad 215, the fourth mounting pad 216, the first sub conductive pad 105, and the second sub conductive pad 106 are located on the same plane.

本実施形態に係る多層配線板５は、ダミー配線からなる応力緩和部材１１０だけを有する。この応力緩和部材１１０は、第１副導電パッド１０５と第２副導電パッド１０６との間に位置する第３副絶縁層１０４の上表面１０４ａに設けられている。以上の構成を有する多層配線板５は、第１実施形態と同様な作用効果を得られる。   The multilayer wiring board 5 according to the present embodiment has only the stress relaxation member 110 made of dummy wiring. The stress relaxation member 110 is provided on the upper surface 104 a of the third sub-insulating layer 104 located between the first sub-conductive pad 105 and the second sub-conductive pad 106. The multilayer wiring board 5 having the above configuration can obtain the same effects as those of the first embodiment.

＜第３実施形態＞
以下、図６及び７を参照して本発明の第３実施形態を説明する。この実施形態に係る多層配線板６と上述した第１実施形態との相違点は、配線構造体１０が主配線板２２の内部に埋設されずに主配線板２２より外部に突出すること、及び応力緩和部材１１０だけを設けることである。 <Third Embodiment>
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. The difference between the multilayer wiring board 6 according to this embodiment and the first embodiment described above is that the wiring structure 10 protrudes outside from the main wiring board 22 without being embedded in the main wiring board 22, and Only the stress relaxation member 110 is provided.

具体的には、配線構造体１０は、ダイアタッチフィルム１０９を介して主配線板２２の第３主絶縁層２０６の上表面２０６ａに固定されている（図７参照）。本実施形態に係る配線構造体１０は、第１実施形態と異なって主絶縁層に覆われておらず、第３主絶縁層２０６より外部に突出し、外部に露出している。このため、配線構造体１０の第３副絶縁層１０４は、多層配線板６の最外層を構成することになり、第３副絶縁層１０４の上表面１０４ａは、特許請求の範囲に記載の「多層配線板の表面」に相当する。   Specifically, the wiring structure 10 is fixed to the upper surface 206a of the third main insulating layer 206 of the main wiring board 22 via the die attach film 109 (see FIG. 7). Unlike the first embodiment, the wiring structure 10 according to the present embodiment is not covered with the main insulating layer, protrudes outside from the third main insulating layer 206, and is exposed to the outside. Therefore, the third sub-insulating layer 104 of the wiring structure 10 constitutes the outermost layer of the multilayer wiring board 6, and the upper surface 104a of the third sub-insulating layer 104 is described in the claims. This corresponds to the “surface of the multilayer wiring board”.

第３副絶縁層１０４の上表面１０４ａに形成された複数の第１副導電パッド１０５及び複数の第２副導電パッド１０６は、外部に露出し、第１半導体素子２を実装するための第１実装パッド、第２半導体素子３を実装するための第２実装パッドをそれぞれ構成する。そして、第１半導体素子２と第２半導体素子３とが実装される際に、第１副導電パッド１０５は半田バンプ７を介して直接に第１半導体素子２の電極と電気的に接続され、第２副導電パッド１０６は半田バンプ７を介して直接に第２半導体素子３の電極と電気的に接続される。   The plurality of first sub-conductive pads 105 and the plurality of second sub-conductive pads 106 formed on the upper surface 104a of the third sub-insulating layer 104 are exposed to the outside, and are used for mounting the first semiconductor element 2. A mounting pad and a second mounting pad for mounting the second semiconductor element 3 are configured. Then, when the first semiconductor element 2 and the second semiconductor element 3 are mounted, the first sub-conductive pad 105 is electrically connected to the electrode of the first semiconductor element 2 directly via the solder bump 7, The second sub conductive pad 106 is electrically connected directly to the electrode of the second semiconductor element 3 through the solder bump 7.

配線構造体１０を挟んで第３主絶縁層２０６の上表面２０６ａの一方側（図６では、左側）には第１半導体素子２を実装するための第３実装パッド２１５、他方側（図６では、右側）には第２半導体素子３を実装するための第４実装パッド２１６が、それぞれ複数形成されている。第３実装パッド２１５は第３主絶縁層２０６の内部に設けられた第６主ビア導体２１９を介し、第４実装パッド２１６は第３主絶縁層２０６の内部に設けられた第７主ビア導体２２０を介し、第３主導体層２０５とそれぞれ電気的に接続されている。なお、第３実装パッド２１５及び第４実装パッド２１６の上表面は、同一平面に位置している。   A third mounting pad 215 for mounting the first semiconductor element 2 on one side (left side in FIG. 6) of the upper surface 206a of the third main insulating layer 206 across the wiring structure 10, and the other side (FIG. 6). Then, a plurality of fourth mounting pads 216 for mounting the second semiconductor element 3 are formed on the right side). The third mounting pad 215 is provided via a sixth main via conductor 219 provided in the third main insulating layer 206, and the fourth mounting pad 216 is provided as a seventh main via conductor provided in the third main insulating layer 206. Each of the third main conductor layers 205 is electrically connected via 220. Note that the upper surfaces of the third mounting pad 215 and the fourth mounting pad 216 are located on the same plane.

図６に示すように、本実施形態に係る配線構造体１０は主配線板２２より外部に突出するため、第１副導電パッド１０５及び第２副導電パッド１０６は、第３実装パッド２１５及び第４実装パッド２１６と比べて位置が高い。従って、第１半導体素子２及び第２半導体素子３が実装され場合には、これらの半導体素子２，３が第３主絶縁層２０６の上表面２０６ａと平行するように、配線構造体１０側の半田バンプ７と主配線板２２側の半田バンプ４との高さ（厚み）を調整する必要がある。   As shown in FIG. 6, since the wiring structure 10 according to the present embodiment protrudes from the main wiring board 22, the first sub conductive pad 105 and the second sub conductive pad 106 are connected to the third mounting pad 215 and the second mounting pad 215. The position is higher than that of the 4-mount pad 216. Therefore, when the first semiconductor element 2 and the second semiconductor element 3 are mounted, the semiconductor elements 2 and 3 on the wiring structure 10 side are parallel to the upper surface 206a of the third main insulating layer 206. It is necessary to adjust the height (thickness) of the solder bump 7 and the solder bump 4 on the main wiring board 22 side.

本実施形態に係る多層配線板６は、第１実施形態と異なり、ダミー配線からなる応力緩和部材１１０だけを有する。この応力緩和部材１１０は、第１副導電パッド１０５と第２副導電パッド１０６との間に位置する第３副絶縁層１０４の上表面１０４ａに設けられている。以上の構成を有する多層配線板６は、第１実施形態と同様な作用効果を得られる。   Unlike the first embodiment, the multilayer wiring board 6 according to the present embodiment has only the stress relaxation member 110 made of dummy wiring. The stress relaxation member 110 is provided on the upper surface 104 a of the third sub-insulating layer 104 located between the first sub-conductive pad 105 and the second sub-conductive pad 106. The multilayer wiring board 6 having the above configuration can obtain the same effects as those of the first embodiment.

＜第４実施形態＞
以下、図８を参照して本発明の第４実施形態を説明する。この実施形態に係る多層配線板８は、配線構造体１１がグランド層１１６を有し、グランド層１１６内に応力緩和部材１１３が配置される点において上述の第２実施形態と異なっているが、その他の構造等は第２実施形態と同様のため、重複する説明を省略する。 <Fourth embodiment>
The fourth embodiment of the present invention will be described below with reference to FIG. The multilayer wiring board 8 according to this embodiment is different from the above-described second embodiment in that the wiring structure 11 has a ground layer 116 and the stress relaxation member 113 is disposed in the ground layer 116. Since other structures and the like are the same as those of the second embodiment, redundant description is omitted.

具体的には、配線構造体１１は、第２副絶縁層１０２と第３副絶縁層１０４との間に配置された第４副絶縁層１１４を更に備える。第４副絶縁層１１４は、第２副絶縁層１０２及び第３副絶縁層１０４と同様に感光性樹脂からなる絶縁層である。この第４副絶縁層１１４には、第３副導体層１１５とグランド層１１６が設けられている。更に、グランド層１１６には、ダミー配線からなる応力緩和部材１１３が配置されている。本実施形態に係る多層配線板８は、第１実施形態と同様な作用効果を得られるほか、配線構造体１１の内部に更に応力緩和部材１１３が配置されるので、熱応力を緩和する効果を更に高めることができる。しかも、応力緩和部材１１３がグランド層１１６に設けられるので、応力緩和部材１１３の設置によって副導体層への影響を与えず、応力緩和部材１１３の設置場所を容易に確保することができる。   Specifically, the wiring structure 11 further includes a fourth sub-insulating layer 114 disposed between the second sub-insulating layer 102 and the third sub-insulating layer 104. The fourth sub-insulating layer 114 is an insulating layer made of a photosensitive resin like the second sub-insulating layer 102 and the third sub-insulating layer 104. The fourth sub-insulating layer 114 is provided with a third sub-conductor layer 115 and a ground layer 116. Further, a stress relaxation member 113 made of dummy wiring is disposed on the ground layer 116. The multilayer wiring board 8 according to the present embodiment can obtain the same effect as that of the first embodiment, and the stress relaxation member 113 is further arranged inside the wiring structure 11, so that the effect of relaxing the thermal stress can be achieved. It can be further increased. In addition, since the stress relaxation member 113 is provided on the ground layer 116, the installation location of the stress relaxation member 113 can be easily secured without affecting the sub conductor layer by the installation of the stress relaxation member 113.

＜第５実施形態＞
以下、図９を参照して本発明の第５実施形態を説明する。この実施形態に係る多層配線板９は、応力緩和樹脂層１１１を更に備える点において上述の第１実施形態と異なっているが、その他の構造等は第１実施形態と同様のため、重複する説明を省略する。 <Fifth Embodiment>
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG. The multilayer wiring board 9 according to this embodiment is different from the above-described first embodiment in that it further includes a stress relaxation resin layer 111, but the other structures and the like are the same as those of the first embodiment, and thus redundant description is made. Is omitted.

具体的には、配線構造体１０の第３副絶縁層１０４の上表面１０４ａには、応力緩和樹脂層１１１が形成されている。応力緩和樹脂層１１１は、第１副導電パッド１０５と第４主ビア導体２１７との導通、第２副導電パッド１０６と第５主ビア導体２１８との導通に影響を与えないように、第１副導電パッド１０５、第２副導電パッド１０６及び応力緩和部材１１０を取り囲んで形成されている。   Specifically, a stress relaxation resin layer 111 is formed on the upper surface 104 a of the third sub-insulating layer 104 of the wiring structure 10. The stress relaxation resin layer 111 is formed so as not to affect the conduction between the first sub-conductive pad 105 and the fourth main via conductor 217 and the conduction between the second sub-conductive pad 106 and the fifth main via conductor 218. The sub conductive pad 105, the second sub conductive pad 106 and the stress relaxation member 110 are surrounded.

応力緩和樹脂層１１１に用いられる材料として、主配線板２０の主絶縁層２０２，２０４，２０６，２０８及び配線構造体１０の副絶縁層１００，１０２，１０４のいずれよりも柔らかく、且つ残留応力が小さい樹脂材料であることが好適である。具体的には、応力緩和樹脂層１１１の材料として、例えば、ポリエステル樹脂、ポリイミド樹脂、エラストマー、ノルボルネン系樹脂、シリコーン系樹脂、ノボラック系樹脂、エポキシ系樹脂などが挙げられる。そして、ポリエステル樹脂を用いた場合、残留応力がポリブチレンテレフタレート樹脂の８０％以下であるものが好適である。   The material used for the stress relaxation resin layer 111 is softer than any of the main insulating layers 202, 204, 206, 208 of the main wiring board 20 and the sub insulating layers 100, 102, 104 of the wiring structure 10, and has a residual stress. A small resin material is preferable. Specifically, examples of the material of the stress relaxation resin layer 111 include polyester resin, polyimide resin, elastomer, norbornene resin, silicone resin, novolac resin, and epoxy resin. When a polyester resin is used, it is preferable that the residual stress is 80% or less of the polybutylene terephthalate resin.

本実施形態に係る多層配線板９は、第１実施形態と同様な作用効果を得られるほか、配線構造体１０の第３副絶縁層１０４の上表面１０４ａに応力緩和樹脂層１１１が更に形成されるため、多層配線板１と半導体素子２，３双方の材料の熱膨張率の違いによって生じる熱応力を緩和する効果を一層高めることができる。従って、クラックの発生及び配線構造体１０の副導体層１０１，１０３の断線を確実に防止することができる。   The multilayer wiring board 9 according to the present embodiment can obtain the same effects as the first embodiment, and further has a stress relaxation resin layer 111 formed on the upper surface 104a of the third sub-insulating layer 104 of the wiring structure 10. Therefore, the effect of relieving the thermal stress caused by the difference in thermal expansion coefficient between the materials of the multilayer wiring board 1 and the semiconductor elements 2 and 3 can be further enhanced. Therefore, generation of cracks and disconnection of the sub conductor layers 101 and 103 of the wiring structure 10 can be reliably prevented.

＜第６実施形態＞
以下、図１０を参照して本発明の第６実施形態を説明する。この実施形態に係る多層配線板３０と上述した第５実施形態との相違点は、応力緩和樹脂層２２３が主配線板２０の最外層に形成されることである。 <Sixth Embodiment>
The sixth embodiment of the present invention will be described below with reference to FIG. The difference between the multilayer wiring board 30 according to this embodiment and the fifth embodiment described above is that the stress relaxation resin layer 223 is formed in the outermost layer of the main wiring board 20.

具体的には、主配線板２０の最外層である第４主絶縁層２０８の上表面２０８ａには、応力緩和樹脂層２２３が形成されている。応力緩和樹脂層２２３は、第４主絶縁層２０８の上表面２０８ａに形成された第１実装パッド２１３及び第２実装パッド２１４の上表面を外部に露出するように、第１実装パッド２１３、第２実装パッド２１４及び応力緩和部材２２１を取り囲んでいる。また、応力緩和樹脂層２２３の上表面は、第１実装パッド２１３、第２実装パッド２１４及び応力緩和部材２２１の上表面と同一平面に位置している。このようにすれば、第１実装パッド２１３、第２実装パッド２１４及び応力緩和部材２２１の剥離を防止することができる。   Specifically, a stress relaxation resin layer 223 is formed on the upper surface 208a of the fourth main insulating layer 208, which is the outermost layer of the main wiring board 20. The stress relaxation resin layer 223 includes the first mounting pad 213, the first mounting pad 213, and the second mounting pad 214 so that the upper surfaces of the first mounting pad 213 and the second mounting pad 214 formed on the upper surface 208 a of the fourth main insulating layer 208 are exposed to the outside. 2 The mounting pad 214 and the stress relaxation member 221 are surrounded. The upper surface of the stress relaxation resin layer 223 is located on the same plane as the upper surfaces of the first mounting pad 213, the second mounting pad 214, and the stress relaxation member 221. In this way, peeling of the first mounting pad 213, the second mounting pad 214, and the stress relaxation member 221 can be prevented.

応力緩和樹脂層２２３は、第４主絶縁層２０８の上表面２０８ａ全面にわたって形成される必要はなく、少なくとも第１実装パッド２１３、第２実装パッド２１４及び応力緩和部材２２１の配置領域に形成されればよい。なお、応力緩和樹脂層２２３には、上述した応力緩和樹脂層１１１と同じ材料が用いられている。   The stress relaxation resin layer 223 does not need to be formed over the entire upper surface 208a of the fourth main insulating layer 208, and is formed at least in the arrangement region of the first mounting pad 213, the second mounting pad 214, and the stress relaxation member 221. That's fine. The stress relaxation resin layer 223 is made of the same material as the stress relaxation resin layer 111 described above.

本実施形態に係る多層配線板３０は、上述した第１実施形態と同様な作用効果を得られるほか、実装される半導体素子２，３による熱膨張や収縮の影響を最も受けやすい最外層である第４主絶縁層２０８の上表面２０８ａに応力緩和樹脂層２２３を形成することで、熱応力を緩和する効果をより一層高めることができる。   The multilayer wiring board 30 according to the present embodiment is the outermost layer that can obtain the same effects as those of the first embodiment described above and is most susceptible to thermal expansion and contraction by the mounted semiconductor elements 2 and 3. By forming the stress relaxation resin layer 223 on the upper surface 208a of the fourth main insulating layer 208, the effect of relaxing the thermal stress can be further enhanced.

＜第７実施形態＞
以下、図１１を参照して本発明の第７実施形態を説明する。この実施形態に係る多層配線板３１は、応力緩和樹脂層１１１を備える点において上述の第２実施形態と異なっているが、その他の構造等は第２実施形態と同様のため、重複する説明を省略する。 <Seventh embodiment>
Hereinafter, a seventh embodiment of the present invention will be described with reference to FIG. The multilayer wiring board 31 according to this embodiment is different from the above-described second embodiment in that the stress relaxation resin layer 111 is provided, but the other structures and the like are the same as those of the second embodiment, and thus redundant description is given. Omitted.

具体的には、多層配線板３１の最外層である配線構造体１０の第３副絶縁層１０４の上表面１０４ａには、応力緩和樹脂層１１１が形成されている。この応力緩和樹脂層１１１は、第３副絶縁層１０４の上表面１０４ａに形成された第１副導電パッド１０５及び第２副導電パッド１０６の上表面を外部に露出するように、第１副導電パッド１０５、第２副導電パッド１０６及び応力緩和部材１１０を取り囲んでいる。また、応力緩和樹脂層１１１の上表面は、第１副導電パッド１０５、第２副導電パッド１０６及び応力緩和部材１１０の上表面と同一平面に位置している。このようにすれば、第１副導電パッド１０５、第２副導電パッド１０６及び応力緩和部材１１０の剥離を防止することができる。   Specifically, a stress relaxation resin layer 111 is formed on the upper surface 104 a of the third sub-insulating layer 104 of the wiring structure 10 that is the outermost layer of the multilayer wiring board 31. The stress relaxation resin layer 111 is formed so that the upper surfaces of the first sub-conductive pad 105 and the second sub-conductive pad 106 formed on the upper surface 104a of the third sub-insulating layer 104 are exposed to the outside. The pad 105, the second sub conductive pad 106, and the stress relaxation member 110 are surrounded. Further, the upper surface of the stress relaxation resin layer 111 is located on the same plane as the upper surfaces of the first sub conductive pad 105, the second sub conductive pad 106 and the stress relaxation member 110. In this way, it is possible to prevent the first sub conductive pad 105, the second sub conductive pad 106, and the stress relaxation member 110 from being peeled off.

本実施形態に係る多層配線板３１は、第１実施形態と同様な作用効果を得られるほか、配線構造体１０の第３副絶縁層１０４の上表面１０４ａに応力緩和樹脂層１１１が形成されるため、配線構造体１０と半導体素子２，３双方の材料の熱膨張率の違いによって生じる熱応力を緩和する効果を一層高めることができる。従って、配線構造体１０でのクラックの発生及び副導体層１０１，１０３の断線を確実に防止することができる。   The multilayer wiring board 31 according to the present embodiment can obtain the same functions and effects as those of the first embodiment, and the stress relaxation resin layer 111 is formed on the upper surface 104a of the third sub-insulating layer 104 of the wiring structure 10. Therefore, it is possible to further enhance the effect of relieving thermal stress caused by the difference in thermal expansion coefficient between the wiring structure 10 and the semiconductor elements 2 and 3. Therefore, generation of cracks in the wiring structure 10 and disconnection of the sub conductor layers 101 and 103 can be reliably prevented.

＜第８実施形態＞
以下、図１２を参照して本発明の第８実施形態を説明する。この実施形態に係る多層配線板３２は、放熱部材１１２を備える点において上述の第１実施形態と異なっているが、その他の構造等は第１実施形態と同様のため、重複する説明を省略する。 <Eighth Embodiment>
Hereinafter, an eighth embodiment of the present invention will be described with reference to FIG. The multilayer wiring board 32 according to this embodiment is different from the above-described first embodiment in that it includes a heat radiating member 112, but the other structure and the like are the same as those of the first embodiment, and thus redundant description is omitted. .

具体的には、配線構造体１０のダイアタッチフィルム１０９が形成される側には、放熱部材１１２が設けられている。この放熱部材１１２は、ダイアタッチフィルム１０９及び第１副絶縁層１００の間に配置され、例えば銅めっきにより形成された金属めっき層であり、その厚さは１０〜８０μｍであることが好ましい。なお、放熱部材１１２は、上述した銅めっき層のほか、その他の金属メッキ層、金属板又はナノカーボン材料によって形成されてもよい。   Specifically, a heat radiating member 112 is provided on the side of the wiring structure 10 where the die attach film 109 is formed. The heat radiating member 112 is a metal plating layer that is disposed between the die attach film 109 and the first sub-insulating layer 100 and is formed by, for example, copper plating, and the thickness is preferably 10 to 80 μm. In addition to the copper plating layer described above, the heat dissipation member 112 may be formed of other metal plating layers, metal plates, or nanocarbon materials.

本実施形態に係る多層配線板３２は、上述した第１実施形態と同様な作用効果を得られるほか、配線構造体１０に放熱部材１１２が設けられるため、放熱部材１１２を介して半導体素子２，３の作動時に発生した熱を効率良く周囲に放出することができ、熱応力の発生を抑制する効果を奏する。これによって、熱応力による応力集中の発生を防止し、応力集中に起因するクラックの発生を確実に抑えることが可能になる。   The multilayer wiring board 32 according to the present embodiment can obtain the same effects as those of the first embodiment described above, and since the heat dissipation member 112 is provided in the wiring structure 10, the semiconductor element 2 is interposed via the heat dissipation member 112. The heat generated during the operation of 3 can be efficiently released to the surroundings, and the effect of suppressing the generation of thermal stress is achieved. As a result, the occurrence of stress concentration due to thermal stress can be prevented, and the occurrence of cracks due to stress concentration can be reliably suppressed.

以上、本発明の実施形態について詳述したが、本発明は、上述の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の精神を逸脱しない範囲で、種々の設計変更を行うことができるものである。例えば、上述の実施形態において、配線構造体の副絶縁層は感光性樹脂、主配線板の主絶縁層は熱硬化性エポキシ樹脂によってそれぞれ形成されたが、副絶縁層と主絶縁層とは同じ又は同等な熱膨張率を有する材料によって形成されてもよい。このように同じ又は同等な熱膨張率を有する材料を用いることで、材料の熱膨張率の違いによる熱応力の発生を防止することができ、クラックの発生を確実に抑制する効果を奏する。   Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various designs can be made without departing from the spirit of the present invention described in the claims. It can be changed. For example, in the above-described embodiment, the sub-insulating layer of the wiring structure is formed of a photosensitive resin and the main insulating layer of the main wiring board is formed of a thermosetting epoxy resin, but the sub-insulating layer and the main insulating layer are the same. Or you may form with the material which has an equivalent thermal expansion coefficient. Thus, by using the material which has the same or equivalent thermal expansion coefficient, generation | occurrence | production of the thermal stress by the difference in the thermal expansion coefficient of material can be prevented, and there exists an effect which suppresses generation | occurrence | production of a crack reliably.

また、主配線板２０側の応力緩和部材２２１は、必ずしも第４主絶縁層２０８の上表面２０８ａ及び上表面２０８ａ下方の双方に設ける必要はなく、上表面２０８ａの下方だけに設けてよい。例えば、第１実施形態に係る多層配線板１では、応力緩和部材２２１を設けずに、応力緩和部材１１０のみを設けてもよい。また、応力緩和部材は、必ずしも無電解めっき層及び電解めっき層によって構成されなくてもよく、その他のめっき層あるいは金属板によって構成されてもよい。更に、図１３に示すように、多層配線板１に第１半導体素子２及び第２半導体素子３が実装された場合、第１半導体素子２、第２半導体素子３及び多層配線板１の隙間にアンダーフィル材３３が充填されてもよい。このようにすれば、多層配線板１と半導体素子２，３双方の材料の熱膨張率の違いによって生じる熱応力を一層緩和することができ、クラックの発生を防止する効果を更に高めることができる。   The stress relaxation member 221 on the main wiring board 20 side is not necessarily provided on both the upper surface 208a and the lower surface 208a below the fourth main insulating layer 208, and may be provided only below the upper surface 208a. For example, in the multilayer wiring board 1 according to the first embodiment, only the stress relaxation member 110 may be provided without providing the stress relaxation member 221. Moreover, the stress relaxation member does not necessarily need to be comprised with an electroless-plating layer and an electrolytic plating layer, and may be comprised with another plating layer or a metal plate. Further, as shown in FIG. 13, when the first semiconductor element 2 and the second semiconductor element 3 are mounted on the multilayer wiring board 1, the gap between the first semiconductor element 2, the second semiconductor element 3 and the multilayer wiring board 1 is provided. The underfill material 33 may be filled. In this way, the thermal stress caused by the difference in thermal expansion coefficient between the materials of the multilayer wiring board 1 and the semiconductor elements 2 and 3 can be further relaxed, and the effect of preventing the occurrence of cracks can be further enhanced. .

また、以上の実施形態では、コア基板２００を有する主配線板２０をベースに説明したが、これに限らず、本発明はコア基板２００を有しないコアレス基板にも適用可能である。さらに、必要に応じて、多層配線板１の表面及び裏面にソルダーレジスト層を形成しても良い。また、応力緩和部材は、図３に示す一つの長方形の塊に限らず、例えば図１４に示すように複数の板状の応力緩和部材２２３を整列してなるものとしても良い。さらに、応力緩和部材の形状は長方形に限定されずに、円形、楕円形、正方形等の形状としても良い。   Moreover, although the above embodiment demonstrated based on the main wiring board 20 which has the core board | substrate 200, this invention is applicable not only to this but the coreless board | substrate which does not have the core board | substrate 200. FIG. Furthermore, you may form a soldering resist layer in the surface and back surface of the multilayer wiring board 1 as needed. Further, the stress relaxation member is not limited to the single rectangular block shown in FIG. 3, and a plurality of plate-like stress relaxation members 223 may be aligned as shown in FIG. 14, for example. Furthermore, the shape of the stress relaxation member is not limited to a rectangle, and may be a circle, an ellipse, a square, or the like.

１，５，６，８，９，３０，３１，３２ 多層配線板
１０，１１ 配線構造体
２０，２１，２２ 主配線板
３３ アンダーフィル材
１００ 第１副絶縁層
１０１ 第１副導体層
１０２ 第２副絶縁層
１０３ 第２副導体層
１０４ 第３副絶縁層
１０４ａ 上表面
１０５ 第１副導電パッド
１０６ 第２副導電パッド
１０９ ダイアタッチフィルム
１１０ 応力緩和部材
１１１ 応力緩和樹脂層
１１２ 放熱部材
１１３ 応力緩和部材
１１４ 第４副絶縁層
１１５ 第３副導体層
１１６ グランド層
２０１ 第１主導体層
２０２ 第１主絶縁層
２０３ 第２主導体層
２０４ 第２主絶縁層
２０５ 第３主導体層
２０６ 第３主絶縁層
２０７ 第４主導体層
２０８ 第４主絶縁層
２０８ａ 上表面
２１３ 第１実装パッド
２１４ 第２実装パッド
２１５ 第３実装パッド
２１６ 第４実装パッド
２２１ 応力緩和部材 1, 5, 6, 8, 9, 30, 31, 32 Multi-layer wiring board 10, 11 Wiring structure 20, 21, 22 Main wiring board 33 Underfill material 100 First sub-insulating layer 101 First sub-conductor layer 102 Second sub-insulating layer 103 Second sub-conductor layer 104 Third sub-insulating layer 104a Upper surface 105 First sub-conductive pad 106 Second sub-conductive pad 109 Die attach film 110 Stress relaxation member 111 Stress relaxation resin layer 112 Heat dissipation member 113 Stress relaxation Member 114 Fourth sub-insulating layer 115 Third sub-conductor layer 116 Ground layer 201 First main conductor layer 202 First main insulating layer 203 Second main conductor layer 204 Second main insulating layer 205 Third main conductor layer 206 Third main Insulating layer 207 Fourth main conductor layer 208 Fourth main insulating layer 208a Upper surface 213 First mounting pad 214 Second mounting pad 215 Third mounting pad 216 Fourth mounting pad 21 stress relaxation member

Claims (15)

主絶縁層と主導体層とを交互に積層してなる主配線板と、前記主配線板に搭載されるとともに前記主導体層の配線幅よりも狭い配線幅の副導体層を有する配線構造体とを備え、隣接する第１半導体素子及び第２半導体素子を実装するための多層配線板であって、
前記多層配線板の表面には、前記配線構造体の前記副導体層とそれぞれ電気的に接続され、前記第１半導体素子を実装するための複数の第１実装パッドと、前記第２半導体素子を実装するための複数の第２実装パッドとが形成され、
前記複数の第１実装パッドと前記複数の第２の実装パッドとの間には、前記表面及び該表面の下方の少なくとも一方に形成される応力緩和部材が配置されている。 A wiring structure having a main wiring board in which main insulating layers and main conductor layers are alternately laminated, and a sub-conductor layer mounted on the main wiring board and having a wiring width narrower than the wiring width of the main conductor layer A multilayer wiring board for mounting the adjacent first semiconductor element and second semiconductor element,
A plurality of first mounting pads for mounting the first semiconductor element, the second semiconductor element being electrically connected to the sub-conductor layer of the wiring structure, respectively, on the surface of the multilayer wiring board A plurality of second mounting pads for mounting are formed;
Between the plurality of first mounting pads and the plurality of second mounting pads, stress relaxation members formed on at least one of the surface and the lower side of the surface are arranged. 請求項１に記載の多層配線板において、
前記配線構造体は、前記主配線板の内部に埋設され、
前記第１実装パッド及び前記第２実装パッドは、前記主配線板に形成されている。 In the multilayer wiring board according to claim 1,
The wiring structure is embedded in the main wiring board,
The first mounting pad and the second mounting pad are formed on the main wiring board. 請求項１に記載の多層配線板において、
前記配線構造体は、外部に露出するように前記主配線板に搭載され、
前記第１実装パッド及び前記第２実装パッドは、前記配線構造体に形成されている。 In the multilayer wiring board according to claim 1,
The wiring structure is mounted on the main wiring board so as to be exposed to the outside,
The first mounting pad and the second mounting pad are formed in the wiring structure. 請求項１〜３のいずれか一項に記載の多層配線板において、
前記応力緩和部材は、前記第１実装パッド及び前記第２実装パッドと同じ材料によって形成されている。 In the multilayer wiring board according to any one of claims 1 to 3,
The stress relaxation member is made of the same material as the first mounting pad and the second mounting pad. 請求項１〜４のいずれか一項に記載の多層配線板において、
前記多層配線板の前記表面には、その表面に形成される前記第１実装パッド及び前記第２実装パッドを外部に露出するように応力緩和樹脂層が形成されている。 In the multilayer wiring board according to any one of claims 1 to 4,
A stress relaxation resin layer is formed on the surface of the multilayer wiring board so as to expose the first mounting pad and the second mounting pad formed on the surface. 請求項５に記載の多層配線板において、
前記配線構造体は、副絶縁層を有し、
前記応力緩和樹脂層は、前記主絶縁層及び前記副絶縁層のいずれよりも柔らく、且つ残留応力が小さい樹脂材料によって形成されている。 In the multilayer wiring board according to claim 5,
The wiring structure has a sub-insulating layer,
The stress relaxation resin layer is made of a resin material that is softer than both the main insulating layer and the sub insulating layer and has a small residual stress. 請求項５又は６に記載の多層配線板において、
前記第１実装パッド及び前記第２実装パッドの上表面と、前記応力緩和樹脂層の上表面とは、同一平面に位置している。 In the multilayer wiring board according to claim 5 or 6,
An upper surface of the first mounting pad and the second mounting pad and an upper surface of the stress relaxation resin layer are located on the same plane. 請求項５に記載の多層配線板において、
前記配線構造体は、前記主配線板の内部に埋設され、
前記配線構造体の最外層には、前記複数の第１実装パッドと対応する複数の第１副導電パッドと、前記複数の第２実装パッドと対応する複数の第２副導電パッドと、前記第１副導電パッド及び前記第２副導電パッドを取り囲む応力緩和樹脂層とが更に形成されている。 In the multilayer wiring board according to claim 5,
The wiring structure is embedded in the main wiring board,
The outermost layer of the wiring structure includes a plurality of first sub-conductive pads corresponding to the plurality of first mounting pads, a plurality of second sub-conductive pads corresponding to the plurality of second mounting pads, and the first A stress relaxation resin layer surrounding the first sub conductive pad and the second sub conductive pad is further formed. 請求項６〜８のいずれか一項に記載の多層配線板において、
前記副絶縁層は、前記主絶縁層と同じ又は同等な熱膨張率を有する材料によって形成されている。 In the multilayer wiring board as described in any one of Claims 6-8,
The sub-insulating layer is formed of a material having the same or equivalent coefficient of thermal expansion as the main insulating layer. 請求項１〜９のいずれか一項に記載の多層配線板において、
前記配線構造体はグランド層を有し、
前記応力緩和部材は、前記グランド層に配置されている。 In the multilayer wiring board according to any one of claims 1 to 9,
The wiring structure has a ground layer,
The stress relaxation member is disposed on the ground layer. 請求項１〜１０のいずれか一項に記載の多層配線板において、
前記配線構造体には、前記主配線板に固定するための接着層が形成されている。 In the multilayer wiring board according to any one of claims 1 to 10,
The wiring structure is formed with an adhesive layer for fixing to the main wiring board. 請求項１〜１１のいずれか一項に記載の多層配線板において、
前記配線構造体には、放熱部材が設けられている。 In the multilayer wiring board according to any one of claims 1 to 11,
The wiring structure is provided with a heat radiating member. 請求項１２に記載の多層配線板において、
前記放熱部材は、前記接着層が形成される側に設けられている。 In the multilayer wiring board according to claim 12,
The heat radiating member is provided on the side where the adhesive layer is formed. 請求項１２又は１３に記載の多層配線板において、
前記放熱部材は、金属板、金属めっき層又はナノカーボン材料によって形成されている。 In the multilayer wiring board according to claim 12 or 13,
The heat dissipation member is formed of a metal plate, a metal plating layer, or a nanocarbon material. 請求項１２〜１４のいずれか一項に記載の多層配線板において、
前記放熱部材の厚さは１０〜８０μｍである。 In the multilayer wiring board according to any one of claims 12 to 14,
The heat dissipation member has a thickness of 10 to 80 μm.
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