WO2022004403A1 - Multilayer wiring board and semiconductor device - Google Patents

Multilayer wiring board and semiconductor device Download PDF

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Publication number
WO2022004403A1
WO2022004403A1 PCT/JP2021/023000 JP2021023000W WO2022004403A1 WO 2022004403 A1 WO2022004403 A1 WO 2022004403A1 JP 2021023000 W JP2021023000 W JP 2021023000W WO 2022004403 A1 WO2022004403 A1 WO 2022004403A1
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Prior art keywords
semiconductor chip
layer
wiring board
metal
build
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PCT/JP2021/023000
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French (fr)
Japanese (ja)
Inventor
英幸 浅生
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凸版印刷株式会社
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Publication of WO2022004403A1 publication Critical patent/WO2022004403A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Definitions

  • the present invention relates to a multilayer wiring board and a semiconductor device.
  • the present application claims priority over Japanese Patent Application No. 2020-112371 filed in Japan on June 30, 2020 and Japanese Patent Application No. 2020-12935 filed in Japan on June 30, 2020, and the contents thereof. Is used here.
  • Patent Document 1 discloses a printed wiring board using a glass interposer.
  • the present invention is provided with a metal structure that is in contact with a semiconductor chip to release heat, and further is provided with a structure capable of transferring heat from the metal structure, thereby providing a multilayer wiring having good heat dissipation. It is an object of the present invention to provide a substrate and a semiconductor device.
  • the multilayer wiring board of the first aspect of the present invention has a core layer and a build-up layer, and a port in which a first semiconductor chip is mounted face-up and a contact portion with the first semiconductor chip is metal.
  • a conductor for heat dissipation arranged in the build-up layer, and a via structure for heat transfer arranged in the core layer.
  • the multilayer wiring board of the second aspect of the present invention has a core layer and a build-up layer, a port in which a first semiconductor chip is mounted face-up and a contact portion with the first semiconductor is metal, and a port.
  • the first aspect and the second aspect of the present invention are semiconductor devices including the multilayer wiring board, the first semiconductor chip, and the second semiconductor chip.
  • HBM High Bandwidth Memory
  • LSI Large-Scale Integrated circuit
  • FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention.
  • the semiconductor device 10 includes a plurality of semiconductor chips and a multilayer wiring board 1 on which the plurality of semiconductor chips are mounted.
  • Build-up layers 12 are arranged above and below the core layer 11 to form a multilayer wiring board 1.
  • each build-up layer 12 is composed of three layers L1, L2, and L3.
  • a first semiconductor chip 21 (HBM in the example of FIG. 1) is mounted on the upper surface of the upper build-up layer 12 face-up with the back surface facing the core layer 11. That is, the side of the first semiconductor chip 21 without the HBM connection pad faces the core layer 11.
  • the first semiconductor chip 21 is embedded in the L1 layer.
  • the first semiconductor chip 21 does not have to be embedded in the L1 layer.
  • a heat exhaust pad 22 which is a metal port for mounting the first semiconductor chip 21 face-up is arranged on the L1 layer directly below the first semiconductor chip 21, a heat exhaust pad 22 which is a metal port for mounting the first semiconductor chip 21 face-up is arranged.
  • the contact portion with the first semiconductor chip 21 is metal.
  • a heat exhaust via 23 made of metal and a flat heat exhaust plate 24 are arranged in the L2 layer directly below the L1 layer.
  • a heat exhaust via 25 made of metal and a flat heat exhaust plate 26 are arranged in the L3 layer directly below the L2 layer.
  • the heat exhaust via 23 and the heat exhaust via 25 are vias (conductors for heat dissipation) for floating potential heat dissipation.
  • a via structure 27 for heat transfer made of metal is arranged in the core layer 11 directly below the L3 layer.
  • the opening of the via structure 27 is circular.
  • the wall surface of the via structure 27 has a structure in which copper plating is deposited on the openings of holes vertically formed and the wall surface, and then the voids not plated with copper are filled with resin or metal paste.
  • the build-up layer 12 on the lower side also has a flat heat exhaust plate 26, a heat exhaust via 25, a flat heat exhaust plate 24, a heat exhaust via 23, and a flat surface.
  • the heat exhaust plate 29 is arranged.
  • a metal post 32 (joint structure) and a metal structure 33 are arranged on the upper surface of the upper build-up layer 12.
  • the second semiconductor chip 31 (LSI in the example of FIG. 1) is mounted face-down, and the metal post 32 is a second semiconductor chip 31 (LSI in the example of FIG. 1) mounted on the first semiconductor chip 21. It has a joint structure for mounting at a position higher than the height of. The height is the height in the arrangement direction of the core layer 11 and the build-up layer 12.
  • the metal structure 33 comes into contact with the housing of the second semiconductor chip 31.
  • the metal structure 33 comes into contact with the second semiconductor chip 31 to release heat.
  • the first semiconductor chip 21 and the second semiconductor chip 31 are connected by a connecting metal post 41.
  • a heat exhaust pad 34 made of metal is arranged in the L1 layer directly below the metal post 32 under the second semiconductor chip 31. Further, a heat exhaust via 35 made of metal and a flat heat exhaust plate 36 are arranged in the L2 layer directly below the L1 layer. Further, a heat exhaust via 37 made of metal and a flat heat exhaust plate 38 are arranged in the L3 layer directly below the L2 layer. As described above, the heat exhaust via 35 and the heat exhaust via 37 are vias (conductors) for heat dissipation of the floating potential.
  • a via structure 27 for heat transfer made of metal is arranged as in the case under the first semiconductor chip 21.
  • the build-up layer 12 on the lower side also has a flat heat exhaust plate 38, a heat exhaust via 37, a flat heat exhaust plate 36, a heat exhaust via 35, and a flat surface.
  • the heat exhaust plate 39 is arranged.
  • a metal heat exhaust pad 22 (metal structure) that is in contact with the semiconductor chip and releases heat is arranged.
  • a metal structure 33 that is in contact with the semiconductor chip and releases heat is arranged.
  • a waste heat via is formed under the semiconductor chip and is vertically connected to the opposite side surface.
  • FIG. 2A and 2B are schematic views of a semiconductor device according to the first embodiment of the present invention.
  • FIG. 2A is a cross-sectional view
  • FIG. 2B is an upper view.
  • FIG. 2A shows a third semiconductor chip 51 (LSI in FIG. 2A). Similar to the first semiconductor chip 21 and the second semiconductor chip 31, a heat exhaust via is formed under the semiconductor chip 51 under the third semiconductor chip 51, and is vertically connected to the opposite side surface. ing.
  • the multilayer wiring board 1 has a structure capable of transferring heat from the metal structure, heat is exhausted from the opposite surface side of the board.
  • FIGS. 3A and 3B are schematic views of a multilayer wiring board according to the first embodiment of the present invention.
  • FIG. 3A is a cross-sectional view
  • FIG. 3B is an upper view.
  • FIG. 4 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device 110 includes a plurality of semiconductor chips and a multilayer wiring board 101 on which the plurality of semiconductor chips are mounted.
  • Build-up layers 112 are arranged above and below the core layer 111 to form a multilayer wiring board 101.
  • each build-up layer 112 is composed of three layers L1, L2, and L3.
  • a first semiconductor chip 21 (HBM in the example of FIG. 4) is mounted on the upper surface of the upper build-up layer 112 face-up with the back surface facing the core layer 111 side. That is, the side of the first semiconductor chip 21 without the HBM connection pad faces the core layer 111.
  • the first semiconductor chip 21 is embedded in the L1 layer. The first semiconductor chip 21 does not have to be embedded in the L1 layer.
  • a heat exhaust pad 22 which is a metal port for mounting the first semiconductor chip 21 face-up is arranged on the L1 layer directly below the first semiconductor chip 21, a heat exhaust pad 22 which is a metal port for mounting the first semiconductor chip 21 face-up is arranged. Further, a heat exhaust via 23 made of metal and a flat heat exhaust plate 24 are arranged in the L2 layer directly below the L1 layer. Further, a heat exhaust via 25 made of metal is arranged in the L3 layer directly below the L2 layer.
  • a conductor block (metal block) 120 for heat transfer made of metal is embedded in the core layer 111 directly below the L3 layer.
  • the metal block 120 is connected to the heat exhaust via 25 and is located near the end face of the multilayer wiring board. As a result, the metal block 120 dissipates heat from the end face portion of the multilayer wiring board to the outer heat spreader heat sink 121.
  • the multilayer wiring board 101 includes a fixing pin hole 122 for fixing the outer heat spreader heat sink 121 with a fixing pin.
  • the lower structure of the second semiconductor chip 31 is the same as that of the first embodiment, the description thereof will be omitted. Since the lower side of the second semiconductor chip 31 has a structure capable of transferring heat from the metal structure, heat is exhausted from the opposite side of the substrate.
  • FIGS. 5A and 5B are schematic views of the semiconductor device according to the second embodiment of the present invention.
  • 5A is a cross-sectional view and FIG. 5B is an upper view.
  • FIGS. 5A and 5B show a third semiconductor chip 51 (LSI in FIG. 5A). Similar to the first semiconductor chip 21 and the second semiconductor chip 31, a heat exhaust via is formed under the semiconductor chip 51 under the third semiconductor chip 51, and is vertically connected to the opposite side surface. ing.
  • the multilayer wiring board 101 has a structure capable of transferring heat from the metal structure, heat is exhausted from the opposite surface side of the board.
  • FIGS. 6A and 6B are schematic views of a multilayer wiring board according to a second embodiment of the present invention.
  • FIG. 6A is a cross-sectional view
  • FIG. 6B is an upper view.
  • FIG. 7 is a cross-sectional view of the semiconductor device according to the embodiment of the present invention.
  • the semiconductor device 610 includes a plurality of semiconductor chips and a multilayer wiring board 600 on which the plurality of semiconductor chips are mounted.
  • Build-up layers 612 are arranged above and below the core layer 611 to form a multilayer wiring board 600.
  • each build-up layer 612 is composed of three layers L1, L2, and L3.
  • a first semiconductor chip 210 (HBM in the example of FIG. 7) is mounted on the upper surface of the upper build-up layer 612 face-up with the back surface facing the core layer 611. That is, the side of the first semiconductor chip 210 without the connection pad of the HBM faces the core layer 611.
  • the first semiconductor chip 210 is embedded in the L1 layer.
  • the first semiconductor chip 210 may not be embedded in the L1 layer.
  • a heat exhaust pad 220 which is a metal port for mounting the first semiconductor chip 210 face-up, is arranged on the L1 layer directly below the first semiconductor chip 210.
  • the contact portion with the first semiconductor chip 210 is made of metal.
  • a flat heat exhaust plate 240 made of metal is arranged in the L2 layer directly below the L1 layer.
  • a flat heat exhaust plate 260 made of metal is arranged in the L3 layer directly below the L2 layer.
  • a via structure 270 for heat transfer made of metal is arranged in the core layer 611 directly below the L3 layer.
  • the opening of the via structure 270 is circular.
  • the wall surface of the via structure 270 has a structure in which copper plating is deposited on the openings of holes vertically formed and the wall surface, and then the voids not plated with copper are filled with resin or metal paste.
  • a flat heat exhaust plate 260, a flat heat exhaust plate 240, and a flat heat exhaust plate 290 are arranged on the build-up layer 612 on the lower side (opposite surface side).
  • a metal post 320 (joint structure) and a metal structure 330 are arranged on the upper surface of the upper build-up layer 612.
  • the second semiconductor chip 310 (LSI in the example of FIG. 7) is mounted face-down.
  • the metal post 320 has a bonding structure for mounting the second semiconductor chip 310 (LSI in the example of FIG. 7) at a position higher than the height of the first semiconductor chip 210.
  • the height is the height in the arrangement direction of the core layer 611 and the build-up layer 612.
  • the metal structure 330 comes into contact with the housing of the second semiconductor chip 310.
  • the metal structure 330 is in contact with the second semiconductor chip 310 to dissipate heat.
  • the first semiconductor chip 210 and the second semiconductor chip 310 are connected by a connecting metal post 410.
  • a heat exhaust pad 340 made of metal is arranged in the L1 layer directly below the metal post 320 under the second semiconductor chip 310. Further, in the L2 layer directly below the L1 layer, a heat exhaust via (conductive via) 350 made of metal and a flat heat exhaust plate 360 are arranged. Further, in the L3 layer directly below the L2 layer, a heat exhaust via (conductive via) 370 made of metal and a flat heat exhaust plate 380 are arranged. As described above, the heat exhaust via 350 and the heat exhaust via 370 are vias (conductors) for heat dissipation of the floating potential.
  • a via structure 270 for heat transfer made of metal is arranged as in the case under the first semiconductor chip 210.
  • the build-up layer 612 on the lower side also has a flat heat exhaust plate 380, a heat exhaust via (conductive via) 370, a flat heat exhaust plate 360, and a heat exhaust via. (Conductive via) 350 and a flat heat exhaust plate 390 are arranged.
  • a metal heat exhaust pad 220 (metal structure) that is in contact with the semiconductor chip and releases heat is arranged.
  • a metal structure 330 that is in contact with the semiconductor chip and releases heat is arranged. Since the multilayer wiring board 600 has a via structure 270 for heat transfer in the core layer 611, heat is exhausted from the opposite surface side of the board.
  • the build-up layer 612 immediately below the first semiconductor chip 210 has no via structure, there is little distortion of the substrate, and the surface of the substrate has less unevenness caused by the presence or absence of the via structure, so that the mounting surface is smooth. Is good.
  • the heat transfer is slower than the structure in which the upper and lower parts are connected by metal, and the speed of heat transfer to the insulating resin of the build-up layer can be delayed (adjusted).
  • FIG. 8A and 8B are schematic views of a semiconductor device according to an embodiment of the present invention.
  • FIG. 8A is a cross-sectional view
  • FIG. 8B is an upper view.
  • FIG. 8A shows a third semiconductor chip 510 (LSI in FIG. 8A). Similar to the second semiconductor chip 310, a heat exhaust via is formed under the semiconductor chip under the third semiconductor chip 510, and is vertically connected to the opposite side surface.
  • the multilayer wiring board 600 has a structure capable of transferring heat from the metal structure, heat is exhausted from the opposite surface side of the board.
  • FIGS. 9A and 9B are schematic views of a multilayer wiring board according to an embodiment of the present invention.
  • 9A is a cross-sectional view and FIG. 9B is an upper view.
  • the semiconductor device shown in FIGS. 8A and 8B can be obtained.

Abstract

A multilayer wiring board comprising a core layer and a build-up layer. The multilayer wiring board further comprises: a port on which a first semiconductor chip is mounted face-up and of which a portion in contact with the first semiconductor is made of metal; a bonded structure on which a second semiconductor chip is mounted in a position higher than the height of the first semiconductor chip; a metal structure connecting a housing of the second semiconductor chip and the build-up layer; a heat-dissipating conductor disposed on the build-up layer; and a heat-dissipating via structure disposed on the core layer.

Description

多層配線基板および半導体装置Multilayer wiring board and semiconductor device
　本発明は、多層配線基板および半導体装置に関する。
　本願は、２０２０年６月３０日に日本に出願された特願２０２０－１１２３７１号及び２０２０年６月３０日に日本に出願された特願２０２０－１１２９３５号について優先権を主張し、これらの内容をここに援用する。 The present invention relates to a multilayer wiring board and a semiconductor device.
The present application claims priority over Japanese Patent Application No. 2020-112371 filed in Japan on June 30, 2020 and Japanese Patent Application No. 2020-12935 filed in Japan on June 30, 2020, and the contents thereof. Is used here.
　近年、更なるビッグデータを扱う半導体実装基板において、大容量メモリとロジックチップの１パッケージ化は必須であり、大型シリコンチップ、ガラスインターポーザ、有機基板上の薄膜・微小配線形成など様々なアプローチが実施・検討されている。例えば特許文献１は、ガラスインターポーザを用いたプリント配線板を開示している。 In recent years, it has become essential to package a large-capacity memory and a logic chip into one package for semiconductor mounting boards that handle even larger data, and various approaches such as large silicon chips, glass interposers, and thin film / micro wiring formation on organic boards have been implemented.・ It is being considered. For example, Patent Document 1 discloses a printed wiring board using a glass interposer.
日本国特開２０１６－５１８４７号公報Japanese Patent Application Laid-Open No. 2016-51847
　特許文献１に記載のプリント配線板において、ガラスインターポーザを内部に埋め込むとコプラナリティを取るのが難しい。コプラナリティを取るためにガラスインターポーザを表面に置くと、実装する半導体チップが宙に浮くので、放熱性がよくない。すなわち、特許文献１では、半導体チップの実装性を高めるため、放熱性が不十分である。 In the printed wiring board described in Patent Document 1, it is difficult to obtain coplanarity if a glass interposer is embedded inside. If a glass interposer is placed on the surface for coplanarity, the semiconductor chip to be mounted floats in the air, resulting in poor heat dissipation. That is, in Patent Document 1, heat dissipation is insufficient in order to improve the mountability of the semiconductor chip.
　そこでこの発明は、上述の課題を解決するため、半導体チップに接して熱を逃がす金属の構造体を備え、さらに金属の構造体から伝熱可能な構成を備えることにより、放熱性の良い多層配線基板および半導体装置を提供することを目的としている。 Therefore, in order to solve the above-mentioned problems, the present invention is provided with a metal structure that is in contact with a semiconductor chip to release heat, and further is provided with a structure capable of transferring heat from the metal structure, thereby providing a multilayer wiring having good heat dissipation. It is an object of the present invention to provide a substrate and a semiconductor device.
　本発明の第１態様の多層配線基板は、コア層とビルドアップ層とを有し、第１の半導体チップがフェイスアップで実装され、前記第１の半導体チップとの接触部が金属であるポートと、第２の半導体チップが前記第１の半導体チップの高さよりも高い位置で実装される接合構造と、前記第２の半導体チップの筐体と前記ビルドアップ層とを接続する金属の構造体と、前記ビルドアップ層に配置された放熱用の導体と、前記コア層に配置された伝熱用のビア構造と、を有している。 The multilayer wiring board of the first aspect of the present invention has a core layer and a build-up layer, and a port in which a first semiconductor chip is mounted face-up and a contact portion with the first semiconductor chip is metal. A bonding structure in which the second semiconductor chip is mounted at a position higher than the height of the first semiconductor chip, and a metal structure connecting the housing of the second semiconductor chip and the build-up layer. And a conductor for heat dissipation arranged in the build-up layer, and a via structure for heat transfer arranged in the core layer.
　本発明の第２態様の多層配線基板は、コア層とビルドアップ層とを有し、第１の半導体チップがフェイスアップで実装され、第１の半導体との接触部が金属であるポートと、第２の半導体チップが前記第１の半導体チップの高さよりも高い位置で実装される接合構造と、前記第２の半導体チップの筐体と前記ビルドアップ層とを接続する金属の構造体と、前記第１の半導体チップの直下の前記ビルドアップ層に配置された金属ブレーン層と、前記第２の半導体チップの直下の前記ビルドアップ層に配置された導電ビアと、前記コア層に配置された伝熱用のビア構造と、を有している。 The multilayer wiring board of the second aspect of the present invention has a core layer and a build-up layer, a port in which a first semiconductor chip is mounted face-up and a contact portion with the first semiconductor is metal, and a port. A bonding structure in which the second semiconductor chip is mounted at a position higher than the height of the first semiconductor chip, a metal structure connecting the housing of the second semiconductor chip and the build-up layer, and the like. A metal brain layer arranged in the build-up layer directly below the first semiconductor chip, a conductive via arranged in the build-up layer directly below the second semiconductor chip, and a core layer arranged in the core layer. It has a via structure for heat transfer.
　本発明の第１態様及び第２態様は、前記多層配線基板と、前記第１の半導体チップと、前記第２の半導体チップと、を備える半導体装置である。 The first aspect and the second aspect of the present invention are semiconductor devices including the multilayer wiring board, the first semiconductor chip, and the second semiconductor chip.
　本発明によれば、ＨＢＭ（High Bandwidth Memory）やそれに付随する超多ピンＬＳＩ（Large-Scale Integrated circuit）が実装しやすい。さらに、これらの半導体チップが発する熱を、直接接触している配線基板を通して放熱することができるので、従来、実装した半導体チップ周辺を覆うように搭載していた放熱機構を用いずに、高い放熱性を得ることができる。これにより、高速動作を長時間安定して続けることができる多層配線基板および半導体装置を、生産性よく提供することが可能となる。 According to the present invention, HBM (High Bandwidth Memory) and its associated ultra-multi-pin LSI (Large-Scale Integrated circuit) can be easily mounted. Furthermore, since the heat generated by these semiconductor chips can be dissipated through the wiring board that is in direct contact with the semiconductor chips, high heat dissipation is possible without using a heat dissipation mechanism that is conventionally mounted so as to cover the periphery of the mounted semiconductor chip. You can get sex. This makes it possible to provide a multilayer wiring board and a semiconductor device capable of stably continuing high-speed operation for a long period of time with high productivity.
本発明の第１の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の模式図である。It is a schematic diagram of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の模式図である。It is a schematic diagram of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１の実施形態に係る多層配線基板の模式図である。It is a schematic diagram of the multilayer wiring board which concerns on 1st Embodiment of this invention. 本発明の第１の実施形態に係る多層配線基板の模式図である。It is a schematic diagram of the multilayer wiring board which concerns on 1st Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置の模式図である。It is a schematic diagram of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置の模式図である。It is a schematic diagram of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第２の実施形態に係る多層配線基板の模式図である。It is a schematic diagram of the multilayer wiring board which concerns on 2nd Embodiment of this invention. 本発明の第２の実施形態に係る多層配線基板の模式図である。It is a schematic diagram of the multilayer wiring board which concerns on 2nd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の模式図である。It is a schematic diagram of the semiconductor device which concerns on 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の模式図である。It is a schematic diagram of the semiconductor device which concerns on 3rd Embodiment of this invention. 本発明の第３の実施形態に係る多層配線基板の模式図である。It is a schematic diagram of the multilayer wiring board which concerns on 3rd Embodiment of this invention. 本発明の第３の実施形態に係る多層配線基板の模式図である。It is a schematic diagram of the multilayer wiring board which concerns on 3rd Embodiment of this invention.
　以下、本発明の実施形態による半導体装置および配線基板を、図面を参照して説明する。 Hereinafter, the semiconductor device and the wiring board according to the embodiment of the present invention will be described with reference to the drawings.
　（第１の実施形態）
　図１は、本発明の第１の実施形態に係る半導体装置の断面図である。半導体装置１０は、複数の半導体チップと、複数の半導体チップを実装する多層配線基板１とを備える。コア層１１の上下にビルドアップ層１２が配置されて、多層配線基板１が構成されている。図１の例では、各々のビルドアップ層１２は、Ｌ１、Ｌ２、Ｌ３の３層から構成されている。 (First Embodiment)
FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. The semiconductor device 10 includes a plurality of semiconductor chips and a multilayer wiring board 1 on which the plurality of semiconductor chips are mounted. Build-up layers 12 are arranged above and below the core layer 11 to form a multilayer wiring board 1. In the example of FIG. 1, each build-up layer 12 is composed of three layers L1, L2, and L3.
　上側のビルドアップ層１２の上面には、第１の半導体チップ２１（図１の例ではＨＢＭ）が、フェイスアップで、背面をコア層１１側にして実装される。すなわち、第１の半導体チップ２１のＨＢＭの接続パッドのない側が、コア層１１に向いている。図１では、第１の半導体チップ２１がＬ１層に埋め込まれている。第１の半導体チップ２１は、Ｌ１層に埋め込まれていなくてもよい。 A first semiconductor chip 21 (HBM in the example of FIG. 1) is mounted on the upper surface of the upper build-up layer 12 face-up with the back surface facing the core layer 11. That is, the side of the first semiconductor chip 21 without the HBM connection pad faces the core layer 11. In FIG. 1, the first semiconductor chip 21 is embedded in the L1 layer. The first semiconductor chip 21 does not have to be embedded in the L1 layer.
　第１の半導体チップ２１の直下のＬ１層には、第１の半導体チップ２１をフェイスアップで実装するための金属のポートである排熱用パッド２２が配置されている。排熱用パッド２２において、第１の半導体チップ２１との接触部が金属である。さらにＬ１層の直下のＬ２層には、金属からなる排熱用ビア２３と平面状の排熱板２４が配置されている。さらにＬ２層の直下のＬ３層には、金属からなる排熱用ビア２５と平面状の排熱板２６が配置されている。このように、排熱用ビア２３および排熱用ビア２５は、フローティング電位放熱用のビア（放熱用の導体）である。 On the L1 layer directly below the first semiconductor chip 21, a heat exhaust pad 22 which is a metal port for mounting the first semiconductor chip 21 face-up is arranged. In the heat exhaust pad 22, the contact portion with the first semiconductor chip 21 is metal. Further, a heat exhaust via 23 made of metal and a flat heat exhaust plate 24 are arranged in the L2 layer directly below the L1 layer. Further, a heat exhaust via 25 made of metal and a flat heat exhaust plate 26 are arranged in the L3 layer directly below the L2 layer. As described above, the heat exhaust via 23 and the heat exhaust via 25 are vias (conductors for heat dissipation) for floating potential heat dissipation.
　さらにＬ３層の直下のコア層１１には、金属からなる伝熱用のビア構造２７が配置されている。ビア構造２７の開口部は、円形である。ビア構造２７の壁面が垂直に開けられた孔の開口部および壁面に銅めっきを析出させた後、銅めっきされなかった空隙部に樹脂または金属ペーストを充填した構造をしている。下側（反対面側）のビルドアップ層１２にも、上側と同様に、平面状の排熱板２６、排熱用ビア２５、平面状の排熱板２４、排熱用ビア２３、平面状の排熱板２９が配置されている。 Further, a via structure 27 for heat transfer made of metal is arranged in the core layer 11 directly below the L3 layer. The opening of the via structure 27 is circular. The wall surface of the via structure 27 has a structure in which copper plating is deposited on the openings of holes vertically formed and the wall surface, and then the voids not plated with copper are filled with resin or metal paste. Similarly to the upper side, the build-up layer 12 on the lower side (opposite surface side) also has a flat heat exhaust plate 26, a heat exhaust via 25, a flat heat exhaust plate 24, a heat exhaust via 23, and a flat surface. The heat exhaust plate 29 is arranged.
　上側のビルドアップ層１２の上面には、金属ポスト３２（接合構造）と、金属の構造体３３とが配置されている。第２の半導体チップ３１（図１の例ではＬＳＩ）は、フェイスダウンで実装されており、金属ポスト３２は、第２の半導体チップ３１（図１の例ではＬＳＩ）を第１の半導体チップ２１の高さよりも高い位置で実装するための接合構造を有している。なお、高さとは、コア層１１及びビルドアップ層１２の配列方向における高さである。金属の構造体３３は、第２の半導体チップ３１の筐体と接触する。金属の構造体３３は、第２の半導体チップ３１に接して熱を逃がす。第１の半導体チップ２１と第２の半導体チップ３１とは、接続用金属ポスト４１で接続される。 A metal post 32 (joint structure) and a metal structure 33 are arranged on the upper surface of the upper build-up layer 12. The second semiconductor chip 31 (LSI in the example of FIG. 1) is mounted face-down, and the metal post 32 is a second semiconductor chip 31 (LSI in the example of FIG. 1) mounted on the first semiconductor chip 21. It has a joint structure for mounting at a position higher than the height of. The height is the height in the arrangement direction of the core layer 11 and the build-up layer 12. The metal structure 33 comes into contact with the housing of the second semiconductor chip 31. The metal structure 33 comes into contact with the second semiconductor chip 31 to release heat. The first semiconductor chip 21 and the second semiconductor chip 31 are connected by a connecting metal post 41.
　第２の半導体チップ３１の下の金属ポスト３２の直下のＬ１層には、金属からなる排熱用パッド３４が配置されている。さらにＬ１層の直下のＬ２層には、金属からなる排熱用ビア３５と平面状の排熱板３６が配置されている。さらにＬ２層の直下のＬ３層には、金属からなる排熱用ビア３７と平面状の排熱板３８が配置されている。このように、排熱用ビア３５および排熱用ビア３７は、フローティング電位放熱用のビア（導体）である。 A heat exhaust pad 34 made of metal is arranged in the L1 layer directly below the metal post 32 under the second semiconductor chip 31. Further, a heat exhaust via 35 made of metal and a flat heat exhaust plate 36 are arranged in the L2 layer directly below the L1 layer. Further, a heat exhaust via 37 made of metal and a flat heat exhaust plate 38 are arranged in the L3 layer directly below the L2 layer. As described above, the heat exhaust via 35 and the heat exhaust via 37 are vias (conductors) for heat dissipation of the floating potential.
　さらにＬ３層の直下のコア層１１には、第１の半導体チップ２１の下と同様に、金属からなる伝熱用のビア構造２７が配置されている。下側（反対面側）のビルドアップ層１２にも、上側と同様に、平面状の排熱板３８、排熱用ビア３７、平面状の排熱板３６、排熱用ビア３５、平面状の排熱板３９が配置されている。 Further, in the core layer 11 directly below the L3 layer, a via structure 27 for heat transfer made of metal is arranged as in the case under the first semiconductor chip 21. Similarly to the upper side, the build-up layer 12 on the lower side (opposite surface side) also has a flat heat exhaust plate 38, a heat exhaust via 37, a flat heat exhaust plate 36, a heat exhaust via 35, and a flat surface. The heat exhaust plate 39 is arranged.
　第１の半導体チップ２１の直下には、半導体チップに接して熱を逃がす金属の排熱用パッド２２（金属の構造体）が配置されている。第２の半導体チップ３１の直下には、半導体チップに接して熱を逃がす金属の構造体３３が配置されている。半導体チップの下に、排熱用ビアが形成されていて、反対側面まで垂直に接続されている。これにより、多層配線基板１は、金属の構造体から伝熱可能な構成を備えているため、基板の反対面側から排熱が行われる。 Immediately below the first semiconductor chip 21, a metal heat exhaust pad 22 (metal structure) that is in contact with the semiconductor chip and releases heat is arranged. Immediately below the second semiconductor chip 31, a metal structure 33 that is in contact with the semiconductor chip and releases heat is arranged. A waste heat via is formed under the semiconductor chip and is vertically connected to the opposite side surface. As a result, since the multilayer wiring board 1 has a structure capable of transferring heat from the metal structure, heat is exhausted from the opposite surface side of the board.
　図２Ａ及び図２Ｂは、本発明の第１の実施形態に係る半導体装置の模式図である。図２Ａは断面図であり、図２Ｂは上視図である。図１に示す半導体装置に加えて、図２Ａでは、第３の半導体チップ５１（図２ＡではＬＳＩ）が示されている。第３の半導体チップ５１の下も、第１の半導体チップ２１、第２の半導体チップ３１と同様に、半導体チップの下に、排熱用ビアが形成されていて、反対側面まで垂直に接続されている。これにより、多層配線基板１は、金属の構造体から伝熱可能な構成を備えているため、基板の反対面側から排熱が行われる。 2A and 2B are schematic views of a semiconductor device according to the first embodiment of the present invention. FIG. 2A is a cross-sectional view, and FIG. 2B is an upper view. In addition to the semiconductor device shown in FIG. 1, FIG. 2A shows a third semiconductor chip 51 (LSI in FIG. 2A). Similar to the first semiconductor chip 21 and the second semiconductor chip 31, a heat exhaust via is formed under the semiconductor chip 51 under the third semiconductor chip 51, and is vertically connected to the opposite side surface. ing. As a result, since the multilayer wiring board 1 has a structure capable of transferring heat from the metal structure, heat is exhausted from the opposite surface side of the board.
　図３Ａ及び図３Ｂは、本発明の第１の実施形態に係る多層配線基板の模式図である。図３Ａは断面図であり、図３Ｂは上視図である。図３Ａ及び図３Ｂに示す多層配線基板に、半導体チップを実装することで、図２Ａ及び図２Ｂに示す半導体装置となる。 3A and 3B are schematic views of a multilayer wiring board according to the first embodiment of the present invention. FIG. 3A is a cross-sectional view, and FIG. 3B is an upper view. By mounting the semiconductor chip on the multilayer wiring board shown in FIGS. 3A and 3B, the semiconductor device shown in FIGS. 2A and 2B can be obtained.
　（第２の実施形態）
　図４は、本発明の第２の実施形態に係る半導体装置の断面図である。半導体装置１１０は、複数の半導体チップと、複数の半導体チップを実装する多層配線基板１０１とを備える。コア層１１１の上下にビルドアップ層１１２が配置されて、多層配線基板１０１が構成されている。図４の例では、各々のビルドアップ層１１２は、Ｌ１、Ｌ２、Ｌ３の３層から構成されている。 (Second embodiment)
FIG. 4 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention. The semiconductor device 110 includes a plurality of semiconductor chips and a multilayer wiring board 101 on which the plurality of semiconductor chips are mounted. Build-up layers 112 are arranged above and below the core layer 111 to form a multilayer wiring board 101. In the example of FIG. 4, each build-up layer 112 is composed of three layers L1, L2, and L3.
　上側のビルドアップ層１１２の上面には、第１の半導体チップ２１（図４の例ではＨＢＭ）が、フェイスアップで、背面をコア層１１１側にして実装される。すなわち、第１の半導体チップ２１のＨＢＭの接続パッドのない側が、コア層１１１に向いている。図４では、第１の半導体チップ２１がＬ１層に埋め込まれている。第１の半導体チップ２１は、Ｌ１層に埋め込まれていなくてもよい。 A first semiconductor chip 21 (HBM in the example of FIG. 4) is mounted on the upper surface of the upper build-up layer 112 face-up with the back surface facing the core layer 111 side. That is, the side of the first semiconductor chip 21 without the HBM connection pad faces the core layer 111. In FIG. 4, the first semiconductor chip 21 is embedded in the L1 layer. The first semiconductor chip 21 does not have to be embedded in the L1 layer.
　第１の半導体チップ２１の直下のＬ１層には、第１の半導体チップ２１をフェイスアップで実装するための金属のポートである排熱用パッド２２が配置されている。さらにＬ１層の直下のＬ２層には、金属からなる排熱用ビア２３と平面状の排熱板２４が配置されている。さらにＬ２層の直下のＬ３層には、金属からなる排熱用ビア２５が配置されている。 On the L1 layer directly below the first semiconductor chip 21, a heat exhaust pad 22 which is a metal port for mounting the first semiconductor chip 21 face-up is arranged. Further, a heat exhaust via 23 made of metal and a flat heat exhaust plate 24 are arranged in the L2 layer directly below the L1 layer. Further, a heat exhaust via 25 made of metal is arranged in the L3 layer directly below the L2 layer.
　さらにＬ３層の直下のコア層１１１には、金属からなる伝熱用の導体ブロック（金属ブロック）１２０が埋め込まれている。金属ブロック１２０は、排熱用ビア２５と接続しており、多層配線基板の端面近くに位置する。これにより、金属ブロック１２０が、多層配線基板端面部から、外側のヒートスプレッダ・ヒートシンク１２１に放熱する。多層配線基板１０１は、外側のヒートスプレッダ・ヒートシンク１２１を固定ピンで固定するための、固定ピン穴１２２を備える。 Further, a conductor block (metal block) 120 for heat transfer made of metal is embedded in the core layer 111 directly below the L3 layer. The metal block 120 is connected to the heat exhaust via 25 and is located near the end face of the multilayer wiring board. As a result, the metal block 120 dissipates heat from the end face portion of the multilayer wiring board to the outer heat spreader heat sink 121. The multilayer wiring board 101 includes a fixing pin hole 122 for fixing the outer heat spreader heat sink 121 with a fixing pin.
　第２の半導体チップ３１の下側の構造は、第１の実施形態と同様なので、説明を省略する。第２の半導体チップ３１の下側は、金属の構造体から伝熱可能な構成であるため、基板の反対面側から排熱が行われる。 Since the lower structure of the second semiconductor chip 31 is the same as that of the first embodiment, the description thereof will be omitted. Since the lower side of the second semiconductor chip 31 has a structure capable of transferring heat from the metal structure, heat is exhausted from the opposite side of the substrate.
　図５Ａ及び図５Ｂは、本発明の第２の実施形態に係る半導体装置の模式図である。図５Ａは断面図であり、図５Ｂは上視図である。図４に示す半導体装置に加えて、図５Ａ及び図５Ｂでは、第３の半導体チップ５１（図５ＡではＬＳＩ）が示されている。第３の半導体チップ５１の下も、第１の半導体チップ２１、第２の半導体チップ３１と同様に、半導体チップの下に、排熱用ビアが形成されていて、反対側面まで垂直に接続されている。これにより、多層配線基板１０１は、金属の構造体から伝熱可能な構成を備えているため、基板の反対面側から排熱が行われる。 5A and 5B are schematic views of the semiconductor device according to the second embodiment of the present invention. 5A is a cross-sectional view and FIG. 5B is an upper view. In addition to the semiconductor device shown in FIG. 4, FIGS. 5A and 5B show a third semiconductor chip 51 (LSI in FIG. 5A). Similar to the first semiconductor chip 21 and the second semiconductor chip 31, a heat exhaust via is formed under the semiconductor chip 51 under the third semiconductor chip 51, and is vertically connected to the opposite side surface. ing. As a result, since the multilayer wiring board 101 has a structure capable of transferring heat from the metal structure, heat is exhausted from the opposite surface side of the board.
　図６Ａ及び図６Ｂは、本発明の第２の実施形態に係る多層配線基板の模式図である。図６Ａは断面図であり、図６Ｂは上視図である。図６Ａ及び図６Ｂに示す多層配線基板に、半導体チップを実装することで、図５Ａ及び図５Ｂに示す半導体装置となる。 6A and 6B are schematic views of a multilayer wiring board according to a second embodiment of the present invention. FIG. 6A is a cross-sectional view, and FIG. 6B is an upper view. By mounting the semiconductor chip on the multilayer wiring board shown in FIGS. 6A and 6B, the semiconductor device shown in FIGS. 5A and 5B can be obtained.
（第３実施形態）
　以下、本発明の実施形態による半導体装置および配線基板を、図面を参照して説明する。 (Third Embodiment)
Hereinafter, the semiconductor device and the wiring board according to the embodiment of the present invention will be described with reference to the drawings.
　図７は、本発明の実施形態に係る半導体装置の断面図である。半導体装置６１０は、複数の半導体チップと、複数の半導体チップを実装する多層配線基板６００とを備える。コア層６１１の上下にビルドアップ層６１２が配置されて、多層配線基板６００が構成されている。図７の例では、各々のビルドアップ層６１２は、Ｌ１、Ｌ２、Ｌ３の３層から構成されている。 FIG. 7 is a cross-sectional view of the semiconductor device according to the embodiment of the present invention. The semiconductor device 610 includes a plurality of semiconductor chips and a multilayer wiring board 600 on which the plurality of semiconductor chips are mounted. Build-up layers 612 are arranged above and below the core layer 611 to form a multilayer wiring board 600. In the example of FIG. 7, each build-up layer 612 is composed of three layers L1, L2, and L3.
　上側のビルドアップ層６１２の上面には、第１の半導体チップ２１０（図７の例ではＨＢＭ）が、フェイスアップで、背面をコア層６１１側にして実装される。すなわち、第１の半導体チップ２１０のＨＢＭの接続パッドのない側がコア層６１１に向いている。図７では、第１の半導体チップ２１０がＬ１層に埋め込まれている。第１の半導体チップ２１０は、Ｌ１層に埋め込まれていなくてもよい。 A first semiconductor chip 210 (HBM in the example of FIG. 7) is mounted on the upper surface of the upper build-up layer 612 face-up with the back surface facing the core layer 611. That is, the side of the first semiconductor chip 210 without the connection pad of the HBM faces the core layer 611. In FIG. 7, the first semiconductor chip 210 is embedded in the L1 layer. The first semiconductor chip 210 may not be embedded in the L1 layer.
　第１の半導体チップ２１０の直下のＬ１層には、第１の半導体チップ２１０をフェイスアップで実装するための金属のポートである排熱用パッド２２０が配置されている。排熱用パッド２２０において、第１の半導体チップ２１０との接触部が金属である。さらにＬ１層の直下のＬ２層には、金属からなる平面状の排熱板２４０が配置されている。さらにＬ２層の直下のＬ３層には、金属からなる平面状の排熱板２６０が配置されている。このように、第１の半導体チップ２１０の下のビルドアップ層６１２には、ビア構造がなく、金属ブレーン層（導体層）のみが形成されている。 A heat exhaust pad 220, which is a metal port for mounting the first semiconductor chip 210 face-up, is arranged on the L1 layer directly below the first semiconductor chip 210. In the heat exhaust pad 220, the contact portion with the first semiconductor chip 210 is made of metal. Further, a flat heat exhaust plate 240 made of metal is arranged in the L2 layer directly below the L1 layer. Further, a flat heat exhaust plate 260 made of metal is arranged in the L3 layer directly below the L2 layer. As described above, the build-up layer 612 under the first semiconductor chip 210 has no via structure, and only the metal brain layer (conductor layer) is formed.
　さらにＬ３層の直下のコア層６１１には、金属からなる伝熱用のビア構造２７０が配置されている。ビア構造２７０の開口部が円形である。ビア構造２７０の壁面が垂直に開けられた孔の開口部および壁面に銅めっきを析出させた後、銅めっきされなかった空隙部に樹脂または金属ペーストを充填した構造をしている。下側（反対面側）のビルドアップ層６１２にも、上側と同様に、平面状の排熱板２６０、平面状の排熱板２４０、平面状の排熱板２９０が配置されている。 Further, a via structure 270 for heat transfer made of metal is arranged in the core layer 611 directly below the L3 layer. The opening of the via structure 270 is circular. The wall surface of the via structure 270 has a structure in which copper plating is deposited on the openings of holes vertically formed and the wall surface, and then the voids not plated with copper are filled with resin or metal paste. Similarly to the upper side, a flat heat exhaust plate 260, a flat heat exhaust plate 240, and a flat heat exhaust plate 290 are arranged on the build-up layer 612 on the lower side (opposite surface side).
　上側のビルドアップ層６１２の上面には、金属ポスト３２０（接合構造）と、金属の構造体３３０とが配置されている。第２の半導体チップ３１０（図７の例ではＬＳＩ）は、フェイスダウンで実装されている。金属ポスト３２０は、第２の半導体チップ３１０（図７の例ではＬＳＩ）を第１の半導体チップ２１０の高さよりも高い位置で実装するため接合構造を有している。なお、高さとは、コア層６１１及びビルドアップ層６１２の配列方向における高さである。金属の構造体３３０は、第２の半導体チップ３１０の筐体と接触する。金属の構造体３３０は、第２の半導体チップ３１０に接して熱を逃がす。第１の半導体チップ２１０と第２の半導体チップ３１０は、接続用金属ポスト４１０で接続される。 A metal post 320 (joint structure) and a metal structure 330 are arranged on the upper surface of the upper build-up layer 612. The second semiconductor chip 310 (LSI in the example of FIG. 7) is mounted face-down. The metal post 320 has a bonding structure for mounting the second semiconductor chip 310 (LSI in the example of FIG. 7) at a position higher than the height of the first semiconductor chip 210. The height is the height in the arrangement direction of the core layer 611 and the build-up layer 612. The metal structure 330 comes into contact with the housing of the second semiconductor chip 310. The metal structure 330 is in contact with the second semiconductor chip 310 to dissipate heat. The first semiconductor chip 210 and the second semiconductor chip 310 are connected by a connecting metal post 410.
　第２の半導体チップ３１０の下の金属ポスト３２０の直下のＬ１層には、金属からなる排熱用パッド３４０が配置されている。さらにＬ１層の直下のＬ２層には、金属からなる排熱用ビア（導電ビア）３５０と平面状の排熱板３６０が配置されている。さらにＬ２層の直下のＬ３層には、金属からなる排熱用ビア（導電ビア）３７０と平面状の排熱板３８０が配置されている。このように、排熱用ビア３５０および排熱用ビア３７０は、フローティング電位放熱用のビア（導体）である。 A heat exhaust pad 340 made of metal is arranged in the L1 layer directly below the metal post 320 under the second semiconductor chip 310. Further, in the L2 layer directly below the L1 layer, a heat exhaust via (conductive via) 350 made of metal and a flat heat exhaust plate 360 are arranged. Further, in the L3 layer directly below the L2 layer, a heat exhaust via (conductive via) 370 made of metal and a flat heat exhaust plate 380 are arranged. As described above, the heat exhaust via 350 and the heat exhaust via 370 are vias (conductors) for heat dissipation of the floating potential.
　さらにＬ３層の直下のコア層６１１には、第１の半導体チップ２１０の下と同様に、金属からなる伝熱用のビア構造２７０が配置されている。下側（反対面側）のビルドアップ層６１２にも、上側と同様に、平面状の排熱板３８０、排熱用ビア（導電ビア）３７０、平面状の排熱板３６０、排熱用ビア（導電ビア）３５０、平面状の排熱板３９０が配置されている。 Further, in the core layer 611 directly below the L3 layer, a via structure 270 for heat transfer made of metal is arranged as in the case under the first semiconductor chip 210. Similarly to the upper side, the build-up layer 612 on the lower side (opposite surface side) also has a flat heat exhaust plate 380, a heat exhaust via (conductive via) 370, a flat heat exhaust plate 360, and a heat exhaust via. (Conductive via) 350 and a flat heat exhaust plate 390 are arranged.
　このように、第１の半導体チップ２１０の直下には、半導体チップに接して熱を逃がす金属の排熱用パッド２２０（金属の構造体）が配置されている。第２の半導体チップ３１０の直下には、半導体チップに接して熱を逃がす金属の構造体３３０が配置されている。多層配線基板６００は、コア層６１１に伝熱用のビア構造２７０を有しているため、基板の反対面側から排熱が行われる。 As described above, directly below the first semiconductor chip 210, a metal heat exhaust pad 220 (metal structure) that is in contact with the semiconductor chip and releases heat is arranged. Immediately below the second semiconductor chip 310, a metal structure 330 that is in contact with the semiconductor chip and releases heat is arranged. Since the multilayer wiring board 600 has a via structure 270 for heat transfer in the core layer 611, heat is exhausted from the opposite surface side of the board.
　第１の半導体チップ２１０の直下のビルドアップ層６１２にビア構造がないので、基板の歪が少なく、基板表面に、ビア構造のある所とない所によって生じる凹凸が少ないため、実装面の平滑性がよい。また、上下をメタルでつないだ構造に比べて、熱の伝わり方がゆっくりであり、ビルドアップ層の絶縁樹脂を伝熱する速度を遅らせる（調整する）ことができる。 Since the build-up layer 612 immediately below the first semiconductor chip 210 has no via structure, there is little distortion of the substrate, and the surface of the substrate has less unevenness caused by the presence or absence of the via structure, so that the mounting surface is smooth. Is good. In addition, the heat transfer is slower than the structure in which the upper and lower parts are connected by metal, and the speed of heat transfer to the insulating resin of the build-up layer can be delayed (adjusted).
　図８Ａ及び図８Ｂは、本発明の実施形態に係る半導体装置の模式図である。図８Ａは断面図であり、図８Ｂは上視図である。図７に示す半導体装置に加えて、図８Ａでは、第３の半導体チップ５１０（図８ＡではＬＳＩ）が示されている。第３の半導体チップ５１０の下は、第２の半導体チップ３１０と同様に、半導体チップの下に、排熱用ビアが形成されていて、反対側面まで垂直に接続されている。これにより、多層配線基板６００は、金属の構造体から伝熱可能な構成を備えているため、基板の反対面側から排熱が行われる。 8A and 8B are schematic views of a semiconductor device according to an embodiment of the present invention. FIG. 8A is a cross-sectional view, and FIG. 8B is an upper view. In addition to the semiconductor device shown in FIG. 7, FIG. 8A shows a third semiconductor chip 510 (LSI in FIG. 8A). Similar to the second semiconductor chip 310, a heat exhaust via is formed under the semiconductor chip under the third semiconductor chip 510, and is vertically connected to the opposite side surface. As a result, since the multilayer wiring board 600 has a structure capable of transferring heat from the metal structure, heat is exhausted from the opposite surface side of the board.
　図９Ａ及び図９Ｂは、本発明の実施形態に係る多層配線基板の模式図である。図９Ａは断面図であり、図９Ｂは上視図である。図９Ａ及び図９Ｂに示す多層配線基板に、半導体チップを実装することで、図８Ａ及び図８Ｂに示す半導体装置となる。 9A and 9B are schematic views of a multilayer wiring board according to an embodiment of the present invention. 9A is a cross-sectional view and FIG. 9B is an upper view. By mounting the semiconductor chip on the multilayer wiring board shown in FIGS. 9A and 9B, the semiconductor device shown in FIGS. 8A and 8B can be obtained.
　以上、本発明の好ましい実施形態を説明したが、本発明はこれら実施形態およびその変形例に限定されることはない。本発明の趣旨を逸脱しない範囲で、構成の付加、省略、置換、およびその他の変更が可能である。 Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments and variations thereof. It is possible to add, omit, replace, and make other changes to the configuration without departing from the spirit of the present invention.
　１、１０１、６００…多層配線基板、１０、１１０、６１０…半導体装置、１１、１１１、６１１…コア層、１２、１１２、６１２…ビルドアップ層、２１、２１０…第１の半導体チップ、２２、２２０…排熱用パッド（ポート）、２３、２５、３５、３７、３５０、３７０…排熱用ビア（放熱用の導体）、２４、２６、２９、３６、３８、３９、３８０、３９０…排熱板、２７、２７０…ビア構造、３１、３１０…第２の半導体チップ、３２、３２０…金属ポスト（接合構造）、３３、３３０…金属の構造体、３４、３４０…排熱用パッド、１２０…導体ブロック（金属ブロック） 1, 101, 600 ... Multilayer wiring board, 10, 110, 610 ... Semiconductor device, 11, 111, 611 ... Core layer, 12, 112, 612 ... Build-up layer, 21, 210 ... First semiconductor chip, 22, 220 ... Heat exhaust pad (port), 23, 25, 35, 37, 350, 370 ... Heat exhaust via (conductor for heat dissipation), 24, 26, 29, 36, 38, 39, 380, 390 ... Exhaust Hot plate, 27, 270 ... Via structure, 31, 310 ... Second semiconductor chip, 32, 320 ... Metal post (joint structure), 33, 330 ... Metal structure, 34, 340 ... Heat exhaust pad, 120 … Conductor block (metal block)

Claims (6)

  1. 　コア層とビルドアップ層とを有する多層配線基板であって、
    　第１の半導体チップがフェイスアップで実装され、前記第１の半導体チップとの接触部が金属であるポートと、
    　第２の半導体チップが前記第１の半導体チップの高さよりも高い位置で実装される接合構造と、
    　前記第２の半導体チップの筐体と前記ビルドアップ層とを接続する金属の構造体と、
    　前記ビルドアップ層に配置された放熱用の導体と、
    　前記コア層に配置された伝熱用のビア構造と、
    を有する多層配線基板。     A multi-layer wiring board having a core layer and a build-up layer.
    A port in which the first semiconductor chip is mounted face-up and the contact portion with the first semiconductor chip is metal,
    A bonding structure in which the second semiconductor chip is mounted at a position higher than the height of the first semiconductor chip,
    A metal structure connecting the housing of the second semiconductor chip and the build-up layer, and
    The conductor for heat dissipation arranged in the build-up layer and
    The via structure for heat transfer arranged in the core layer and
    Multi-layer wiring board with.
  2. 　前記コア層の伝熱用のビア構造は、金属ブロックである、
    　請求項１に記載の多層配線基板。     The via structure for heat transfer of the core layer is a metal block.
    The multilayer wiring board according to claim 1.
  3. 　請求項１または２に記載の多層配線基板と、
    　前記第１の半導体チップと、
    　前記第２の半導体チップと、
    を備える半導体装置。     The multilayer wiring board according to claim 1 or 2,
    With the first semiconductor chip
    With the second semiconductor chip
    A semiconductor device equipped with.
  4. 　コア層とビルドアップ層とを有する多層配線基板であって、
    　第１の半導体チップがフェイスアップで実装され、前記第１の半導体チップとの接触部が金属であるポートと、
    　第２の半導体チップが前記第１の半導体チップの高さよりも高い位置で実装される接合構造と、
    　前記第２の半導体チップの筐体と前記ビルドアップ層とを接続する金属の構造体と、
    　前記第１の半導体チップの直下の前記ビルドアップ層に配置された金属ブレーン層と、
    　前記第２の半導体チップの直下の前記ビルドアップ層に配置された導電ビアと、
    　前記コア層に配置された伝熱用のビア構造と、
    を有する多層配線基板。     A multi-layer wiring board having a core layer and a build-up layer.
    A port in which the first semiconductor chip is mounted face-up and the contact portion with the first semiconductor chip is metal,
    A bonding structure in which the second semiconductor chip is mounted at a position higher than the height of the first semiconductor chip,
    A metal structure connecting the housing of the second semiconductor chip and the build-up layer, and
    A metal brain layer arranged in the build-up layer directly below the first semiconductor chip, and
    Conductive vias arranged in the build-up layer directly below the second semiconductor chip, and
    The via structure for heat transfer arranged in the core layer and
    Multi-layer wiring board with.
  5. 　前記第１の半導体チップの直下の前記ビルドアップ層には、前記導電ビアが設けられていない、
    　請求項４に記載の多層配線基板。     The conductive via is not provided in the build-up layer directly below the first semiconductor chip.
    The multilayer wiring board according to claim 4.
  6. 　請求項４または５に記載の多層配線基板と、
    　前記第１の半導体チップと、
    　前記第２の半導体チップと、
    を備える半導体装置。     The multilayer wiring board according to claim 4 or 5,
    With the first semiconductor chip
    With the second semiconductor chip
    A semiconductor device equipped with.
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JP2014220307A (en) * 2013-05-06 2014-11-20 株式会社デンソー Multilayer board, electronic device using the same and method of manufacturing multilayer board
JP2016122758A (en) * 2014-12-25 2016-07-07 イビデン株式会社 Multilayer wiring board

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003204013A (en) * 2002-01-10 2003-07-18 Hitachi Ltd High frequency module
JP2013135168A (en) * 2011-12-27 2013-07-08 Ibiden Co Ltd Printed wiring board
JP2014220307A (en) * 2013-05-06 2014-11-20 株式会社デンソー Multilayer board, electronic device using the same and method of manufacturing multilayer board
JP2016122758A (en) * 2014-12-25 2016-07-07 イビデン株式会社 Multilayer wiring board

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