JP2016072421A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2016072421A JP2016072421A JP2014199925A JP2014199925A JP2016072421A JP 2016072421 A JP2016072421 A JP 2016072421A JP 2014199925 A JP2014199925 A JP 2014199925A JP 2014199925 A JP2014199925 A JP 2014199925A JP 2016072421 A JP2016072421 A JP 2016072421A
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- metal pattern
- semiconductor device
- metal
- substrate
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Abstract
【解決手段】半導体装置は、セラミック基板CS1上に形成された複数の金属パターンMPと、複数の金属パターンMPに搭載された複数の半導体チップを有する。また、複数の金属パターンMPは、互いに対向する金属パターンMPHおよび金属パターンMPUと、を有する。また金属パターンMPHと金属パターンMPUとの間に設けられ、かつ、複数の金属パターンMPから露出した領域EX1は、金属パターンMPHの延在方向に沿って、ジグザグに延びる。
【選択図】図9
Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
以下で図面を用いて詳しく説明する本実施の形態では、セラミック基板上に複数の半導体チップが並べて搭載された半導体装置の例として、入力された直流電力を交流電力に変換して出力する電力変換装置(インバータ装置)を取り上げて説明する。
次に、図1に示すインバータ回路INVを構成する半導体装置PKG1の構成例について説明する。図2は、図1に示す半導体装置の外観を示す斜視図である。また、図3は、図2に示す半導体装置の裏面側を示す平面図である。また、図4は、図3のA−A線に沿った断面図である。また、図5は、図3に示すセラミック基板の上面側のレイアウトを示す平面図である。また、図6は、図5に示す半導体装置が構成する回路を模式的に示す説明図である。また、図7は、図5に示す半導体チップの周辺を拡大して示す拡大平面図である。また、図8は図7のA−A線に沿った拡大断面図である。
次に、図5に示す金属パターンの平面形状の詳細について説明する。図9は、図5に示す複数の金属パターンのレイアウトを示す平面図である。また、図14は、図9に対する検討例を示す平面図である。また、図10は図9に対する変形例を示す平面図である。
次に、図1〜図10を用いて説明した半導体装置PKG1の製造工程について、図11に示す工程フローに沿って説明する。図11は、図2に示す半導体装置の組立てフローを示す説明図である。
まず、図11に示す基板準備工程では、図9に示すセラミック基板を準備する。本工程で準備するセラミック基板CS1を準備する。本工程で準備するセラミック基板CS1は、例えばアルミナを主成分とするセラミックであって、上面CStおよび下面CSb(図4参照)に複数の金属パターンMPが接合されている。
次に、図11に示すダイボンド工程では、図12に示すように、セラミック基板CS1の金属パターンMP上に、複数の半導体チップCPを搭載する。図12は、図11に示すダイボンド工程でセラミック基板上に複数の半導体チップを搭載した状態を示す平面図である。
次に、図11に示すワイヤボンド工程では、図13に示すように、半導体チップCPと金属パターンMPとをワイヤ(導電性部材)BWを介して電気的に接続する。図13は、図12に示す複数の半導体チップと複数の金属パターンとをワイヤを介して電気的に接続した状態を示す平面図である。
次に、図11に示す端子搭載工程では、図5に示すように、複数の金属パターンMP上に端子LDを搭載する。端子LDは、複数の金属パターンと、図示しない外部機器とを電気的に接続するためのリード端子であって、細長く伸びる一方の端部を金属パターンMPに接続する。図4に示す例では、複数の端子LDのそれぞれは、半田SDを介して金属パターンMP上に搭載される。
次に、図11に示す蓋材取付工程では、図4に示すように、セラミック基板CS1の上面CStを覆うように蓋材CVを接着固定する。セラミック基板CS1の上面CStの周縁部と蓋材CVとは、接着材BD1を介して接着固定される。
次に、図11に示す封止工程では、図4に示すようにセラミック基板CS1と蓋材CVとに囲まれた空間内に封止材MGを供給し、複数の端子LDのそれぞれの一部分、複数の半導体チップCP、および複数のワイヤBWを封止する。封止材MGは、ゲル状の材料であり、蓋材CVの一部に図示しない供給用の貫通孔を形成しておき、貫通孔からゲル状の封止材MGを充填する。
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。なお、上記実施の形態中でもいくつかの変形例について説明したが、以下では、上記実施の形態で説明した変形例以外の代表的な変形例について説明する。
例えば、上記実施の形態では、スイッチング素子として、ハイサイド用のトランジスタQ1を3個、およびローサイド用のトランジスタQ1を3個用いて、三相交流電力を出力する電力変換回路について説明したが、スイッチング素子の数には種々の変形例がある。
また例えば、上記実施の形態では、セラミック基板CS1上の金属パターンMPのレイアウトとして、ハイサイド用の金属パターンMPHとローサイド用の金属パターンMPLとの間に、金属パターンMPU、MPV、MPWが並べて配置される実施態様について説明した。
また、例えば、上記の通り種々の変形例について説明したが、上記で説明した各変形例同士を組み合わせて適用することができる。
(a)第1面、前記第1面の反対側に位置する第2面を有し、前記第1面に複数の金属パターンが形成されたセラミック基板を準備する工程と、
(b)前記複数の金属パターンのうちの第1金属パターンに複数の第1半導体チップを搭載する工程と、
(c)前記複数の第1半導体チップのうちの少なくとも一部と、前記複数の金属パターンのうちの第2金属パターンとを電気的に接続する工程と、
を有し、
前記複数の金属パターンは、
第1辺を備え、前記複数の半導体チップのうちの複数の第1半導体チップが搭載される第1金属パターンと、
前記第1金属パターンの前記第1辺と対向する第2辺を有する第2金属パターンと、
を有し、
前記セラミック基板の前記第1面のうち、前記第1金属パターンと前記第2金属パターンの間に設けられ、かつ、前記複数の金属パターンから露出する第1領域は、前記第1金属パターンが延在する第1方向に沿って、ジグザグに延びる、半導体装置の製造方法。
BW ワイヤ(導電性部材)
CD、CP、CTH、CTL 半導体チップ
CMD 制御回路
CNV コンバータ回路
CPb 下面
CPt 上面
CS1、CS2、CSh1 セラミック基板
CSb 下面
CSs1、CSs2、CSs3、CSs4 基板辺
CSt 上面
CV 蓋材(キャップ、カバー部材)
CVb 下面
CVs1、CVs2、CVs3、CVs4 辺
CVt 上面
D1 ダイオード
DT1、DT2、DT3、DT4 凹部
DTC 配電回路
E1、E2 電位
EX1、EX2 領域
FLG フランジ部
INV インバータ回路
LD 端子
LT 端子
MG 封止材
MHs1、MHs2、MLs1、MLs2、MUs1、MUs2、MVs1、MVs2、MWs1、MWs2 辺
MP、MPB、MPH、MPL、MPT、MPU、MPV、MPW 金属パターン
MPm 上面
PDA、PDC、PDE、PDG、PDK 電極
PKG1 半導体装置
PKT 収容部(ポケット)
PR1、PR2、PR3、PR4 凸部
Q1 トランジスタ
SCM 太陽電池モジュール
SD 半田
THH、THL 貫通孔
UT、VT、WT 出力端子
VL1 仮想線(中心線)
WEX1 幅
Claims (19)
- 第1面および前記第1面の反対側に位置する第2面を有するセラミック基板と、
前記セラミック基板の前記第1面に形成された複数の金属パターンと、
前記複数の金属パターンのうちの一部に搭載された複数の半導体チップと、
を有し、
前記複数の金属パターンは、
第1辺を備え、前記複数の半導体チップのうちの複数の第1半導体チップが搭載された第1金属パターンと、
前記第1金属パターンの前記第1辺と対向する第2辺を備え、かつ、前記第1金属パターンとは分離された第2金属パターンと、
を有し、
前記第1金属パターンの前記第1辺は、平面視において、前記第2金属パターンの前記第2辺に向かって突出する複数の第1凸部、および前記複数の第1凸部の間に形成された第1凹部を有し、
前記第2金属パターンの前記第2辺は、平面視において、前記第1金属パターンの前記第1辺に向かって突出する第2凸部、および前記第2凸部の両隣に形成された複数の第2凹部を有し、
前記複数の第1凸部は、前記複数の第2凹部に向かって突出するように設けられ、前記第2凸部は、前記第1凹部に向かって突出するように設けられている、半導体装置。 - 請求項1に記載の半導体装置において、
前記セラミック基板の前記第1面は、第1方向に沿って延びる第1基板辺、前記第1基板辺の反対側に位置する第2基板辺、前記第1方向に交差する第2方向に沿って延びる第3基板辺、および前記第3基板辺の反対側に位置する第4基板辺を有し、
前記第1基板辺および前記第2基板辺の長さは、前記第3基板辺および前記第4基板辺の長さよりも長く、
前記第1金属パターンの前記第1辺および前記第2金属パターンの前記第2辺のそれぞれは、前記第1方向に沿って設けられている、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1金属パターンには、第1電位が供給され、
前記第2金属パターンには、前記第1電位とは異なる第2電位が供給される、半導体装置。 - 請求項1に記載の半導体装置において、
平面視において、前記複数の第1凸部は、前記複数の第2凹部で囲まれた領域内に設けられ、前記第2凸部は、前記第1凹部に囲まれた領域内に設けられている、半導体装置。 - 請求項4に記載の半導体装置において、
前記複数の第1半導体チップのうちの少なくとも一部は、複数のワイヤを介して前記第2金属パターンと電気的に接続され、
前記複数のワイヤのそれぞれは、前記第2金属パターンの前記第2凸部に接合された、半導体装置。 - 請求項5に記載の半導体装置において、
前記第2凸部の面積は、前記複数の第1凸部のそれぞれの面積よりも大きい、半導体装置。 - 請求項1に記載の半導体装置において、
前記第2金属パターンは、前記第2辺の反対側に位置する第3辺を備え、
前記複数の金属パターンは、前記第2金属パターンの前記第3辺と対向する第4辺を備え、かつ、前記第1金属パターンおよび前記第2金属パターンとは分離された第3金属パターン、を有し、
前記第2金属パターンの前記第3辺は、平面視において、前記第3金属パターンの前記第4辺に向かって突出する複数の第3凸部、および前記複数の第3凸部の間に形成された第3凹部を有し、
前記第3金属パターンの前記第4辺は、平面視において、前記第2金属パターンの前記第3辺に向かって突出する第4凸部、および前記第4凸部の両隣に形成された複数の第4凹部を有し、
前記複数の第3凸部は、前記複数の第4凹部に向かって突出するように設けられ、前記第4凸部は、前記第3凹部に向かって突出するように設けられている、半導体装置。 - 請求項7に記載の半導体装置において、
前記複数の第1凸部は、前記複数の第2凹部で囲まれた領域内に設けられ、前記第2凸部は、前記第1凹部に囲まれた領域内に設けられている、半導体装置。 - 請求項8に記載の半導体装置において、
前記複数の第1半導体チップのうちの少なくとも一部は、複数のワイヤを介して前記第2金属パターンと電気的に接続され、
前記複数のワイヤのそれぞれは、前記第2金属パターンの前記第2凸部に接合された、半導体装置。 - 請求項9に記載の半導体装置において、
前記第2凸部の面積は、前記複数の第1凸部のそれぞれの面積よりも大きい、半導体装置。 - 請求項7に記載の半導体装置において、
前記セラミック基板の前記第1面は、第1方向に沿って延びる第1基板辺、前記第1基板辺の反対側に位置する第2基板辺、前記第1方向に交差する第2方向に沿って延びる第3基板辺、および前記第3基板辺の反対側に位置する第4基板辺を有し、
前記第1基板辺および前記第2基板辺の長さは、前記第3基板辺および前記第4基板辺の長さよりも長く、
前記複数の金属パターンは、前記セラミック基板の前記第1基板辺と前記第1金属パターンとの間、および前記セラミック基板の前記第3基板辺と前記第3金属パターンとの間、に配置された複数の第4金属パターンを有し、
前記第1金属パターンは、前記第1辺の反対側に位置し、かつ、前記複数の第4金属パターンと対向するように前記第1方向に沿って直線的に延びる第5辺を備え、
前記第3金属パターンは、前記第4辺の反対側に位置し、かつ、前記複数の第4金属パターンと対向するように前記第1方向に沿って直線的に延びる第6辺を備え、
前記セラミック基板の前記第3基板辺の中心と前記第4基板辺の中心とを結ぶ第1仮想線は、前記第1金属パターンの前記第1辺と前記第3金属パターンの前記第4辺の間に存在する、半導体装置。 - 請求項1に記載の半導体装置において、
前記複数の金属パターンは、
第1電位が供給される前記第1金属パターンと、
前記第1電位よりも低い第2電位が供給される第3金属パターンと、
前記第1金属パターンと前記第3金属パターンとの間に設けられ、互いに分離され、かつ、周期的に変動する電位が供給される複数の前記第2金属パターンと、
を有し、
前記複数の半導体チップのうちの複数の第1半導体チップは、前記第1金属パターン上に搭載され、
前記複数の半導体チップのうちの複数の第2半導体チップは、複数の前記第2金属パターン上にそれぞれ搭載され、
前記第1金属パターンの前記第1辺は、平面視において、前記複数の第1凸部および複数の前記第1凹部が交互に配列され、
複数の前記第2金属パターンのそれぞれは、前記第1金属パターンの前記第1辺に向かって突出する前記第2辺の前記第2凸部、および前記第2凸部の両隣に形成された複数の前記第2凹部を有する、半導体装置。 - 請求項12に記載の半導体装置において、
前記複数の第1凸部は、複数の前記第2凹部で囲まれた領域内に設けられ、複数の前記第2凸部は、複数の前記第1凹部に囲まれた領域内に設けられている、半導体装置。 - 請求項13に記載の半導体装置において、
前記複数の第1半導体チップは、複数のワイヤを介して複数の前記第2金属パターンとそれぞれ電気的に接続され、
前記複数のワイヤのそれぞれは、複数の前記第2金属パターンのそれぞれが有する前記第2凸部に接合されている、半導体装置。 - 請求項14に記載の半導体装置において、
前記第2凸部の面積は、前記複数の第1凸部のそれぞれの面積よりも大きい、半導体装置。 - 第1面および前記第1面の反対側に位置する第2面を有するセラミック基板と、
前記セラミック基板の前記第1面に形成された複数の金属パターンと、
前記複数の金属パターンのうちの一部に搭載された複数の半導体チップと、
を有し、
前記複数の金属パターンは、
第1辺を備え、前記複数の半導体チップのうちの複数の第1半導体チップが搭載され、かつ、第1電位が供給される第1金属パターンと、
前記第1金属パターンの前記第1辺と対向する第2辺を備え、かつ、前記第1電位とは異なる第2電位が供給される第2金属パターンと、
を有し、
前記セラミック基板の前記第1面のうち、前記第1金属パターンと前記第2金属パターンの間に設けられ、かつ、前記複数の金属パターンから露出する第1領域は、前記第1金属パターンが延在する第1方向に沿って、ジグザグに延びている、半導体装置。 - 請求項16に記載の半導体装置において、
前記セラミック基板の前記第1面は、前記第1方向に沿って延びる第1基板辺、前記第1基板辺の反対側に位置する第2基板辺、前記第1方向に交差する第2方向に沿って延びる第3基板辺、および前記第3基板辺の反対側に位置する第4基板辺を有し、
前記第1基板辺および前記第2基板辺の長さは、前記第3基板辺および前記第4基板辺の長さよりも長い、半導体装置。 - 請求項16に記載の半導体装置において、
前記第2金属パターンは、前記第2辺の反対側に位置する第3辺を備え、
前記複数の金属パターンは、前記第2金属パターンの前記第3辺と対向する第4辺を備え、かつ、前記第1金属パターンおよび前記第2金属パターンとは分離された第3金属パターン、を有し、
前記セラミック基板の前記第1面のうち、前記第2金属パターンと前記第3金属パターンの間に設けられ、かつ、前記複数の金属パターンから露出する第2領域は、前記第1方向に沿って、ジグザグに延びている、半導体装置。 - 請求項18に記載の半導体装置において、
前記セラミック基板の前記第1面は、第1方向に沿って延びる第1基板辺、前記第1基板辺の反対側に位置する第2基板辺、前記第1方向に交差する第2方向に沿って延びる第3基板辺、および前記第3基板辺の反対側に位置する第4基板辺を有し、
前記第1基板辺および前記第2基板辺の長さは、前記第3基板辺および前記第4基板辺の長さよりも長く、
前記複数の金属パターンは、前記セラミック基板の前記第1基板辺と前記第1金属パターンとの間、および前記セラミック基板の前記第3基板辺と前記第3金属パターンとの間、に配置された複数の第4金属パターンを有し、
前記第1金属パターンは、前記第1辺の反対側に位置し、かつ、前記複数の第4金属パターンと対向するように前記第1方向に沿って直線的に延びる第5辺を備え、
前記第3金属パターンは、前記第4辺の反対側に位置し、かつ、前記複数の第4金属パターンと対向するように前記第1方向に沿って直線的に延びる第6辺を備え、
前記セラミック基板の前記第3基板辺の中心と前記第4基板辺の中心とを結ぶ第1仮想線は、前記第1金属パターンの前記第1辺と前記第3金属パターンの前記第4辺の間に存在する、半導体装置。
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US20110075451A1 (en) * | 2009-09-30 | 2011-03-31 | Infineon Technologies Ag | Power Semiconductor Module and Method for Operating a Power Semiconductor Module |
DE102010006850A1 (de) * | 2010-02-04 | 2011-08-04 | Compact Dynamics GmbH, 82319 | Elektronische Baugruppe zum Schalten elektrischer Leistung |
US20130147540A1 (en) * | 2011-12-07 | 2013-06-13 | Transphorm Inc. | Semiconductor modules and methods of forming the same |
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DE212021000214U1 (de) | 2020-08-05 | 2022-02-16 | Rohm Co., Ltd. | Halbleiterbauteil |
DE112021002615T5 (de) | 2020-08-05 | 2023-03-23 | Rohm Co., Ltd. | Halbleiterbauteil |
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HK1224079A1 (zh) | 2017-08-11 |
US20160093589A1 (en) | 2016-03-31 |
US20170263587A1 (en) | 2017-09-14 |
EP3010040A1 (en) | 2016-04-20 |
US9698125B2 (en) | 2017-07-04 |
CN105470248A (zh) | 2016-04-06 |
KR20160038771A (ko) | 2016-04-07 |
US10236274B2 (en) | 2019-03-19 |
TW201624666A (zh) | 2016-07-01 |
CN205039141U (zh) | 2016-02-17 |
CN105470248B (zh) | 2020-03-27 |
JP6357394B2 (ja) | 2018-07-11 |
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