JP2016062995A - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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JP2016062995A
JP2016062995A JP2014188173A JP2014188173A JP2016062995A JP 2016062995 A JP2016062995 A JP 2016062995A JP 2014188173 A JP2014188173 A JP 2014188173A JP 2014188173 A JP2014188173 A JP 2014188173A JP 2016062995 A JP2016062995 A JP 2016062995A
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Prior art keywords
layer
bump
chip
sealing resin
semiconductor device
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佐藤　隆夫
Takao Sato
隆夫 佐藤
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Toshiba Corp
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Toshiba Corp
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Priority to JP2014188173A priority Critical patent/JP2016062995A/ja
Priority to US14/842,630 priority patent/US20160079222A1/en
Priority to TW104129054A priority patent/TW201613060A/zh
Priority to CN201510591584.9A priority patent/CN105428341A/zh
Publication of JP2016062995A publication Critical patent/JP2016062995A/ja
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Abstract

【課題】半導体装置の信頼性の低下を抑制する。
【解決手段】積層された複数の半導体チップを有するチップ積層体と、チップ積層体を封止する封止樹脂層と、封止樹脂層に埋没するようにチップ積層体上に設けられ、封止樹脂層の上面に沿って封止樹脂層から露出する平坦面を有する第１のバンプ層と、第１のバンプ層の平坦面上に設けられた第２のバンプ層と、を具備する。
【選択図】図１

Description

実施形態の発明は、半導体装置および半導体装置の製造方法に関する。
近年、通信技術や情報処理技術の発達に伴い、半導体装置の小型化および高速化の要求がある。これに対応するため、半導体装置において、複数の半導体チップを積層させた３次元実装により、部品間の配線の長さを短くして動作周波数の増大に対応させ、かつ実装面積効率を高めることを目的とした半導体パッケージの開発が進められている。
例えば、ＮＡＮＤ型フラッシュメモリ等の半導体装置において、小型化および高速化の観点から同一の配線基板にメモリコントローラとメモリチップとを積層させる３次元実装構造が提案されている。３次元実装構造としては、例えばＴＳＶ（Ｔｈｒｏｕｇｈ Ｓｉｌｉｃｏｎ Ｖｉａ）方式による積層構造がある。
３次元実装構造の半導体装置の製造では、リードフレーム等の支持基板上に複数の半導体チップを積層することによりチップ積層体を形成し、チップ積層体上にはんだボール等のバンプ層を形成し、アンダーフィル樹脂により半導体チップ間を封止する。その後、チップ積層体を反転させ、バンプ層を挟んでチップ積層体と配線基板とを接合する。さらに、封止樹脂を充填することによりチップ積層体を封止し、外部接続端子を配線基板に形成した後、ダイシングを行いチップ積層体に応じて配線基板を個片化する。
３次元実装構造の半導体装置では、小型化・薄型化のために半導体チップが非常に薄く、変形しやすい。このため、チップ積層体において半導体チップの反りが発生しやすい。半導体チップの反りが発生するとバンプ層の高さが不均一になり、チップ積層体と配線基板との接続不良が生じやすくなる。このように、３次元実装構造の半導体装置では、半導体チップの反りにより信頼性が低下するといった問題があった。
米国特許第２０１３／０７５８９５号明細書
実施形態の発明が解決しようとする課題は、半導体装置の信頼性の低下を抑制することである。
実施形態の半導体装置は、積層された複数の半導体チップを有するチップ積層体と、チップ積層体を封止する封止樹脂層と、封止樹脂層に埋没するようにチップ積層体上に設けられ、封止樹脂層の上面に沿って封止樹脂層から露出する平坦面を有する第１のバンプ層と、第１のバンプ層の平坦面上に設けられた第２のバンプ層と、を具備する。
半導体装置の構造例を示す図である。 半導体装置の製造方法例を示すフローチャートである。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の構造例を示す図である。 半導体装置の製造方法例を示すフローチャートである。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。 半導体装置の製造方法例を説明するための図である。
以下、実施形態について、図面を参照して説明する。なお、図面は模式的なものであり、例えば厚さと平面寸法との関係、各層の厚さの比率等は現実のものとは異なる場合がある。また、各実施形態において、実質的に同一の構成要素には同一の符号を付し説明を省略する。
（第１の実施形態）
図１は、半導体装置の構造例を示す図である。図１（Ａ）は上面図であり、図１（Ｂ）は図１（Ａ）における線分Ａ１−Ｂ１間の断面図である。図１に示す半導体装置は、ファンイン型の半導体装置であり、支持基板１と、接着剤層２と、積層された複数の半導体チップを有するチップ積層体３と、封止樹脂層４と、バンプ層５と、封止樹脂層６と、バンプ層７と、を具備する。なお、図１では、一例として支持基板１が下側に位置し、バンプ層７が上側に位置するように図示しているが、半導体装置の上下方向は逆であってもよい。また、バンプ層５およびバンプ層７の数は、図１に示す数に限定されない。
支持基板１は、チップ積層体３が搭載される基板である。支持基板１は、例えば金属材料、シリコン等の半導体材料、樹脂材料、セラミック材料等により構成される。支持基板１としては、例えばリードフレームを用いてもよい。リードフレームとしては、例えば４２アロイ等の鉄およびニッケルの合金材料からなるリードフレームを用いることができる。なお、必ずしも支持基板１を設けなくてもよい。
接着剤層２は、支持基板１上に設けられる。接着剤層２は、支持基板１とチップ積層体３とを接着する機能を有する。接着剤層２としては、例えばポリイミド等の樹脂フィルムを用いることができる。
チップ積層体３は、接着剤層２を挟んで支持基板１上に設けられる。チップ積層体３は、支持基板１に積層された半導体チップ３１ａと、半導体チップ３１ｂと、半導体チップ３１ｃと、半導体チップ３１ｄと、を有する。なお、半導体チップの種類は、半導体チップ３１ａないし半導体チップ３１ｄに限定されない。
半導体チップ３１ａは、接着剤層２上に設けられる。例えば、半導体チップ３１ａは、上面に接続パッドを有する。なお、半導体チップ３１ａに半導体チップ３１ａを貫通するＴＳＶ等の貫通電極を設けてもよい。
半導体チップ３１ｂは、半導体チップ３１ａ上に例えば複数積層されて設けられる。半導体チップ３１ｂの積層数は、図１に示す積層数に限定されない。最下層の半導体チップ３１ｂは、バンプ３２および接着層３３を挟んで半導体チップ３１ａに積層され、バンプ３２を介して半導体チップ３１ａに電気的に接続される。また、複数の半導体チップ３１ｂは、バンプ３２および接着層３３を挟んで互いに積層される。
接着層３３は、半導体チップ３１ａないし半導体チップ３１ｃの間隔を維持するためのスペーサとしての機能を有する。接着層３３としては、例えば熱硬化性樹脂等を用いることができる。なお、接着層３３の代わりにＮＣＦ（Ｎｏｎ−Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ：ＮＣＦ）等の絶縁性接着材料を用いて半導体チップ３１ａないし半導体チップ３１ｃの間を封止してもよい。ＮＣＦ等の絶縁性接着材料は、封止と接着の両方の機能を有するため、アンダーフィル樹脂が不要になる。
複数の半導体チップ３１ｂは、半導体チップ３１ｂを貫通するＴＳＶ等の貫通電極３１１を有し、貫通電極３１１およびバンプ３２を介して互いに電気的に接続される。例えば、半導体チップ３１ｂは、上面および下面に接続パッドを有する。半導体チップ３１ａと半導体チップ３１ｂとの接続パッド間、および複数の半導体チップ３１ｂの接続パッド間にバンプ３２が設けられる。貫通電極３１１としては、例えばニッケル、銅、銀、金等の単体または合金を用いることができる。このように、ＴＳＶ方式の積層構造のチップ積層体３を用いることにより、チップ面積を小さくすることができ、接続端子数を多くすることができるため、接続不良等を抑制することができる。
半導体チップ３１ｃは、バンプ３２および接着層３３を挟んで半導体チップ３１ｂに積層され、バンプ３２および貫通電極３１１を介して半導体チップ３１ｂに電気的に接続される。半導体チップ３１ｃは、上面に配線層３４を有する。配線層３４は、半導体チップ３１ａの配線を再配置するための配線層（再配線層ともいう）である。配線層３４は、少なくとも接続配線３４ａを含む複数の接続配線と、絶縁層３４ｂと、を有する。接続配線３４ａは、半導体チップ３１ｃの貫通電極３１１に電気的に接続される。配線層３４上には、電極パッド３５が設けられる。
半導体チップ３１ａないし半導体チップ３１ｃとしては、例えばメモリチップ等を用いることができる。メモリチップとしては、例えばＮＡＮＤ型フラッシュメモリ等の記憶素子を用いることができる。なお、メモリチップにデコーダ等の回路が設けられていてもよい。
半導体チップ３１ｄは、配線層３４上に積層され、接続配線３４ａを介して半導体チップ３１ｃに電気的に接続される。接続配線３４ａおよび電極パッド３５としては、例えば銅、チタン、窒化チタン、クロム、ニッケル、金、またはパラジウム等の単層または積層を用いることができる。
半導体チップ３１ｄとしては、例えばインターフェースチップやコントローラチップを用いることができる。例えば、半導体チップ３１ａないし半導体チップ３１ｃがメモリチップの場合、半導体チップ３１ｄとしてコントローラチップを用い、コントローラチップによりメモリチップに対する書き込みおよび読み出しを制御することができる。なお、半導体チップ３１ｄは、半導体チップ３１ａないし半導体チップ３１ｃよりも小さいことが好ましい。
封止樹脂層４は、少なくとも半導体チップ３１ａないし半導体チップ３１ｄ間を封止する。このとき、半導体チップ３１ａないし半導体チップ３１ｄの側面を覆うように封止樹脂層４を設けてもよい。封止樹脂層４としては、例えばアンダーフィル樹脂等を用いることができる。
バンプ層５は、チップ積層体３の電極パッド３５上に設けられ、例えば配線層３４の接続配線３４ａ以外の接続配線を介して半導体チップ３１ｃに電気的に接続される。
バンプ層５は、例えば錫−銀系、錫−銀−銅系の鉛フリーはんだを用いることができる。バンプ層５として、例えば銅、チタン、窒化チタン、クロム、ニッケル、金、またはパラジウム等の単層または積層を用いてもよい。図１では、バンプ層５がはんだボールの場合について説明する。また、電極パッド３５をバンプ層５の一部とみなしてもよい。
封止樹脂層６は、チップ積層体３を封止する。なお、支持基板１の側面を覆うように封止樹脂層６を設けてもよい。また、支持基板１におけるチップ積層体３形成面の反対面を露出させることにより、放熱性を高めることができる。これに限定されず、上記反対面が封止樹脂層６に覆われていてもよい。
封止樹脂層６は、少なくともＳｉＯ２等の無機充填材を含む。例えば、無機充填材とエポキシ樹脂等の有機樹脂との混合物を用いて封止樹脂層６を構成することができる。無機充填材の含有量は、全体の８０％以上９５％以下であることが好ましい。このような封止樹脂層６は、支持基板１との密着性が高いため好適である。
チップ積層体上にバンプ層を形成し、封止樹脂層によりチップ積層体を封止する場合、チップ積層体において、半導体チップの反りが生じやすい。半導体チップは、半導体素子等を形成する際に生じた残留応力等を有するだけでなく、薄化すると剛性が低くなるため、例えばチップ積層体上にバンプ層を有する場合、支持基板１側が凸になるように凹向きに反りが生じやすい。チップ積層体では、半導体チップを積層すればするほど、下側の半導体チップに積層した半導体チップの応力が加算されていき、反りが顕著になる。反りが生じた場合、中心から周縁に向かってバンプ層が高くなり、複数のバンプ層の高さにばらつきが生じる。
これに対し、図１に示す半導体装置において、バンプ層５は、封止樹脂層６に埋没するようにチップ積層体３上に設けられ、封止樹脂層６の上面に沿って封止樹脂層６から露出された平坦面５１を有する。平坦面５１は、バンプ層７のランドとしての機能を有する。平坦面５１を設けることにより、バンプ層７の形成面の高さを封止樹脂層６の上面の高さに揃えることができる。このとき、複数のバンプ層５の平坦面５１の面積は、周縁に近接するほど大きくてもよい。
バンプ層７は、バンプ層５の平坦面５１上に設けられる。バンプ層７は、外部接続端子としての機能を有する。なお、バンプ層５とバンプ層７とを合わせてバンプとみなしてもよい。バンプ層７としては、例えば錫−銀系、錫−銀−銅系の鉛フリーはんだを用いることができる。バンプ層７として、例えば銅、チタン、窒化チタン、クロム、ニッケル、金、またはパラジウム等の単層または積層を用いてもよい。図１では、バンプ層７がはんだボールの場合について説明するがこれに限定されない。
以上のように、本実施形態の半導体装置は、封止樹脂層に埋没し、封止樹脂層の上面に沿って平坦面を有する第１のバンプ層を有し、第１のバンプ層の平坦面上に第２のバンプ層を有する構造を具備する。これにより、チップ積層体において半導体チップの反りが生じた場合であっても、バンプの高さのばらつきを低減することができる。よって、例えば半導体装置を他の基板等に搭載する場合の接合不良等が抑制され、信頼性の低下を抑制することができる。
また、本実施形態の半導体装置は、チップ積層体上のバンプ層を外部接続端子として用いることができるファンイン型構造を有する。よって、必ずしも半導体装置を別途配線基板に搭載しなくてもよい。従って、半導体装置のサイズを小さくすることができる。
次に、図１に示す半導体装置の製造方法例について図２を参照して説明する。図２は、半導体装置の製造方法例を示すフローチャートである。半導体装置の製造方法例は、複数の半導体チップを積層することによりチップ積層体を形成する積層工程（Ｓ１−１）と、複数の半導体チップの間を封止する第１の封止樹脂層を形成する第１の封止工程（Ｓ１−２）と、チップ積層体上に第１のバンプ層を形成する第１のバンプ層形成工程（Ｓ１−３）と、第１のバンプ層およびチップ積層体を覆う第２の封止樹脂層を形成する第２の封止工程（Ｓ１−４）と、第１のバンプ層の一部および封止樹脂層の一部を、第１のバンプ層が封止樹脂層の上面から露出するまで、半導体チップの積層方向に沿って研削する研削工程（Ｓ１−５）と、第１のバンプ層の研削面上に第２のバンプ層を形成する第２のバンプ層形成工程（Ｓ１−６）と、チップ積層体に応じて支持基板を分離する分離工程（Ｓ１−７）と、を少なくとも具備する。各工程は、例えばステージ、基板、またはテープ等に固定して行ってもよい。なお、各工程の順序は、図２に示す順序に限定されない。また、同一工程により複数の半導体装置を形成してもよい。
さらに、上記工程について、図３ないし図９を参照して説明する。図３ないし図９は、半導体装置の製造方法例を説明するための図である。ここでは、一例として支持基板１にリードフレームを用いる場合について説明する。
積層工程（Ｓ１−１）では、図３に示すように、半導体チップ３１ａないし半導体チップ３１ｄを積層することによりチップ積層体３を形成する。例えば、マウンタ等を用いて半導体チップ３１ａないし半導体チップ３１ｄを積層することができる。
積層工程（Ｓ１−１）では、まず半導体チップ３１ａに接着剤層２を予め形成しておき、接着剤層２を挟んで支持基板１上に半導体チップ３１ａを積層し、加熱処理を行い接着剤層２を硬化させることにより半導体チップ３１ａを接着する。このとき、同一工程により複数の半導体装置を製造する場合、支持基板１として集合基板を用いてもよい。
次に、第１の面にバンプ３２および接着層３３を有し、貫通電極３１１を有する複数の半導体チップ３１ｂをバンプ３２および接着層３３を挟んで半導体チップ３１ａ上に複数積層する。このとき、例えば熱処理を行うことによりバンプ３２を介して半導体チップ３１ａの接続パッドと半導体チップ３１ｂの接続パッドとを接合する。バンプ３２および接着層３３は、例えば積層する２つの半導体チップの少なくとも一方にバンプ３２を構成するバンプ層および接着層３３を構成する接着剤の塗布層を設けておくことにより形成される。
次に、第１の面に配線層３４および電極パッド３５を有し、第２の面にバンプ３２および接着層３３を有する半導体チップ３１ｃをバンプ３２および接着層３３を挟んで半導体チップ３１ｂ上に積層する。このとき、例えば熱処理を行うことにより貫通電極３１１およびバンプ３２を介して半導体チップ３１ａないし半導体チップ３１ｃを接合する。
次に、配線層３４の上に半導体チップ３１ｄを積層する。例えば、熱圧着や還元雰囲気下でのリフロー等により半導体チップ３１ｄを例えばバンプを介して接続配線３４ａに電気的に接続する。上記工程によりチップ積層体３を形成することができる。
第１の封止工程（Ｓ１−２）では、図４に示すように、半導体チップ３１ａないし半導体チップ３１ｄの間および半導体チップ３１ａないし半導体チップ３１ｄの側面に封止樹脂層４を形成する。例えば、半導体チップ３１ａないし半導体チップ３１ｄの間にディスペンサ等を用いてアンダーフィル樹脂を充填することにより、封止樹脂層４を形成することができる。なお、半導体チップ３１ａないし半導体チップ３１ｃ間の封止工程と、半導体チップ３１ｃと半導体チップ３１ｄとの間の封止工程は別工程であってもよい。また、チップ積層体３を囲むように支持基板１に溝を形成してもよい。これにより、例えば同一工程で複数の半導体装置を製造する場合に隣り合うチップ積層体３の形成領域にアンダーフィル樹脂が流出することを抑制することができる。
第１のバンプ層形成工程（Ｓ１−３）では、図５に示すように、チップ積層体３上にバンプ層５を形成する。例えば、ボールマウンタ等を用いて電極パッド３５上にはんだボールを設けることによりバンプ層５を形成することができる。
第２の封止工程（Ｓ１−４）では、図６に示すように、チップ積層体３およびバンプ層５を覆う封止樹脂層６を形成する。例えば、トランスファモールド法、コンプレッションモールド法、インジェクションモールド法等のモールド法を用いてチップ積層体３およびバンプ層５を覆うように封止樹脂層６に適用可能な材料の封止樹脂を充填し、硬化させることにより封止樹脂層６を形成することができる。同一工程で複数の半導体装置を製造する場合、チップ積層体３毎に個別のキャビティ−となるように封止樹脂層６を形成することが好ましい。
研削工程（Ｓ１−５）では、図７に示すように、バンプ層５の一部および封止樹脂層６の一部を、バンプ層５が封止樹脂層６の上面から露出するまで、半導体チップの積層方向に沿って研削する。これにより、封止樹脂層６の上面に沿ってバンプ層５に平坦面５１を形成する。例えば、砥石等を用いてバンプ層５の一部および封止樹脂層６の一部を研削することにより、平坦面５１を形成することができる。これに限定されず、ブラスト処理やＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ：ＣＭＰ）処理を行うことにより、バンプ層５の一部および封止樹脂層６の一部を研削してもよい。
第２のバンプ層形成工程（Ｓ１−６）では、図８に示すように、バンプ層５の研削面である平坦面５１上にバンプ層７を形成する。例えば、バンプ層５の平坦面５１上にフラックスを塗布後、ボールマウンタ等を用いてバンプ層５の平坦面５１上にはんだボールを搭載し、リフロー炉に入れてはんだボールを溶融させ、電極パッド３５と接合させる。その後、溶剤や純水洗浄によりフラックスを除去することによりバンプ層７を形成することができる。
分離工程（Ｓ１−７）では、図９に示すように、チップ積層体３に応じてチップ搭載部を含む支持基板１の一部を分離する。図９（Ａ）は、チップ積層体３が設けられたリードフレームである支持基板１の分離後の平面図であり、図９（Ｂ）は、図３ないし図８に示す断面方向とは異なり、吊りピン部に沿った方向である図９（Ａ）の線分Ｘ−Ｙにおける断面図である。
図９に示す支持基板１は、チップ搭載部１１と、チップ搭載部１１を支持する吊りピン部１２と、を有する。支持基板１に設けられたチップ搭載部１１上にチップ積層体３が形成される。分離工程（Ｓ１−７）では、例えばダイシングブレードを用いて吊りピン部１２を切断することによりチップ積層体３に応じてチップ搭載部１１を含む支持基板１の一部を分離することができる。以上により半導体装置が製造される。なお、複数の半導体装置を形成する場合、チップ積層体３毎にチップ搭載部１１を含む支持基板１の一部を分離する。集合基板を用いて半導体装置を製造する場合、集合基板の一部を分離することにより、分離された集合基板の一部が支持基板１となる。
以上のように、本実施形態における半導体装置の製造方法では、チップ積層体上に第１のバンプ層を形成した後に、第１のバンプ層およびチップ積層体を覆う封止樹脂層を形成する。その後、半導体チップの積層方向に沿って第１のバンプ層の一部および封止樹脂層の一部を研削する。これにより、封止樹脂層の上面に沿って第１のバンプ層に平坦面を形成することができる。さらに、第１のバンプ層の平坦面上に第２のバンプ層を形成することにより、チップ積層体において半導体チップの反りが生じた場合であっても、バンプの高さのばらつきを抑制することができる。
（第２の実施形態）
本実施形態では、第１の実施形態における半導体装置と第１のバンプ層の構造が異なる半導体装置について説明する。なお、第１の実施形態の半導体装置と同じ部分については第１の実施形態の説明を適宜援用することができる。
図１０は、半導体装置の構造例を示す図である。図１０（Ａ）は上面図であり、図１０（Ｂ）は図１０（Ａ）における線分Ａ２−Ｂ２間の断面図である。図１０に示す半導体装置は、図１に示す半導体装置と同様にファンイン型の半導体装置であり、支持基板１と、接着剤層２と、積層された複数の半導体チップを有するチップ積層体３と、半導体チップ間を封止する封止樹脂層４と、チップ積層体３上に設けられたバンプ層５と、チップ積層体３を封止する封止樹脂層６と、バンプ層５上に設けられたバンプ層７と、を具備する。なお、図１０では、一例として支持基板１が下側に位置し、バンプ層７が上側に位置するように図示しているが、半導体装置の上下方向は逆であってもよい。また、バンプ層５およびバンプ層７の数は、図１０に示す数に限定されない。支持基板１、接着剤層２、チップ積層体３、封止樹脂層４、封止樹脂層６、バンプ層７については、第１の実施形態の説明を適宜援用し、ここではバンプ層５について説明する。
バンプ層５は、封止樹脂層６に埋没するように設けられ、封止樹脂層６の上面に沿って封止樹脂層６から露出された平坦面５１を有する。バンプ層５は、チップ積層体３の電極パッド３５上に設けられ、例えば配線層３４の接続配線３４ａ以外の配線を介して半導体チップ３１ｃに電気的に接続される。
バンプ層５は、例えば錫−銀系、錫−銀−銅系の鉛フリーはんだを用いることができる。バンプ層５として、例えば銅、チタン、窒化チタン、クロム、ニッケル、金、またはパラジウム等の単層または積層を用いてもよい。図１０では、バンプ層５が埋込電極の場合について説明する。なお、電極パッド３５をバンプ層５の一部とみなしてもよい。
本実施形態の半導体装置は、第１の実施形態の半導体装置と比較して第１のバンプ層を埋込電極で構成する点が少なくとも異なる。埋込電極で第１のバンプ層を構成することにより、例えば複数の第１のバンプ層の径を同じにすることができるため、第２のバンプ層との接合不良を抑制することができる。よって、信頼性の低下を抑制することができる。
また、本実施形態の半導体装置は、第１の実施形態と同様にチップ積層体上の第２のバンプ層を外部接続端子として用いることができるファンイン型構造を有する。よって、必ずしも半導体装置を別途配線基板に搭載しなくてもよい。従って、半導体装置のサイズを小さくすることができる。
次に、図１０に示す半導体装置の製造方法例について図１１を参照して説明する。図２は、半導体装置の製造方法例を示すフローチャートである。半導体装置の製造方法例は、複数の半導体チップを積層することによりチップ積層体を形成する積層工程（Ｓ２−１）と、複数の半導体チップの間を封止する第１の封止樹脂層を形成する第１の封止工程（Ｓ２−２）と、チップ積層体を覆う第２の封止樹脂層を形成する第２の封止工程（Ｓ２−３）と、チップ積層体の一部が露出するように第２の封止樹脂層に開口部を形成する開口部形成工程（Ｓ２−４）と、開口部を埋めるように導電層を設けることにより第１のバンプ層を形成する第１のバンプ層形成工程（Ｓ２−５）と、第１のバンプ層の一部および封止樹脂層の一部を、第１のバンプ層が封止樹脂層の上面から露出するまで、半導体チップの積層方向に沿って研削する研削工程（Ｓ２−６）と、第１のバンプ層の研削面上に第２のバンプ層を形成する第２のバンプ層形成工程（Ｓ２−７）と、チップ積層体に応じて支持基板を分離する分離工程（Ｓ２−８）と、を少なくとも具備する。なお、各工程の順序は、図１１に示す順序に限定されない。また、同一工程により複数の半導体装置を形成してもよい。
さらに、上記工程について、図１２ないし図１７を参照して説明する。図１２ないし図１７は、半導体装置の製造方法例を説明するための図である。ここでは、一例として支持基板１にリードフレームを用いる場合について説明する。
図１２に示すように、積層工程（Ｓ２−１）では、積層工程（Ｓ１−１）と同様に、チップ積層体３を形成し、第１の封止工程（Ｓ２−２）では、第１の封止工程（Ｓ１−２）と同様に、封止樹脂層４を形成する。その他の説明については、積層工程（Ｓ１−１）および第１の封止工程（Ｓ１−２）の説明を適宜援用することができるため、説明を省略する。
第２の封止工程（Ｓ２−３）では、図１３に示すように、チップ積層体３を覆う封止樹脂層６を形成する。その他の説明については、第２の封止工程（Ｓ１−４）の説明を適宜援用することができるため、説明を省略する。
開口部形成工程（Ｓ２−４）では、図１４に示すように、チップ積層体３の上面の一部（ここでは電極パッド３５の少なくとも一部）が露出するように封止樹脂層６に開口部６ａを形成する。例えば、封止樹脂層６にレーザー光を照射して開口部６ａを形成することができる。これに限定されず、例えばフォトリソグラフィー技術を用いて開口部６ａを形成してもよい。
第１のバンプ層形成工程（Ｓ２−５）では、図１５に示すように、チップ積層体３上にバンプ層５を形成する。例えば、バンプ層５に適用可能な金属の導電ペーストやはんだ材料等を用いて開口部６ａを埋めるように導電層を設けることによりバンプ層５を形成することができる。なお、封止樹脂層６の上を覆うように導電層を形成してもよい。また、開口部６ａを埋めるようにバンプ層５の形成が可能であれば他の方法を用いてバンプ層５を形成してもよい。
研削工程（Ｓ２−６）では、図１６に示すように、バンプ層５の一部および封止樹脂層６の一部を、バンプ層５が封止樹脂層６の上面から露出するまで、半導体チップの積層方向に沿って研削する。これにより、封止樹脂層６の上面に沿ってバンプ層５に平坦面５１を形成する。その他の説明については、研削工程（Ｓ１−５）の説明を適宜援用することができるため、説明を省略する。
第２のバンプ層形成工程（Ｓ２−７）では、図１７に示すように、バンプ層５の研削面である平坦面５１上にバンプ層７を形成する。その他の説明については、第２のバンプ層形成工程（Ｓ１−６）の説明を適宜援用することができるため、説明を省略する。
分離工程（Ｓ２−８）では、分離工程（Ｓ１−７）と同様にチップ積層体３に応じてチップ搭載部を含む支持基板１の一部を分離する。その他の説明については、分離工程（Ｓ１−７）の説明を適宜援用することができるため、説明を省略する。以上により半導体装置が製造される。
以上のように、本実施形態における半導体装置の製造方法では、チップ積層体を覆う封止樹脂層を形成した後に、チップ積層体の一部が露出するように封止樹脂層に開口部を形成する。その後、開口部を埋めるように導電層を設けることにより第１のバンプ層を形成し、その後、半導体チップの積層方向に沿って第１のバンプ層の一部および封止樹脂層の一部を研削する。これにより、径のばらつきが少ない第１のバンプ層を形成することができる。また、封止樹脂層の上面に沿って第１のバンプ層に平坦面を形成することができる。さらに、第１のバンプ層の平坦面に第２のバンプ層を形成することにより、チップ積層体において半導体チップの反りが生じた場合であっても、バンプの高さのばらつきを抑制することができる。
なお、各実施形態は例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施し得るものであり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると共に、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１…支持基板、１１…チップ搭載部、１２…吊りピン部、２…接着剤層、３…チップ積層体、３１ａ…半導体チップ、３１ｂ…半導体チップ、３１ｃ…半導体チップ、３１ｄ…半導体チップ、３２…バンプ、３３…接着層、３４…配線層、３４ａ…接続配線、３４ｂ…絶縁層、３５…電極パッド、３１１…貫通電極、４…封止樹脂層、５…バンプ層、５１…平坦面、６…封止樹脂層、６ａ…開口部、７…バンプ層。

Claims (5)

  1. 積層された複数の半導体チップを有するチップ積層体と、
    前記チップ積層体を封止する封止樹脂層と、
    前記封止樹脂層に埋没するように前記チップ積層体上に設けられ、前記封止樹脂層の上面に沿って前記封止樹脂層から露出する平坦面を有する第１のバンプ層と、
    前記第１のバンプ層の前記平坦面上に設けられた第２のバンプ層と、を具備する半導体装置。
  2. 請求項１に記載の半導体装置において、
    前記チップ積層体が搭載された支持基板をさらに具備する、半導体装置。
  3. 複数の半導体チップを積層することによりチップ積層体を形成し、
    前記チップ積層体上に第１のバンプ層を形成し、
    前記第１のバンプ層および前記チップ積層体を覆う封止樹脂層を形成し、
    前記第１のバンプ層の一部および前記封止樹脂層の一部を、前記第１のバンプ層が前記封止樹脂層の上面から露出するまで、前記半導体チップの積層方向に沿って研削し、
    前記第１のバンプ層の研削面上に第２のバンプ層を形成する、半導体装置の製造方法。
  4. 複数の半導体チップを積層することによりチップ積層体を形成し、
    前記チップ積層体を覆う封止樹脂層を形成し、
    前記チップ積層体の上面の一部が露出するように前記封止樹脂層に開口部を形成し、
    前記開口部を埋めるように導電層を設けることにより第１のバンプ層を形成し、
    前記第１のバンプ層の一部および前記封止樹脂層の一部を、前記第１のバンプ層が前記封止樹脂層の上面から露出するまで、前記半導体チップの積層方向に沿って研削し、
    前記第１のバンプ層の研削面上に第２のバンプ層を形成する、半導体装置の製造方法。
  5. 請求項３または請求項４に記載の半導体装置の製造方法において、
    支持基板に設けられたチップ搭載部上に前記複数の半導体チップを積層することにより前記チップ積層体を形成し、
    前記第２のバンプ層を形成した後に前記チップ積層体に応じて前記チップ搭載部を含む前記支持基板の一部を分離する、半導体装置の製造方法。
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