JP2015046484A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP2015046484A JP2015046484A JP2013176723A JP2013176723A JP2015046484A JP 2015046484 A JP2015046484 A JP 2015046484A JP 2013176723 A JP2013176723 A JP 2013176723A JP 2013176723 A JP2013176723 A JP 2013176723A JP 2015046484 A JP2015046484 A JP 2015046484A
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- bonding wire
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Abstract
Description
図1は、実施の形態に係る半導体装置SDの構成を示す断面図である。本実施形態に係る半導体装置SDは、チップ搭載部DPの第1面に第1半導体チップSC1及び第2半導体チップSC2を搭載した構成を有している。チップ搭載部DPは、例えばリードフレームのダイパッドである。第1半導体チップSC1は、ボンディングワイヤWIR1を介して第1端子TER1に接続しており、第2半導体チップSC2はボンディングワイヤWIR2を介して第2端子TER2に接続している。第1端子TER1及び第2端子TER2は、例えばリードフレームのリード端子である。そして第1半導体チップSC1と第2半導体チップSC2は、ボンディングワイヤWIR3を介して互いに接続されている。ボンディングワイヤWIR1,WIR2,WIR3は、例えば金ワイヤであるが、他の金属(例えば銅)によって形成されていても良い。
図13は、変形例1に係る半導体装置SDの平面図である。図14は、図13の領域αを拡大した図である。図13は実施形態における図2に対応しており、図14は実施形態における図3に対応している。本変形例に係る半導体装置SDは、第1電極パッドPAD11及び第2電極パッドPAD21の配置を除いて、実施形態に係る半導体装置SDと同様の構成である。
図15は、変形例2に係る半導体装置SDの平面図である。図16は、図15の領域αを拡大した図である。図15は実施形態における図2に対応しており、図16は実施形態における図3に対応している。本変形例に係る半導体装置SDは、以下の点を除いて、実施形態に係る半導体装置SDと同様の構成である。
図17は、変形例3に係る半導体装置SDの構成を示す断面図である。本図に示す半導体装置SDは、第1半導体チップSC1および第2半導体チップSC2の封止構造がQFP(Quad Flat Package)である点を除いて、実施形態又は変形例1,2のいずれかに係る半導体装置SDと同様の構成である。
図18は、変形例4に係る半導体装置SDの構成を示す断面図である。本図に示す半導体装置SDは、第1半導体チップSC1および第2半導体チップSC2の封止構造がBGA(Ball Grid Array)である点を除いて、実施形態又は変形例1,2のいずれかに係る半導体装置SDと同様の構成である。
DP チップ搭載部
GR1 グループ
GR2 グループ
FC 流路
MDR 封止樹脂
PAD1 電極パッド
PAD11 第1電極パッド
PAD111 第1電極パッド
PAD112 第1電極パッド
PAD113 第1電極パッド
PAD114 第1電極パッド
PAD117 第1電極パッド
PAD2 電極パッド
PAD21 第2電極パッド
PAD211 第2電極パッド
PAD212 第2電極パッド
PAD213 第2電極パッド
PAD214 第2電極パッド
PAD217 第2電極パッド
PAD221 電極パッド
PAD222 電極パッド
PAD223 電極パッド
PT 樹脂保持部
PTR パワートランジスタ
PTR1 パワートランジスタ
PTR2 パワートランジスタ
SC1 第1半導体チップ
SC2 第2半導体チップ
SD 半導体装置
SID1 第1辺
SID2 第2辺
SID3 第3辺
SID4 第4辺
SID5 第5辺
SID6 第6辺
SID7 第7辺
SID8 第8辺
SL リード
TER1 第1端子
TER2 第2端子
UCPAD1 空電極パッド
UCPAD2 空電極パッド
WIR1 ボンディングワイヤ
WIR2 ボンディングワイヤ
WIR3 ボンディングワイヤ
WIR31 第1ボンディングワイヤ
WIR32 第2ボンディングワイヤ
WIR33 第3ボンディングワイヤ
WIR34 第4ボンディングワイヤ
WIR35 第5ボンディングワイヤ
WIR36 第6ボンディングワイヤ
WIR37 第7ボンディングワイヤ
Claims (9)
- 矩形であり、第1辺、前記第1辺に対向する第2辺、第3辺、及び第4辺を有する第1半導体チップと、
矩形であり、第5辺、前記第5辺に対向する第6辺、第7辺、及び第8辺を有する第2半導体チップと、
前記第1半導体チップ及び前記第2半導体チップを同一面上に搭載したチップ搭載部と、
前記第1半導体チップと前記第2半導体チップを接続する複数のボンディングワイヤと、
を備え、
前記第1半導体チップの前記第1辺は、前記第2半導体チップの前記第5辺に対向しており、
前記第1半導体チップは、前記第1辺に沿って配置された複数の第1電極パッドを有しており、
前記第2半導体チップは、前記第5辺に沿って配置された複数の第2電極パッドを有しており、
第1の前記ボンディングワイヤ、第2の前記ボンディングワイヤ、第3の前記ボンディングワイヤ、及び第4の前記ボンディングワイヤは、前記第1辺に沿ってこの順に並んでおり、
前記チップ搭載部に垂直な方向から見た場合において、
前記第1のボンディングワイヤと前記第2のボンディングワイヤの間隔の最大値は、前記第2のボンディングワイヤと前記第3のボンディングワイヤの間隔の最大値よりも広く、
前記第2のボンディングワイヤと前記第3のボンディングワイヤの間隔の最大値は、前記第3のボンディングワイヤと前記第4のボンディングワイヤの間隔の最大値よりも広い半導体装置。 - 請求項1に記載の半導体装置において、
前記チップ搭載部に垂直な方向から見た場合において、
前記第1のボンディングワイヤは、前記第4のボンディングワイヤよりも前記第3辺の近くに位置しており、かつ、前記第4辺に向けて凸になる方向に湾曲している半導体装置。 - 請求項1に記載の半導体装置において、
前記第5辺は前記1辺よりも長く、
前記第2半導体チップは長方形であり、かつ前記第5辺は前記長方形の長辺である半導体装置。 - 請求項3に記載の半導体装置において、
前記第1のボンディングワイヤ、前記第2のボンディングワイヤ、前記第3のボンディングワイヤ、及び前記第4のボンディングワイヤは、互いに異なる前記第1電極パッドを互いに異なる前記第2電極パッドに接続しており、
前記第1のボンディングワイヤに接続する前記第2電極パッドと前記第2のボンディングワイヤに接続する前記第2電極パッドの間隔は、前記第2のボンディングワイヤに接続する前記第2電極パッドと前記第3のボンディングワイヤに接続する前記第2電極パッドの間隔よりも広く、
前記第2のボンディングワイヤに接続する前記第2電極パッドと前記第3のボンディングワイヤに接続する前記第2電極パッドの間隔は、前記第3のボンディングワイヤに接続する前記第2電極パッドと前記第4のボンディングワイヤに接続する前記第2電極パッドの間隔よりも広い半導体装置。 - 請求項1に記載の半導体装置において、
前記第1半導体チップは、前記第1辺に沿って配置され、前記第1のボンディングワイヤと前記第4のボンディングワイヤの間とは異なる場所に位置し、かつ前記ボンディングワイヤが接続されていない空電極パッドを有している半導体装置。 - 矩形であり、第1辺、前記第1辺に対向する第2辺、第3辺、及び第4辺を有する第1半導体チップと、
矩形であり、第5辺、前記第5辺に対向する第6辺、第7辺、及び第8辺を有する第2半導体チップと、
前記第1半導体チップ及び前記第2半導体チップを同一面上に搭載したチップ搭載部と、
前記第1半導体チップと前記第2半導体チップを接続する複数のボンディングワイヤと、
を備え、
前記第1半導体チップの第1辺は、前記第2半導体チップの第5辺に対向しており、
前記第1半導体チップは、前記第1辺に沿って配置された複数の第1電極パッドを有しており、
前記第2半導体チップは、前記第5辺に沿って配置された複数の第2電極パッドを有しており、
第1の前記ボンディングワイヤ、第2の前記ボンディングワイヤ、第3の前記ボンディングワイヤ、及び第4の前記ボンディングワイヤは、前記第1辺に沿ってこの順に並んでおり、かつ互いに異なる前記第1電極パッドを互いに異なる前記第2電極パッドに接続しており、
前記チップ搭載部に垂直な方向から見た場合において、
前記第1のボンディングワイヤに接続する前記第2電極パッドと前記第2のボンディングワイヤに接続する前記第2電極パッドの間隔は、前記第2のボンディングワイヤに接続する前記第2電極パッドと前記第3のボンディングワイヤに接続する前記第2電極パッドの間隔よりも広く、
前記第2のボンディングワイヤに接続する前記第2電極パッドと前記第3のボンディングワイヤに接続する前記第2電極パッドの間隔は、前記第3のボンディングワイヤに接続する前記第2電極パッドと前記第4のボンディングワイヤに接続する前記第2電極パッドの間隔よりも広い半導体装置。 - 請求項6に記載の半導体装置において、
前記チップ搭載部に垂直な方向から見た場合において、
前記第1のボンディングワイヤは、前記第4のボンディングワイヤよりも前記第3辺の近くに位置しており、かつ、前記第4辺に向けて凸になる方向に湾曲している半導体装置。 - 請求項6に記載の半導体装置において、
前記第5辺は前記1辺よりも長く、
前記第2半導体チップは長方形であり、かつ前記第5辺は前記長方形の長辺である半導体装置。 - 矩形であり、第1辺、前記第1辺に対向する第2辺、第3辺、及び第4辺を有する第1半導体チップと、矩形であり、第5辺、前記第5辺に対向する第6辺、第7辺、及び第8辺を有する第2半導体チップと、をチップ搭載部の同一面の上に搭載する工程と、
前記第1半導体チップと前記第2半導体チップを複数のボンディングワイヤで接続する工程と、
前記第1半導体チップ、前記第2半導体チップ、及び前記複数のボンディングワイヤを、前記第3辺側から封止樹脂を注入することによって前記封止樹脂で封止する工程と、
を備え、
前記第1半導体チップの第1辺は、前記第2半導体チップの第5辺に対向しており、
前記第1半導体チップは、前記第1辺に沿って配置された複数の第1電極パッドを有しており、
前記第2半導体チップは、前記第5辺に沿って配置された複数の第2電極パッドを有しており、
第1の前記ボンディングワイヤ、第2の前記ボンディングワイヤ、第3の前記ボンディングワイヤ、及び第4のボンディングワイヤは、前記第1辺に沿って、前記第3辺側からこの順に並んでおり、かつ互いに異なる前記第1電極パッドを互いに異なる前記第2電極パッドに接続しており、
前記チップ搭載部に垂直な方向から見た場合において、
前記第1のボンディングワイヤに接続する前記第2電極パッドと前記第2のボンディングワイヤに接続する前記第2電極パッドの間隔は、前記第2のボンディングワイヤに接続する前記第2電極パッドと前記第3のボンディングワイヤに接続する前記第2電極パッドの間隔よりも広く、
前記第2のボンディングワイヤに接続する前記第2電極パッドと前記第3のボンディングワイヤに接続する前記第2電極パッドの間隔は、前記第3のボンディングワイヤに接続する前記第2電極パッドと前記第4のボンディングワイヤに接続する前記第2電極パッドの間隔よりも広い半導体装置の製造方法。
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