CN104425428A - 半导体器件以及制造半导体器件的方法 - Google Patents

半导体器件以及制造半导体器件的方法 Download PDF

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Publication number
CN104425428A
CN104425428A CN201410432259.3A CN201410432259A CN104425428A CN 104425428 A CN104425428 A CN 104425428A CN 201410432259 A CN201410432259 A CN 201410432259A CN 104425428 A CN104425428 A CN 104425428A
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closing line
limit
electrode pad
semiconductor chip
coupled
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CN201410432259.3A
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浅村规弘
石野能广
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN104425428A publication Critical patent/CN104425428A/zh
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Abstract

本发明涉及半导体器件以及制造半导体器件的方法。公开了一种半导体器件，其中当两个相邻的半导体芯片借助接合线耦接时，可以抑制相邻接合线之间的短路。第一接合线、第二接合线、第三接合线以及第四接合线沿第一边依次排列。当从垂直于芯片安装部的方向观察时，第一接合线和第二接合线之间的间隔的最大值大于第二接合线和第三接合线之间的间隔的最大值。而且，第二接合线和第三接合线之间的间隔的最大值大于第三接合线和第四接合线之间的间隔的最大值。

Description

半导体器件以及制造半导体器件的方法
相关申请交叉引用
将2013年8月28日提交的日本专利申请No.2013-176723的公开内容，包括说明书，附图和摘要，整体并入本文作为参考。
技术领域
本发明涉及一种半导体器件及其制造方法，并且特别涉及一种可以应用至其中例如两个半导体芯片经由接合线彼此耦接的半导体器件以及可以应用至制造该半导体器件的方法的技术。
背景技术
在安装半导体芯片的方法中，半导体芯片安装在引线框架或插接板(interposer)上，使得引线框架和半导体芯片经由接合线彼此耦接，并且半导体芯片和接合线进一步由密封树脂密封。在这种半导体器件的制造中，担心接合线由于密封树脂的流动而变形，由此导致相邻接合线之间的短路。
为了应付这种担心，日本未审专利公布No.2004-158875公开了，在其中半导体芯片安装在引线框架上的半导体器件中，引线框架的内部引线之间的间隔随着接近管芯焊盘(支撑体)的角部而逐渐增大。
发明内容
在半导体器件中，多个半导体芯片安装在引线框架的管芯焊盘或插接板上。另一方面，近年来，已经促进了半导体器件的小型化。由于本发明人的研究，已经发现，当在这种半导体器件中两个相邻的半导体芯片经由接合线彼此耦接时，担心接合线由于密封树脂的流动而变形，由此导致相邻接合线之间的短路。从本说明书的说明和附图中将使其他问题和新特征变得清晰。
根据一个实施例，第一半导体芯片和第二半导体芯片安装在芯片安装部上，它们经由多条接合线彼此耦接。第一半导体芯片的第一边面对第二半导体芯片的第五边。第一半导体芯片具有沿第一边布置的多个第一电极焊盘，并且第二半导体芯片具有沿第五边布置的多个第二电极焊盘。第一接合线，第二接合线，第三接合线以及第四接合线沿第一边依次排列。当从垂直于芯片安装部的方向观察时，第一接合线和第二接合线之间的间隔的最大值大于第二接合线和第三接合线之间的间隔的最大值。而且，第二接合线和第三接合线之间的间隔的最大值大于第三接合线和第四接合线之间的间隔的最大值。
根据另一实施例，第一半导体芯片和第二半导体芯片安装在芯片安装部上，它们经由多条接合线彼此耦接。第一半导体芯片的第一边面对第二半导体芯片的第五边。第一半导体芯片具有沿第一边布置的多个第一电极焊盘，并且第二半导体芯片具有沿第五边布置的多个第二电极焊盘。第一接合线，第二接合线，第三接合线以及第四接合线沿第一边依次排列。当从垂直于芯片安装部的方向观察时，耦接至第一接合线的第二电极焊盘和耦接至第二接合线的第二电极焊盘之间的间隔大于耦接至第二接合线的第二电极焊盘和耦接至第三接合线的第二电极焊盘之间的间隔。而且，耦接至第二接合线的第二电极焊盘和耦接至第三接合线的第二电极焊盘之间的间隔大于耦接至第三接合线的第二电极焊盘和耦接至第四接合线的第二电极焊盘之间的间隔。
根据上述各个实施例，当相邻的两个半导体芯片经由接合线彼此耦接时，可以抑制相邻接合线之间的短路。
附图说明
图1是说明根据一个实施例的半导体器件的构造的截面图；
图2是该半导体器件的平面图；
图3是放大由图2中的虚线α围绕的区域的示意图；
图4是说明图3中的线弯曲的状态的示意图；
图5是第二半导体芯片的平面图；
图6是说明第二半导体芯片的电路和元件的布局的平面图；
图7是示意性说明第二半导体芯片的部分电路的电路图；
图8是说明制造半导体器件的方法的示意图；
图9是说明制造半导体器件的方法的示意图；
图10是说明制造半导体器件的方法的示意图；
图11是说明执行使用密封树脂进行密封步骤的设备的构造的平面图；
图12是用于解释将导致线流动的密封树脂的流动的示意图；
图13是根据第一变型的半导体器件的平面图；
图14是放大图13中的区域α的示意图；
图15是根据第二变型的半导体器件的平面图；
图16是放大图15中的区域α的示意图；
图17是说明根据第三变型的半导体器件的构造的截面图；以及
图18是说明根据第四变型的半导体器件的构造的截面图。
具体实施方式
以下将参考附图说明优选实施例。各个附图中示出的相同或相似的部件由相同的参考数字指示，并且将适当省略其重复说明。
(实施例)
图1是说明根据一个实施例的半导体器件SD的构造的截面图。根据本实施例的半导体器件SD具有其中第一半导体芯片SC1和第二半导体芯片SC2安装在芯片安装部DP的第一表面上的构造。芯片安装部DP例如是引线框架的管芯焊盘。第一半导体芯片SC1经由接合线WIR1耦接至第一端子TER1，同时第二半导体芯片SC2经由接合线WIR2耦接至第二端子TER2。第一端子TER1和第二端子TER2例如是引线框架的引线端子。第一半导体芯片SC1和第二半导体芯片SC2经由接合线WIR3彼此耦接。接合线WIR1、WIR2和WIR3例如是金线，但也可以由另一金属(例如铜)形成。
芯片安装部DP的第一表面、第一半导体芯片SC1、第二半导体芯片SC2以及接合线WIR1、WIR2和WIR3由密封树脂MDR密封。在该图中所示的实例中，半导体器件SD是QFN(四方无引脚封装)。因此，第一端子TER1和第二端子TER2的端表面形成为与密封树脂MDR的端表面相同的表面。芯片安装部DP的表面(第二表面)与第一表面相反，并且第一端子TER1和第二端子TER2中的每一个的表面从密封树脂MDR的底表面露出以构成与其底表面相同的表面。但是，半导体器件SD可以具有另一封装结构。
图2是半导体器件SD的平面图。在本示意图中，出于说明目的，省略密封树脂MDR。这里，图1对应于图2中的A-A'截面。
第一半导体芯片SC1的平面形状是矩形，即，例如具有1.5或更小长宽比的正方形或长方形。第一半导体芯片SC1具有第一边SID1、第二边SID2、第三边SID3以及第四边SID4。第一边SID1面对第二半导体芯片SC2的第五边SID5。第二SID2是面对第一边SID1的边，并且第三边SID3和第四边SID4是其余的两个边。
第一半导体芯片SC1具有多个电极焊盘PAD1。电极焊盘PAD1沿第一半导体芯片SC1的四个边布置。随着半导体器件高集成度的发展，第一半导体芯片SC1的一个边的长度例如是1.5mm或更大且2.0mm或更小。电极焊盘PAD1等距布置。相邻的电极焊盘PAD1之间的间隔例如是75um或更小。但是，位于邻近第一半导体芯片SC1的四个角的八个电极焊盘PAD1被布置成略离开位于邻近它们的电极焊盘PAD1。
沿第一边SID1布置的电极焊盘PAD1(第一电极焊盘PAD11)经由接合线WIR3耦接至第二半导体芯片SC2。沿第二边SID2、第三边SID3以及第四边SID4布置的电极焊盘PAD1经由接合线WIR1耦接至第一端子TER1。
在本示意图中示出的实例中，第一半导体芯片SC1是通用微控制器(微控制器(MCU：微控制单元)或微处理器(MPU：微处理单元))。因此，各个没有耦接至接合线的电极焊盘PAD1(未耦接的电极焊盘UCPAD1)被设置在第一半导体芯片SC1中。在本示意图中示出的实例中，未耦接的电极焊盘UCPAD1被设置在各自被布置在第一半导体芯片SC1的四个边中的每一个处的区域中。但是，第一半导体芯片SC1的至少一个边可以不具有未耦接的电极焊盘UCPAD1。
第二半导体芯片SC2例如具有用于电流控制的逻辑电路以及晶体管(下文说明的功率晶体管PTR)，并且其平面形状大于第一半导体芯片SC1的平面形状。具体而言，第二半导体芯片SC2是具有2.0或更大的长宽比的长方形。第二半导体芯片SC2的长边的长度是6.0mm或更大且6.5mm或更小，其大于第一边SID1的长度。另一方面，第二半导体芯片SC2的短边的长度是2.0mm或更大且3.0mm或更小。
第二半导体芯片SC2具有第五边SID5、第六边SID6、第七边SID7以及第八边SID8。第五边SID5面对第一半导体芯片SC1的第一边SID1。第六边SID6面对第五边SID5。在本示意图中所示的实例中，第五边SID5和第六边SID6是第二半导体芯片SC2的长边。第二半导体芯片SC2剩下的两个边(第七边SID7以及第八边SID8)是短边。
第二半导体芯片SC2具有多个电极焊盘PAD2。电极焊盘PAD2沿第二半导体芯片SC2的四个边布置。相邻的电极焊盘PAD2之间的间隔彼此不同，这取决于相邻的电极焊盘耦接至第二半导体芯片SC2中的哪个元件。因此，电极焊盘PAD2之间的间隔比电极焊盘PAD1之间的间隔更随机。因此，电极焊盘PAD2之间的间隔的分散程度大于电极焊盘PAD1之间的间隔的分散程度。
在沿第二半导体芯片SC2的第五边SID5布置的电极焊盘PAD2中，在第五边SID5延伸的方向上位于与第一半导体芯片SC1的第一边SID1重叠的部分中的电极焊盘PAD2(第二电极焊盘PAD21)中的大部分经由接合线WIR3耦接至第一半导体芯片SC1。另一方面，在沿第五边SID5布置的电极焊盘PAD2中，在第五边SID5延伸的方向上位于没有与第一半导体芯片SC1的第一边SID1重叠的部分中的大部分电极焊盘PAD2经由接合线WIR2耦接至第二端子TER2。沿第六边SID6布置的电极焊盘PAD2、沿第七边SID7布置以及沿第八边SID8布置的电极焊盘PAD2也都经由接合线WIR2耦接至第二端子TER2。
这里，各自没有耦接至接合线的电极焊盘PAD2(未耦接的电极焊盘UCPAD2)也被设置在第二半导体芯片SC2中。但是，未耦接的电极焊盘UCPAD2的数量小于未耦接的电极焊盘UCPAD1的数量。
在本示意图中所示的实例中，芯片安装部DP、第一端子TER1以及第二端子TER2形成引线框架。因此，悬置引脚SL附接在芯片安装部DP的四个角中的每一个中。
因为这种引线框架是通用引线框架，芯片安装部DP是正方形的。芯片安装部DP的一个边的长度例如是7.0mm或更大且7.5mm或更小。这里，芯片安装部DP的一个边的长度和第二半导体芯片SC2的长边的长度之间的差是1.0mm或更大且1.5mm或更小。因此，第一半导体芯片SC1的第二边SID2的长度以及第二半导体芯片SC2的第七边SID7的长度的总长度与芯片安装部DP的一个边的长度之间的差在某种程度上变大。为了减小接合线WIR3的长度，需要使第一半导体芯片SC1和第二半导体芯片SC2彼此接近。但是，借助这种构造，接合线WIR1的长度和接合线WIR2的长度之和变大。因此，出于减小半导体器件SD具有的接合线的总长度的目的，第一半导体芯片SC1的第一边SID1和第二半导体芯片SC2的第五边SID5彼此在某种程度上间隔开。因此，接合线WIR3的长度在某种程度上变大。第一边SID1和第五边SID5之间的距离例如是1.0mm或更大且1.5mm或更小。
图3是其中放大由图2中的虚线α围绕的区域的示意图。如上所述，电极焊盘PAD1(第一电极焊盘PAD11)在第一半导体芯片SC1的第一边SID1并排布置，而电极焊盘PAD2(第二电极焊盘PAD21)在第二半导体芯片SC2的靠近第二边SID2的区域中并排布置。这些第一电极焊盘PAD11一对一地经由接合线WIR3耦接至第二电极焊盘PAD21。第一电极焊盘PAD11和第二电极焊盘PAD21之间的间隔例如在垂直于第一边SID1的方向上是1.0mm或更大。
详细来说，接合线WIR3包括第一接合线WIR31、第二接合线WIR32、第三接合线WIR33以及第四接合线WIR34。这四条线依次沿第一边SID1布置。具体而言，第一接合线WIR31、第二接合线WIR32、第三接合线WIR33以及第四接合线WIR34在从第三边SID3朝向第四边SID4的方向上依次排列。
耦接至第一接合线WIR31的第一电极焊盘PAD11(第一电极焊盘PAD111)和耦接至第二接合线WIR32的第一电极焊盘PAD11(第一电极焊盘PAD112)之间的间隔几乎等于第一电极焊盘PAD112和耦接至第三接合线WIR33的第一电极焊盘PAD11(第一电极焊盘PAD113)之间的间隔。第一电极焊盘PAD112和第一电极焊盘PAD113之间的间隔几乎等于第一电极焊盘PAD113和耦接至第四接合线WIR34的第一电极焊盘PAD11(第一电极焊盘PAD114)之间的间隔。未耦接的电极焊盘UCPAD1没有被设置在第一电极焊盘PAD111和第一电极焊盘PAD114之间，即第一接合线WIR31和第四接合线WIR34之间。
另一方面，耦接至第一接合线WIR31的第二电极焊盘PAD21(第二电极焊盘PAD211)和耦接至第二接合线WIR32的第二电极焊盘PAD21(第一电极焊盘PAD212)之间的间隔大于第二电极焊盘PAD212和耦接至第三接合线WIR33的第二电极焊盘PAD21(第二电极焊盘PAD213)之间的间隔。而且，第二电极焊盘PAD212和第二电极焊盘PAD213之间的间隔大于第二电极焊盘PAD213和耦接至第四接合线WIR34的第二电极焊盘PAD21(第二电极焊盘PAD214)之间的间隔。
因此，当从垂直于芯片安装部的方向观察时，第一接合线WIR31和第二接合线WTR32之间的间隔的最大值大于第二接合线WIR32和第三接合线WIR33之间的间隔的最大值。而且，第二接合线WIR32和第三接合线WIR33之间的间隔的最大值大于第三接合线WIR33和第四接合线WIR34之间的间隔的最大值。这里，这些接合线之间的间隔被定义为例如平行于第一边SID1的方向上的间隔。
借助这种构造，如图4中所示，当从第三边SID3朝向第四边SID4的方向上注入密封树脂MDR时，即使接合线WIR3(特别地，第一接合线WIR31)在随着发生线流动而在朝向第四边SID4凸出的方向上弯曲的情况下，也可以抑制相邻的接合线WIR3之间的短路。
在本示意图中所示的实例中以及在位于比第二电极焊盘PAD212更靠近第八边SID8的至少四个第二电极焊盘PAD21中，第二电极焊盘PAD21与位于邻近上述第二电极焊盘PAD21以及靠近第八边SID8的第二电极焊盘PAD21之间的间隔变得随接近第八边SID8而越来越小(例如5μm或更大且15μm或更小的量)。因此，可以进一步抑制相邻的接合线WIR3之间的短路。
在本示意图中所示的实例中，在第一接合线WIR31、第二接合线WIR32、第三接合线WIR33以及第四接合线WIR34的端部中，位于第五边SID5一侧的端部在平面图中在接近第七边SID7的方向上倾斜。
在本示意图中所示的实例中，位于最靠近第四边SID4的接合线WIR3(第五接合线WIR35)和位于邻近第五接合线WIR35的第六接合线WIR36之间的间隔的最大值小于第一接合线WIR31和第二接合线WIR32之间的间隔。
而且，位于最靠近第三边SID3的接合线WIR3(第七接合线WIR37)和位于邻近第七接合线WIR37的接合线WIR3(在这里说明的本实例中是第一接合线WIR31)之间的间隔大于第一接合线WIR31和第二接合线WIR32之间的间隔。
在本示意图中所示的实例中，至少一个未耦接的电极焊盘UCPAD1被设置在耦接至第七接合线WIR37的第一电极焊盘PAD11(第一电极焊盘PAD117)和第一电极焊盘PAD111之间。因此，即使第二电极焊盘PAD211和耦接至第七接合线WIR37的第二电极焊盘PAD21(第二电极焊盘PAD217)之间的间隔小于第二电极焊盘PAD211和第二电极焊盘PAD212之间的间隔，也可以增加第一接合线WIR31和第七接合线WIR37之间的间隔的最大值。
图5是第二半导体芯片SC2的平面图。图6是说明第二半导体芯片SC2的电路和元件的布局的平面图。图7是示意性示出第二半导体芯片SC2的部分电路的电路图。
如图6中所示，逻辑电路CIR设置为靠近第二半导体芯片SC2的第五边SID5和第八边SID8。沿第五边SID5设置的电极焊盘PAD2以及沿第八边SID8设置的电极焊盘PAD2全部都耦接至逻辑电路CIR。
如图6中所示，多个功率晶体管PTR设置为靠近第六边SID6和第七边SID7。具体而言，功率晶体管PTR1和功率晶体管PTR2被布置为在垂直于第六边SID6的方向上排列。在第六边SID6和第七边SID7附近，耦接至功率晶体管PTR的电极焊盘PAD2位于处于功率晶体管PTR1和PTR2之间的区域上。因此，沿第六边SID6布置的电极焊盘PAD2和第六边SID6之间的距离大于沿第五边SID5布置的电极焊盘PAD2和第五边SID5之间的距离。类似地，沿第七边SID7布置的电极焊盘PAD2和第七边SID7之间的距离大于沿第五边SID5布置的电极焊盘PAD2和第五边SID5之间的距离。
详细来说，电极焊盘PAD221、PAD222和PAD223耦接至功率晶体管PTR。如图7中的示意性等效电路中所示，电源电压Vcc施加至电极焊盘PAD221，并且地电势Vs施加至电极焊盘PAD223。电极焊盘PAD222作为功率晶体管PTR的输出端子。
沿第六边SID6布置的电极焊盘PAD2和第六边SID6之间的距离大于沿第五边SID5布置的电极焊盘PAD2和第五边SID5之间的距离，因此可以增加位于邻近第二端子TER2的接合线WIR2和接合线WIR2耦接到的第二端子TER2之间的距离。因此，可以抑制接合线WIR2和接合线WIR2原本不应该耦接到的第二端子TER2之间的短路。在耦接至沿第七边SID7布置的电极焊盘PAD2的接合线WIR2中也能获得这种优势。
以下，将参考图8至10说明制造半导体器件SD的方法。
首先提供第一半导体芯片SC1和第二半导体芯片SC2。例如如下制造第一半导体芯片SC1和第二半导体芯片SC2。
首先在半导体衬底中形成元件隔离膜。由此隔离元件形成区。例如通过采用STI方法形成元件隔离膜，但可以通过采用LOCOS方法形成。随后，在位于元件形成区中的半导体衬底中形成栅极绝缘膜和栅电极。栅极绝缘膜可以是氧化硅膜或具有高于氧化硅膜的介电常数的高介电常数膜(例如硅酸铪膜)。当栅极绝缘膜是氧化硅膜时，通过多晶硅膜形成栅电极。替代地，当栅极绝缘膜是高介电常数膜时，通过金属膜(例如TiN膜)和多晶硅膜的叠层膜形成栅电极。当通过多晶硅形成栅电极时，在形成栅电极的步骤中，多晶硅电阻可以形成在元件隔离膜上。
在第二半导体芯片SC2中，在上述步骤中形成功率晶体管PTR。替代地，可以在不同于形成其他晶体管的栅极绝缘膜的步骤的步骤中形成功率晶体管PTR的栅极绝缘膜。
随后，在位于元件形成区中的半导体衬底中形成用于源极和漏极的延伸区。随后，在栅电极的侧壁中形成侧壁。随后，在位于元件形成区中的半导体衬底中形成用作源极和漏极的杂质区。因此，MOS晶体管形成在半导体衬底上。
随后，多层互连层形成在元件隔离膜和MOS晶体管上。电极焊盘(电极焊盘PAD1或电极焊盘PAD2)形成在最上层互连层中。随后，保护绝缘膜(钝化膜)形成在多层互连层上。位于电极焊盘上的开口形成在保护绝缘膜中。
提供图8中所示的芯片安装部DP。在本示意图中所示的实例中，芯片安装部DP是引线框架。多个芯片安装部DP形成所谓的MAP型，其中它们通过框架耦接在一起。
随后，如图9中所示，第一半导体芯片SC1和第二半导体芯片SC2安装在各个芯片安装部DP上。第一半导体芯片SC1和第二半导体芯片SC2可以通过采用诸如银浆的浆料或通过采用DAF(管芯附接膜)安装在芯片安装部上。
随后，如图10中所示，第一半导体芯片SC1的电极焊盘PAD1经由接合线WIR1耦接至第一端子TER1。而且，第二半导体芯片SC2的电极焊盘PAD2经由接合线WIR2耦接至第二端子TER2。而且，第一半导体芯片SC1的第一电极焊盘PAD11和第二半导体芯片SC2的第二电极焊盘PAD21经由接合线WIR3彼此耦接。
随后，芯片安装部DP，以及第一半导体芯片SC1、第二半导体芯片SC2以及位于芯片安装部DP上的接合线WIR1、WIR2和WIR3都由密封树脂MDR密封。随后分别分离半导体器件SD。
图11是采用密封树脂MDR执行密封步骤的装置的构造的平面图。在本示意图中所示的实例中，密封树脂MDR被保持在树脂保持部PT中。其中保持MAP型芯片安装部DP的间隙S和树脂保持部PT经由流动沟道FC耦接在一起。当密封树脂MDR从树脂保持部PT中挤出时，被挤出的密封树脂MDR经由流动沟道FC流入间隙S中。由此，芯片安装部DP等由密封树脂MDR密封。因此，在密封步骤中，密封树脂MDR从芯片安装部DP的一个方向流入。
图12是用于说明将导致线流动的密封树脂MDR流动的示意图。如上所述，在密封步骤中，密封树脂MDR从芯片安装部DP的一个方向(箭头β方向)流入。在本实施例中，MAP型的芯片安装部DP布置在图11中所示的间隙S中，使得密封树脂MDR从第一半导体芯片SC1的第三边SID3的边流入，换言之，使得第三边SID3面对流动沟道FC。因此，当平面观察时，接合线WIR3在向第四边SID4凸出的方向上弯曲。但是，在本实施例中，接合线WIR3之间的间隔部分地增大，并且因此即使在平面图中，接合线WIR3弯曲，也可以抑制相邻接合线WIR3之间的短路。
而且，位于靠近第四边SID4的接合线WIR3之间的间隔小于位于靠近第三边SID3的接合线WIR3之间的间隔。因此，可以抑制第一半导体芯片SC1的第一电极焊盘PAD11之间的间隔和第二半导体芯片SC2的第二电极焊盘PAD21之间的间隔的平均值增大，即，可以抑制这些半导体芯片尺寸的增加。
特别地，在本实施例中，第二半导体芯片SC2是长方形的。因此，当通用引线框架用作芯片安装部DP时，第一半导体芯片SC1的第二边SID2的长度以及第二半导体芯片SC2的第七边SID7的长度的总长度和芯片安装部DP的一个边的长度之间的差在某种程度上变大。因此，为了减小半导体器件SD的接合线的总长度，需要第一半导体芯片SC1的第一边SID1和第二半导体芯片SC2的第五边SID5在某种程度上彼此间隔开。在这种情况下，接合线WIR3在某种程度上变长，并且因此更可能导致与上述线流动有关的问题。但是同样在这种情况下，即使接合线WIR3弯曲，也可以抑制相邻接合线WIR3之间的短路。
(第一变型例)
图13是根据第一变型例的半导体器件SD的平面图。图14是其中放大了图13中的区域α的示意图。图13和图14分别对应于实施例中的图2和3。除了第一电极焊盘PAD11和第二电极焊盘PAD21的布置之外，根据本变型例的半导体器件SD具有与根据实施例的半导体器件SD相同的构造。
详细来说，在本示意图中所示的实例中，在平面图中，在第一接合线WIR31、第二接合线WIR32、第三接合线WIR33以及第四接合线WIR34中，第五边SID5一侧的端部在接近第八边SID7的方向上倾斜。因此，在沿第一边SID1的方向上，在靠近第一边SID1两端的部分中的每一个中并排设置多个未耦接的电极焊盘UCPAD1。
而且，在第一边SID1中设置多行电极焊盘PAD1。但是，位于靠近中心(位于内部)的所有电极焊盘PAD1都是未耦接的电极焊盘UCPAD1。
也可以在本变型例中获得与实施例中相同的优势。
(第二变型例)
图15是根据第二变型例的半导体器件SD的平面图。图16是其中放大了图15中的区域α的示意图。图15和16分别对应于实施例中的图2和3。除以下要点之外，根据本变型例的半导体器件SD具有和根据实施例的半导体器件SD相同的构造。
首先，第一半导体芯片SC1的平面形状也是长方形。第一边SID1和第二边SID2是第一半导体芯片SC1的长边，而第三边SID3和第四边SID4是其短边。
接合线WIR3被分成两组GR1和GR2。当平面观察时，属于组GR1的接合线WIR3在相对于第一边SID1相同的方向上倾斜。当平面观察时，属于组GR2的接合线WIR3在与属于组GR1的接合线WIR3的倾斜方向相反的方向上倾斜。详细来说，当平面观察时，属于组GR1的接合线WIR3在其位于第二电极焊盘PAD21的端部接近第八边SID8的方向上倾斜。而且，当平面观察时，属于组GR2的接合线WIR3在其位于第一电极焊盘PAD11的端部接近第四边SID4的方向上倾斜。
在属于组GR1的接合线WIR3、两者都耦接至前述接合线WIR3的第一电极焊盘PAD11以及第二电极焊盘PAD21的关系与实施例中所述情况相同。在属于组GR2的接合线WIR3、两者耦接至前述接合线WIR3的第一电极焊盘PAD11以及第二电极焊盘PAD21的关系也与实施例中所述情况相同。
也可以在本变型例中获得与实施例中相同的优势。
(第三变型例)
图17是说明根据第三变型例的半导体器件SD的构造的截面图。除用于第一半导体芯片SC1和第二半导体芯片SC2的密封结构是QFP(四方扁平封装)之外，本示意图中所示的半导体器件SD具有与根据实施例、第一变型例以及第二变型例中任一个的半导体器件SD相同的构造。
详细来说，芯片安装部DP的第二表面由密封树脂MDR覆盖。第一端子TER1和第二端子TER2是引线端子并延伸到密封树脂MDR外部。
也可以在本变型例中获得与实施例中相同的优势。
(第四变型例)
图18是说明根据第四变型例的半导体器件SD的构造的截面图。除用于第一半导体芯片SC1和第二半导体芯片SC2的密封结构是BGA(球栅阵列)之外，本示意图中所示的半导体器件SD具有与根据实施例、第一变型例以及第二变型例中任一个的半导体器件SD相同的构造。
详细来说，芯片安装部DP是插接板，并且各条接合线WIR1和WIR2都耦接至插接板的第一表面上的指状结构(finger)。这些指状结构都通经由插接板中的布线和通孔耦接至设置在插接板的第二表面中的焊球SB。
密封树脂MDR的端表面形成为与插接板(芯片安装部DP)的端表面相同的表面。但是，密封树脂MDR的端表面可以位于插接板的端表面内部。
也可以在本变型例中获得与实施例中相同的优势。
已经基于优选实施例在上文具体说明了本发明人提出的本发明，但是本发明不应局限于优选实施例，并且毋容质疑的是在不脱离本发明主旨的范围内可对本发明进行各种变型。

Claims (9)

1.一种半导体器件，包括：
第一半导体芯片，所述第一半导体芯片是具有第一边、面对所述第一边的第二边、第三边以及第四边的矩形；
第二半导体芯片，所述第二半导体芯片是具有第五边、面对所述第五边的第六边、第七边以及第八边的矩形；
芯片安装部，在所述芯片安装部的相同表面上安装有所述第一半导体芯片和所述第二半导体芯片；以及
多条接合线，所述多条接合线将所述第一半导体芯片耦接至所述第二半导体芯片，
其中，所述第一半导体芯片的所述第一边面对所述第二半导体芯片的所述第五边，
其中，所述第一半导体芯片具有沿所述第一边布置的多个第一电极焊盘，
其中，所述第二半导体芯片具有沿所述第五边布置的多个第二电极焊盘，
其中，在所述接合线中，第一接合线、第二接合线、第三接合线以及第四接合线沿所述第一边依次排列，
其中，当从垂直于所述芯片安装部的方向观察时，所述第一接合线和所述第二接合线之间的间隔的最大值大于所述第二接合线和所述第三接合线之间的间隔的最大值，并且
其中，当从垂直于所述芯片安装部的方向观察时，所述第二接合线和所述第三接合线之间的间隔的最大值大于所述第三接合线和所述第四接合线之间的间隔的最大值。
2.根据权利要求1所述的半导体器件，
其中，当从垂直于所述芯片安装部的方向观察时，所述第一接合线比所述第四接合线更靠近所述第三边，并且在朝向所述第四边凸出的方向上弯曲。
3.根据权利要求1所述的半导体器件，
其中，所述第五边长于所述第一边，并且
其中，所述第二半导体芯片是长方形，并且所述第五边是长方形的长边。
4.根据权利要求3所述的半导体器件，
其中，所述第一接合线、所述第二接合线、所述第三接合线以及所述第四接合线一对一地将所述第一电极焊盘耦接至所述第二电极焊盘，并且
其中，耦接至所述第一接合线的所述第二电极焊盘和耦接至所述第二接合线的所述第二电极焊盘之间的间隔大于耦接至所述第二接合线的所述第二电极焊盘和耦接至所述第三接合线的所述第二电极焊盘之间的间隔，并且
其中，耦接至所述第二接合线的所述第二电极焊盘和耦接至所述第三接合线的所述第二电极焊盘之间的间隔大于耦接至所述第三接合线的所述第二电极焊盘和耦接至所述第四接合线的所述第二电极焊盘之间的间隔。
5.根据权利要求1所述的半导体器件，
其中，所述第一半导体芯片具有未耦接电极焊盘，所述未耦接电极焊盘沿所述第一边布置并且位于与所述第一接合线和所述第四接合线之间的间隔不同的位置处，并且所述接合线没有耦接至所述未耦接电极焊盘。
6.一种半导体器件，包括：
第一半导体芯片，所述第一半导体芯片是具有第一边、面对所述第一边的第二边、第三边以及第四边的矩形；
第二半导体芯片，所述第二半导体芯片是具有第五边、面对所述第五边的第六边、第七边以及第八边的矩形；
芯片安装部，在所述芯片安装部的相同表面上安装有所述第一半导体芯片和所述第二半导体芯片；以及
多条接合线，所述多条接合线将所述第一半导体芯片耦接至所述第二半导体芯片，
其中，所述第一半导体芯片的所述第一边面对所述第二半导体芯片的所述第五边，并且
其中，所述第一半导体芯片具有沿所述第一边布置的多个第一电极焊盘，并且
其中，所述第二半导体芯片具有沿所述第五边布置的多个第二电极焊盘，并且
其中，在所述接合线中，第一接合线、第二接合线、第三接合线以及第四接合线沿所述第一边依次排列，并且它们一对一地将所述第一电极焊盘耦接至所述第二电极焊盘，并且
其中，当从垂直于所述芯片安装部的方向观察时，耦接至所述第一接合线的所述第二电极焊盘和耦接至所述第二接合线的所述第二电极焊盘之间的间隔大于耦接至所述第二接合线的所述第二电极焊盘和耦接至所述第三接合线的所述第二电极焊盘之间的间隔，并且
其中，当从垂直于所述芯片安装部的方向观察时，耦接至所述第二接合线的所述第二电极焊盘和耦接至所述第三接合线的所述第二电极焊盘之间的间隔大于耦接至所述第三接合线的所述第二电极焊盘和耦接至所述第四接合线的所述第二电极焊盘之间的间隔。
7.根据权利要求6所述的半导体器件，
其中，当从垂直于所述芯片安装部的方向观察时，所述第一接合线比所述第四接合线更靠近所述第三边，并且在朝向所述第四边凸出的方向上弯曲。
8.根据权利要求6所述的半导体器件，
其中，所述第五边长于所述第一边，并且
其中，所述第二半导体芯片是长方形，并且所述第五边是长方形的长边。
9.一种制造半导体器件的方法，包括以下步骤：
在芯片安装部的相同表面上安装第一半导体芯片和第二半导体芯片，所述第一半导体芯片是具有第一边、面对所述第一边的第二边、第三边以及第四边的矩形，所述第二半导体芯片是具有第五边、面对所述第五边的第六边、第七边以及第八边的矩形；
用多条接合线耦接所述第一半导体芯片和所述第二半导体芯片；并且
通过从所述第三边一侧注入密封树脂，来用所述密封树脂密封所述第一半导体芯片、所述第二半导体芯片以及所述接合线，
其中，所述第一半导体芯片的所述第一边面对所述第二半导体芯片的所述第五边，
其中，所述第一半导体芯片具有沿所述第一边布置的多个第一电极焊盘，
其中，所述第二半导体芯片具有沿所述第五边布置的多个第二电极焊盘，
其中，在所述接合线中，第一接合线、第二接合线、第三接合线以及第四接合线沿所述第一边从所述第三边一侧依次排列，并且它们一对一地将所述第一电极焊盘耦接至所述第二电极焊盘，
其中，当从垂直于所述芯片安装部的方向观察时，耦接至所述第一接合线的所述第二电极焊盘和耦接至所述第二接合线的所述第二电极焊盘之间的间隔大于耦接至所述第二接合线的所述第二电极焊盘和耦接至所述第三接合线的所述第二电极焊盘之间的间隔，并且
其中，当从垂直于所述芯片安装部的方向观察时，耦接至所述第二接合线的所述第二电极焊盘和耦接至所述第三接合线的所述第二电极焊盘之间的间隔大于耦接至所述第三接合线的所述第二电极焊盘和耦接至所述第四接合线的所述第二电极焊盘之间的间隔。
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