JP2015029033A - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP2015029033A JP2015029033A JP2013226097A JP2013226097A JP2015029033A JP 2015029033 A JP2015029033 A JP 2015029033A JP 2013226097 A JP2013226097 A JP 2013226097A JP 2013226097 A JP2013226097 A JP 2013226097A JP 2015029033 A JP2015029033 A JP 2015029033A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- conductor
- via hole
- wiring board
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 134
- 239000004065 semiconductor Substances 0.000 claims abstract description 90
- 230000002787 reinforcement Effects 0.000 claims abstract description 8
- 230000003014 reinforcing effect Effects 0.000 claims description 58
- 238000009413 insulation Methods 0.000 abstract 4
- 239000011159 matrix material Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 57
- 239000000758 substrate Substances 0.000 description 19
- 230000008646 thermal stress Effects 0.000 description 12
- 230000008602 contraction Effects 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09618—Via fence, i.e. one-dimensional array of vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
【解決手段】下面に下層導体5を有する絶縁層3と、絶縁層3上に形成された四角形状の半導体素子搭載部1aと、半導体素子搭載部1aに格子状に配列された複数の半導体素子接続パッド10と、半導体素子接続パッド10下の絶縁層3に下層導体5を底面として形成されたビアホール7aと、ビアホール7a内に下層導体5と接続するように充填されており、半導体素子接続パッド10と一体的に形成されたビア導体9aと、を具備して成る配線基板Aであって、半導体素子搭載部1aの角部における半導体素子接続パッド10の配列よりも外側の領域の絶縁層3に、下層導体5を底面として形成された補強用ビアホール7bと、補強用ビアホール7b内に下層導体5と接続するように形成された補強用ビア導体9bとが形成されている。
【選択図】図1
Description
配線基板Bは、絶縁基板21と、配線導体22と、絶縁層23とを備えている。配線基板Bの上面中央部には、大型の半導体素子Sを搭載するための半導体素子搭載部21aが形成されている。
配線基板Aは、絶縁基板1と、配線導体2と、絶縁層3とを備えている。配線基板Aの上面中央部には、例えば、演算処理用等の大型の半導体素子Sを搭載するための半導体素子搭載部1aが形成されている。
また、上述の実施形態の一例では、図1(a)に示したように、半導体素子搭載部1aの角部以外における半導体素子接続パッド10の配列よりも外側の領域の絶縁層3には、補強用ビアホール7bを形成していないが、この領域の絶縁層3に補強用ビアホール7bおよび補強用ビア導体9bを形成しても良い。
このような補強用ビアホール7dを形成する場合、絶縁層3下面の下層導体5の外周部を残した状態で補強用ビアホール7dを形成しておき、補強用ビア導体9eの下面が第2下層導体5aに接続されるとともに、補強用ビア導体9eの側面の一部が上述の下層導体5の外周部と接続されるように充填することが好ましい。
このように、一体的に形成された補強用ビア導体9eを第2下層導体5aに加えて下層導体5にも接続することで、補強用ビア導体9eと各下層導体5、5aとの接続面積が大きくなり、補強用ビア導体9eが補強用ビアホール7d内に強固に固定される。このため、半導体素子Sと配線基板A4との熱伸縮差により大きな熱応力が生じても、強固に固定された補強用ビア導体9eに熱応力を分散させることで、半導体素子搭載部1aの角部における半導体素子接続パッド10下のビア導体9aと各下層導体5、5aとの接続部に熱応力が集中的に作用することを回避できる。
3 絶縁層
5 下層導体
7a ビアホール
7b 補強用ビアホール
9a ビア導体
9b 補強用ビア導体
10 半導体素子接続パッド
A 配線基板
Claims (3)
- 下面に下層導体を有する絶縁層と、該絶縁層上に形成された四角形状の半導体素子搭載部と、前記半導体素子搭載部に格子状に配列された複数の半導体素子接続パッドと、前記半導体素子接続パッド下の前記絶縁層に前記下層導体を底面として形成されたビアホールと、該ビアホール内に前記下層導体と接続するように充填されており、前記半導体素子接続パッドと一体的に形成されたビア導体と、を具備して成る配線基板であって、前記半導体素子搭載部の角部における前記半導体素子接続パッドの配列よりも外側の領域の前記絶縁層に、前記下層導体を底面として形成された補強用ビアホールと、該補強用ビアホール内に前記下層導体と接続するように形成された補強用ビア導体とが形成されていることを特徴とする配線基板。
- 下面に第1下層導体を有する第1絶縁層と、該第1絶縁層上に形成された四角形状の半導体素子搭載部と、該半導体素子搭載部に格子状に配列された複数の半導体素子接続パッドと、該半導体素子接続パッド下の前記第1絶縁層に前記第1下層導体を底面として形成されたビアホールと、該ビアホール内に前記第1下層導体と接続するように充填されており、前記半導体素子接続パッドと一体的に形成されたビア導体と、前記第1絶縁層の下側に被着されており、下面に第2下層導体を有する第2絶縁層と、を具備して成る配線基板であって、前記半導体素子搭載部の角部における前記半導体素子接続パッドの配列よりも外側の領域の前記第1絶縁層に形成された第1補強用ビアホールと、該第1補強用ビアホール内に充填された第1補強用ビア導体と、前記第1補強用ビアホールの直下の前記第2絶縁層に前記第2下層導体を底面として形成された第2補強用ビアホールと、該第2補強用ビアホール内に充填された第2補強用ビア導体と、が形成されていることを特徴とする配線基板。
- 前記第1および第2補強用ビアホールが前記第1および第2絶縁層を連通する一体的なビアホールとして形成されており、該ビアホール内に前記第1および第2補強用ビア導体が一体的なビア導体として形成されていることを特徴とする請求項2記載の配線基板。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013226097A JP6096640B2 (ja) | 2013-06-28 | 2013-10-31 | 配線基板 |
TW103121688A TW201507565A (zh) | 2013-06-28 | 2014-06-24 | 配線基板 |
KR1020140077882A KR20150002493A (ko) | 2013-06-28 | 2014-06-25 | 배선 기판 |
CN201410290780.8A CN104254194A (zh) | 2013-06-28 | 2014-06-25 | 布线基板 |
US14/317,538 US20150000970A1 (en) | 2013-06-28 | 2014-06-27 | Wiring board |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013135845 | 2013-06-28 | ||
JP2013135845 | 2013-06-28 | ||
JP2013226097A JP6096640B2 (ja) | 2013-06-28 | 2013-10-31 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015029033A true JP2015029033A (ja) | 2015-02-12 |
JP6096640B2 JP6096640B2 (ja) | 2017-03-15 |
Family
ID=52114500
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013226097A Active JP6096640B2 (ja) | 2013-06-28 | 2013-10-31 | 配線基板 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20150000970A1 (ja) |
JP (1) | JP6096640B2 (ja) |
KR (1) | KR20150002493A (ja) |
CN (1) | CN104254194A (ja) |
TW (1) | TW201507565A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10777503B2 (en) | 2017-05-11 | 2020-09-15 | Schweizer Electronic Ag | Method for contacting a metallic contact pad in a printed circuit board and printed circuit board |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016209480A1 (en) * | 2015-06-24 | 2016-12-29 | Intel Corporation | Combined rear cover and enhanced diffused reflector for display stack |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003078247A (ja) * | 2001-08-30 | 2003-03-14 | Kyocera Corp | 配線基板およびその製造方法 |
JP2005039241A (ja) * | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
JP2006339316A (ja) * | 2005-05-31 | 2006-12-14 | Toshiba Corp | 半導体装置、半導体装置実装基板、および半導体装置の実装方法 |
JP2009071299A (ja) * | 2007-08-23 | 2009-04-02 | Kyocera Corp | 配線基板 |
JP2009260255A (ja) * | 2008-03-25 | 2009-11-05 | Panasonic Corp | 半導体装置および多層配線基板ならびにそれらの製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5860256B2 (ja) * | 2011-09-26 | 2016-02-16 | 京セラサーキットソリューションズ株式会社 | 配線基板 |
TWI476888B (zh) * | 2011-10-31 | 2015-03-11 | Unimicron Technology Corp | 嵌埋穿孔中介層之封裝基板及其製法 |
-
2013
- 2013-10-31 JP JP2013226097A patent/JP6096640B2/ja active Active
-
2014
- 2014-06-24 TW TW103121688A patent/TW201507565A/zh unknown
- 2014-06-25 KR KR1020140077882A patent/KR20150002493A/ko not_active Application Discontinuation
- 2014-06-25 CN CN201410290780.8A patent/CN104254194A/zh active Pending
- 2014-06-27 US US14/317,538 patent/US20150000970A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003078247A (ja) * | 2001-08-30 | 2003-03-14 | Kyocera Corp | 配線基板およびその製造方法 |
JP2005039241A (ja) * | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
JP2006339316A (ja) * | 2005-05-31 | 2006-12-14 | Toshiba Corp | 半導体装置、半導体装置実装基板、および半導体装置の実装方法 |
JP2009071299A (ja) * | 2007-08-23 | 2009-04-02 | Kyocera Corp | 配線基板 |
JP2009260255A (ja) * | 2008-03-25 | 2009-11-05 | Panasonic Corp | 半導体装置および多層配線基板ならびにそれらの製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10777503B2 (en) | 2017-05-11 | 2020-09-15 | Schweizer Electronic Ag | Method for contacting a metallic contact pad in a printed circuit board and printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
KR20150002493A (ko) | 2015-01-07 |
US20150000970A1 (en) | 2015-01-01 |
CN104254194A (zh) | 2014-12-31 |
TW201507565A (zh) | 2015-02-16 |
JP6096640B2 (ja) | 2017-03-15 |
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