JP2015018860A - Semiconductor package manufacturing method - Google Patents

Semiconductor package manufacturing method Download PDF

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JP2015018860A
JP2015018860A JP2013143533A JP2013143533A JP2015018860A JP 2015018860 A JP2015018860 A JP 2015018860A JP 2013143533 A JP2013143533 A JP 2013143533A JP 2013143533 A JP2013143533 A JP 2013143533A JP 2015018860 A JP2015018860 A JP 2015018860A
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semiconductor element
mold resin
solder
heat sink
adhesion
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水野　直仁
Naohito Mizuno
直仁 水野
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To appropriately improve heat resistance of an adhesive auxiliary film sandwiched between a heat sink and a mold resin in a manufacturing method of a semiconductor package which encapsulates a semiconductor element soldered on the heat sink with the mold resin.SOLUTION: A semiconductor package manufacturing method comprises: coating and arranging an adhesive auxiliary film 100 on a portion of one surface 11 of a heat sink 10 other than a portion where a solder 30 is arranged; curing the coated adhesive auxiliary film 100 at a temperature higher than a melting point of the solder 30 and subsequently soldering the heat sink 10 and the semiconductor element 20 via the solder 30; and subsequently, encapsulating the soldered heat sink 10 and semiconductor element 20 with a mold resin 40.

Description

本発明は、基材上に半導体素子をはんだ付けしたものをモールド樹脂で封止してなる半導体パッケージの製造方法に関し、特に基材とモールド樹脂との間に介在する密着補助膜の耐熱性向上に関する。   The present invention relates to a method for manufacturing a semiconductor package in which a semiconductor element is soldered on a base material and sealed with a mold resin, and in particular, the heat resistance improvement of an adhesion auxiliary film interposed between the base material and the mold resin. About.

従来より、この種の半導体パッケージとしては、基材と、基材上にはんだを介してはんだ付けされた半導体素子と、基材および半導体素子を封止するモールド樹脂と、基材および半導体素子とモールド樹脂との間に介在し、モールド樹脂の密着性を確保するための密着補助膜と、を備えたものが提案されている（たとえば、特許文献１参照）。   Conventionally, as this type of semiconductor package, a base material, a semiconductor element soldered onto the base material via solder, a mold resin that seals the base material and the semiconductor element, a base material and the semiconductor element, There has been proposed a film provided with an adhesion auxiliary film for interposing between the mold resin and ensuring the adhesion of the mold resin (for example, see Patent Document 1).

このような半導体パッケージは、基材上に半導体素子をはんだ付けした後、基材および半導体素子の表面に、密着補助膜を設け、その後、モールド樹脂による封止を行うことにより製造される。ここで、密着補助膜は、ポリイミド等の熱硬化性材料よりなるもので、塗布した後、加熱して硬化させることにより設けられる。   Such a semiconductor package is manufactured by soldering a semiconductor element on a base material, providing an adhesion auxiliary film on the surface of the base material and the semiconductor element, and then sealing with a mold resin. Here, the adhesion assisting film is made of a thermosetting material such as polyimide, and is provided by being heated and cured after being applied.

特開２００６−１７９５３８号公報JP 2006-179538 A

ところで、このような半導体パッケージは、より高温での使用が求められている。ここで、当該半導体パッケージにおいては、半導体素子の表面には通常ポリイミド系樹脂よりなる保護膜が設けられているため、半導体素子とモールド樹脂との密着性は、基材とモールド樹脂との密着性に比べて十分に確保される。   By the way, such a semiconductor package is required to be used at a higher temperature. Here, in the semiconductor package, since a protective film made of a polyimide resin is usually provided on the surface of the semiconductor element, the adhesion between the semiconductor element and the mold resin is the adhesion between the substrate and the mold resin. It is sufficiently secured compared to

そこで、基材とモールド樹脂との密着性をより高めるべく、基材表面に設けられる密着補助膜の耐熱性を向上させることが求められている。そのためには、密着補助膜をより高温で硬化させることで、高い使用温度であっても、密着補助膜の硬化状態を維持することが必要となる。密着補助膜の硬化温度が低く、当該硬化が不十分な状態では、基材とモールド樹脂との密着性の確保も不十分となる。   Therefore, in order to further improve the adhesion between the substrate and the mold resin, it is required to improve the heat resistance of the adhesion auxiliary film provided on the substrate surface. For this purpose, it is necessary to maintain the cured state of the adhesion assisting film by curing the adhesion assisting film at a higher temperature even at a high use temperature. When the curing temperature of the adhesion auxiliary film is low and the curing is insufficient, the adhesion between the base material and the mold resin is also insufficient.

しかし、上記従来の製造方法では、半導体素子と基材とをはんだ付けした後、密着補助膜を基材表面に塗布して硬化させていた。そのため、密着補助膜の硬化温度をより高温化させようとすると、当該硬化温度が、はんだの融点を越えてしまい、はんだ付け部分の接合性が損なわれてしまう恐れがある。   However, in the above conventional manufacturing method, after soldering the semiconductor element and the base material, the adhesion auxiliary film is applied to the surface of the base material and cured. For this reason, if the curing temperature of the adhesion assisting film is to be increased, the curing temperature exceeds the melting point of the solder, which may impair the solderability of the soldered portion.

本発明は、上記問題に鑑みてなされたものであり、基材上に半導体素子をはんだ付けしたものをモールド樹脂で封止してなる半導体パッケージの製造方法において、基材とモールド樹脂との間に介在する密着補助膜の耐熱性を適切に向上させることを目的とする。   The present invention has been made in view of the above problems, and in a method for manufacturing a semiconductor package in which a semiconductor element is soldered on a base material and sealed with a mold resin, the base material and the mold resin are provided. The object is to appropriately improve the heat resistance of the adhesion auxiliary film interposed in the film.

上記目的を達成するため、請求項１に記載の発明では、基材（１０）と、基材上にはんだ（３０）を介してはんだ付けされた半導体素子（２０）と、基材および半導体素子を封止するモールド樹脂（４０）と、基材とモールド樹脂との間に介在し、基材とモールド樹脂との密着性を確保するための熱硬化性材料よりなる密着補助膜（１００）と、を備える半導体パッケージを製造する半導体パッケージの製造方法であって、
基材および半導体素子を用意する用意工程と、基材の表面のうちはんだが配置される部位以外の部位に、密着補助膜を塗布して配置する膜配置工程と、塗布された密着補助膜を、はんだの融点よりも高い温度で硬化する硬化工程と、しかる後、基材と半導体素子とを、はんだを介してはんだ付けするはんだ付け工程と、はんだ付けされた基材および半導体素子をモールド樹脂で封止する封止工程と、を備えることを特徴とする。 In order to achieve the above object, according to the first aspect of the present invention, a base material (10), a semiconductor element (20) soldered onto the base material via a solder (30), the base material, and the semiconductor element A mold resin (40) for sealing the substrate, and an adhesion auxiliary film (100) made of a thermosetting material that is interposed between the substrate and the mold resin and ensures adhesion between the substrate and the mold resin. A semiconductor package manufacturing method for manufacturing a semiconductor package comprising:
A preparation step of preparing a base material and a semiconductor element, a film placement step of applying and placing an adhesion auxiliary film on a portion of the surface of the substrate other than a portion where solder is arranged, and an applied adhesion auxiliary film A curing process for curing at a temperature higher than the melting point of the solder, a soldering process for soldering the base material and the semiconductor element via solder, and a mold resin for the soldered base material and the semiconductor element And a sealing step of sealing with.

それによれば、はんだ付けする前に、はんだの融点よりも高い温度で密着補助膜を硬化させるので、従来のようなはんだの溶融を回避しつつ、密着補助膜の硬化温度を高めることができる。よって、本発明によれば、密着補助膜の耐熱性を適切に向上させることができ、高温信頼性に優れた半導体パッケージを提供することができる。   According to this, since the adhesion assisting film is cured at a temperature higher than the melting point of the solder before soldering, the curing temperature of the adhesion assisting film can be increased while avoiding melting of the solder as in the prior art. Therefore, according to the present invention, the heat resistance of the adhesion auxiliary film can be appropriately improved, and a semiconductor package excellent in high-temperature reliability can be provided.

なお、特許請求の範囲およびこの欄で記載した各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。   In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

本発明の実施形態にかかる半導体パッケージの概略断面図である。1 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention. 図１に示される半導体パッケージの製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor package shown by FIG. 図２に続く製造方法を示す工程図である。FIG. 3 is a process diagram illustrating a manufacturing method subsequent to FIG. 2.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各図相互において、互いに同一もしくは均等である部分には、説明の簡略化を図るべく、図中、同一符号を付してある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, parts that are the same or equivalent to each other are given the same reference numerals in the drawings for the sake of simplicity.

本発明の実施形態にかかる半導体パッケージＰ１について、図１を参照して述べる。この半導体パッケージＰ１は、たとえば自動車などの車両に搭載され、車両用の各種電子装置を駆動するための装置として適用されるものである。   A semiconductor package P1 according to an embodiment of the present invention will be described with reference to FIG. The semiconductor package P1 is mounted on a vehicle such as an automobile and is applied as a device for driving various electronic devices for the vehicle.

本実施形態の半導体パッケージＰ１は、大きくは、基材としてのヒートシンク１０と、ヒートシンク１０の一面１１上にはんだ３０を介してはんだ付けされた半導体素子２０と、ヒートシンク１０および半導体素子２０を封止するモールド樹脂４０と、を備えて構成されている。   The semiconductor package P1 of the present embodiment is roughly sealed by a heat sink 10 as a base material, a semiconductor element 20 soldered on one surface 11 of the heat sink 10 via a solder 30, and the heat sink 10 and the semiconductor element 20. Mold resin 40 to be configured.

ヒートシンク１０は半導体素子２０に発生する熱を逃がす放熱機能を有するもので、本実施形態では、表裏の板面の一方を一面１１、他方を他面１２とし、これら両板面１１、１２を連結する側面１３を有する板状をなすものである。   The heat sink 10 has a heat radiating function for releasing heat generated in the semiconductor element 20. In this embodiment, one of the front and back plate surfaces is one surface 11 and the other is the other surface 12, and both the plate surfaces 11 and 12 are connected. It forms the plate shape which has the side surface 13 to do.

このようなヒートシンク１０は、Ｃｕ（銅）やＮｉ（ニッケル）、Ｆｅ（鉄）などの金属よりなるもので、ここでは、はんだ付け性の向上等の点から表面にＡｕ等のめっき１０ａが施されている。このヒートシンク１０は、平面サイズが半導体素子２０よりも大きいものであり、ヒートシンク１０の一面１１の一部にて、半導体素子２０のはんだ付けがなされている。   Such a heat sink 10 is made of a metal such as Cu (copper), Ni (nickel), or Fe (iron). Here, from the viewpoint of improving solderability, the surface is plated with Au or the like 10a. Has been. The heat sink 10 has a larger planar size than the semiconductor element 20, and the semiconductor element 20 is soldered on a part of one surface 11 of the heat sink 10.

半導体素子２０は、たとえばＳｉ（シリコン）やＳｉＣ（シリコンカーバイド）、ＧａＮ（ガリウムナイトライド）などの半導体よりなるもので、通常の半導体プロセスにより、形成されたものであり、具体的には、ＭＯＳトランジスタ、ＩＧＢＴ等のパワー素子などが挙げられる。また、通常のものと同様に、半導体素子２０の表面（はんだ付け面とは反対側の面）は、ポリイミド系樹脂よりなる保護膜２０ａにより構成されている
ヒートシンク１０と半導体素子２０とを接合するはんだ３０としては、Ｓｎ−Ａｇ系、Ｓｎ−Ｎｉ−Ｃｕ−Ｐ系、Ｓｎ−Ｓｂ系、Ｓｎ−Ｐｂ系等の各種はんだ材料が用いられる。これらのはんだ材料は、融点がたとえば１８０℃〜２５０℃程度のものである。 The semiconductor element 20 is made of a semiconductor such as Si (silicon), SiC (silicon carbide), or GaN (gallium nitride), and is formed by a normal semiconductor process. Examples thereof include power elements such as transistors and IGBTs. Further, like the normal one, the surface of the semiconductor element 20 (the surface opposite to the soldering surface) joins the semiconductor element 20 to the heat sink 10 formed of a protective film 20a made of polyimide resin. As the solder 30, various solder materials such as Sn—Ag, Sn—Ni—Cu—P, Sn—Sb, and Sn—Pb are used. These solder materials have a melting point of about 180 ° C. to 250 ° C., for example.

そして、ヒートシンク１０および半導体素子２０の外側には、ＣｕやＮｉなどの金属よりなるリード端子５０が設けられており、このリード端子５０と半導体素子２０とは、ボンディングワイヤ６０により接合され、電気的に導通している。   A lead terminal 50 made of a metal such as Cu or Ni is provided outside the heat sink 10 and the semiconductor element 20. The lead terminal 50 and the semiconductor element 20 are joined by a bonding wire 60 and electrically Is conducting.

ここで、ボンディングワイヤ６０は、ＡｕやアルミニウムやＣｕなどよりなるもので、通常のワイヤボンディングにより形成される。なお、半導体素子２０におけるワイヤ６０との接合部分には、図示しないが、保護膜２０ａより開口するパッドが設けられており、このパッドとワイヤ６０とが接合されている。   Here, the bonding wire 60 is made of Au, aluminum, Cu, or the like, and is formed by ordinary wire bonding. In addition, although not illustrated, a pad that opens from the protective film 20 a is provided at a portion where the semiconductor element 20 is joined to the wire 60, and the pad and the wire 60 are joined.

そして、モールド樹脂４０は、これらヒートシンク１０、半導体素子２０、はんだ３０、リード端子５０、ボンディングワイヤ６０を包み込むように封止している。このモールド樹脂４０は、エポキシ樹脂等の通常のモールド材料よりなるもので、金型成形やポッティング等により形成されている。   The mold resin 40 is sealed so as to enclose the heat sink 10, the semiconductor element 20, the solder 30, the lead terminal 50, and the bonding wire 60. The mold resin 40 is made of a normal mold material such as an epoxy resin, and is formed by molding or potting.

なお、リード端子５０の一部は、モールド樹脂４０から突出しており、半導体パッケージＰ１と外部との信号のやりとりを行うべく、図示しない外部配線などに電気的に接続されるようになっている。また、ヒートシンク１０の他面１２側がモールド樹脂４０より露出することで、放熱性を高めている。   A part of the lead terminal 50 protrudes from the mold resin 40, and is electrically connected to an external wiring (not shown) or the like in order to exchange signals between the semiconductor package P1 and the outside. Further, the heat dissipation is improved by exposing the other surface 12 side of the heat sink 10 from the mold resin 40.

このような構成において、さらに本実施形態の半導体パッケージＰ１では、ヒートシンク１０とモールド樹脂４０との密着性を確保するため密着補助膜１００が、ヒートシンク１０とモールド樹脂４０との間に介在している。   In such a configuration, in the semiconductor package P1 of the present embodiment, the adhesion auxiliary film 100 is interposed between the heat sink 10 and the mold resin 40 in order to ensure adhesion between the heat sink 10 and the mold resin 40. .

この密着補助膜１００は、ヒートシンク１０の表面のうちはんだ３０が配置される部位以外の部位に、配置されている。具体的に、本実施形態では、ヒートシンク１０の一面１１のうちのはんだ３０の配置部分以外の部位にて、モールド樹脂４０との間に密着補助膜１００が配置されている。   The adhesion auxiliary film 100 is disposed on a portion of the surface of the heat sink 10 other than the portion where the solder 30 is disposed. Specifically, in the present embodiment, the adhesion auxiliary film 100 is disposed between the heat sink 10 and the mold resin 40 at a portion other than the portion where the solder 30 is disposed on the one surface 11 of the heat sink 10.

このような密着補助膜１００は、ポリイミド等の熱硬化性材料よりなるもので、塗布および加熱硬化により形成されるものである。たとえば、密着補助膜１００となるポリイミドとしては、日立化成デュポンマイクロシステムズ社製のＰＩＸ１４００、ＰＩＸ６４００（いずれも商品名）などが挙げられる。   Such an adhesion assisting film 100 is made of a thermosetting material such as polyimide, and is formed by coating and heat curing. For example, examples of the polyimide used as the adhesion assisting film 100 include PIX1400 and PIX6400 (both trade names) manufactured by Hitachi Chemical DuPont Microsystems.

また、本実施形態では、密着補助膜１００は、リード端子５０の表面のうちボンディングワイヤ６０と接続される部位以外の部位にも配置されている。これにより、リード端子５０とこれを封止するモールド樹脂４０との密着性も確保するようにしている。   In the present embodiment, the adhesion assisting film 100 is also disposed on a portion of the surface of the lead terminal 50 other than the portion connected to the bonding wire 60. Thereby, the adhesion between the lead terminal 50 and the mold resin 40 for sealing the lead terminal 50 is also ensured.

次に、本実施形態の半導体パッケージＰ１の製造方法について、図２、図３を参照して述べる。まず、用意工程にて、ヒートシンク１０および半導体素子２０を用意する。ヒートシンク１０は、切削、プレス、めっき等の工程を経て作製され、半導体素子２０は半導体プロセスにより作製される。   Next, a method for manufacturing the semiconductor package P1 of the present embodiment will be described with reference to FIGS. First, the heat sink 10 and the semiconductor element 20 are prepared in a preparation process. The heat sink 10 is manufactured through processes such as cutting, pressing, and plating, and the semiconductor element 20 is manufactured by a semiconductor process.

次に、図２（ａ）に示されるように、ヒートシンク１０とリード端子５０とを所定の位置に配置する。このとき、リード端子５０がたとえばリードフレーム素材よりなる場合には、このリードフレーム素材とヒートシンク１０とを、接着やかしめ等により固定した状態とする。   Next, as shown in FIG. 2A, the heat sink 10 and the lead terminal 50 are arranged at predetermined positions. At this time, when the lead terminal 50 is made of, for example, a lead frame material, the lead frame material and the heat sink 10 are fixed by bonding or caulking.

そして、図２（ｂ）に示されるように、ヒートシンク１０の一面１１のうちはんだ３０が配置される部位以外の部位、および、リード端子５０の表面のうちボンディングワイヤ６０と接続される部位以外の部位に、密着補助膜１００としてのポリイミドを塗布して配置する（膜配置工程）。   Then, as shown in FIG. 2B, a part other than the part where the solder 30 is arranged on the one surface 11 of the heat sink 10 and a part other than the part connected to the bonding wire 60 on the surface of the lead terminal 50. The polyimide as the adhesion assisting film 100 is applied and arranged on the site (film arrangement process).

続いて、オーブン等を用いて、塗布された密着補助膜１００を、はんだ３０の融点よりも高い温度で硬化する（硬化工程）。たとえば、上記したＳｎ−Ａｇ系等のはんだ３０の融点は、１８０〜２５０℃であるが、当該ポリイミドの硬化温度は、たとえば２５０℃〜３５０℃の範囲ではんだ融点よりも高いものとする。   Subsequently, the applied adhesion assisting film 100 is cured at a temperature higher than the melting point of the solder 30 using an oven or the like (curing step). For example, the melting point of the above-described Sn-Ag solder 30 is 180 to 250 ° C., and the curing temperature of the polyimide is higher than the solder melting point in the range of 250 to 350 ° C., for example.

この後、図２（ｃ）に示されるように、ヒートシンク１０と半導体素子２０とを、はんだ３０を介してはんだ付けする（はんだ付け工程）。このときのはんだリフロー温度は、上記したＳｎ−Ａｇ系等のはんだ３０の場合、たとえば２３０〜３００℃程度である。   Thereafter, as shown in FIG. 2C, the heat sink 10 and the semiconductor element 20 are soldered via the solder 30 (soldering step). The solder reflow temperature at this time is, for example, about 230 to 300 ° C. in the case of the above-described Sn-Ag solder 30.

その後、図３（ａ）に示されるように、通常のワイヤボンディング方法を用いることにより、リード端子５０と半導体素子２０とをボンディングワイヤ６０で接続する（ワイヤ接続工程）。   Thereafter, as shown in FIG. 3A, the lead terminal 50 and the semiconductor element 20 are connected by the bonding wire 60 by using a normal wire bonding method (wire connection process).

そして、はんだ付けされたヒートシンク１０および半導体素子２０、さらに、リード端子５０およびボンディングワイヤ６０を含む構造体を、金型等に設置して樹脂成形を行うことにより、モールド樹脂４０で封止する（封止工程）。その後は、必要に応じて、リード端子５０についてリードカット等を行うことにより、本実施形態の半導体パッケージＰ１ができあがる。   Then, the structure including the soldered heat sink 10 and the semiconductor element 20 and further the lead terminal 50 and the bonding wire 60 is placed in a mold or the like and is molded with resin, thereby sealing with the mold resin 40 ( Sealing step). Thereafter, if necessary, the lead terminal 50 is subjected to lead cutting or the like, thereby completing the semiconductor package P1 of the present embodiment.

ところで、本実施形態によれば、はんだ付け工程の前に、はんだ３０の融点よりも高い温度で密着補助膜１００を硬化させるので、従来のようなはんだ３０の溶融を回避しつつ、密着補助膜１００の硬化温度を高めることができる。よって、本実施形態によれば、密着補助膜１００の耐熱性を適切に向上させることができ、高温信頼性に優れた半導体パッケージＰ１を提供することができる。   By the way, according to the present embodiment, since the adhesion auxiliary film 100 is cured at a temperature higher than the melting point of the solder 30 before the soldering process, the adhesion auxiliary film is avoided while avoiding melting of the solder 30 as in the prior art. The curing temperature of 100 can be increased. Therefore, according to the present embodiment, the heat resistance of the adhesion auxiliary film 100 can be appropriately improved, and the semiconductor package P1 excellent in high temperature reliability can be provided.

たとえば、半導体素子２０として、ＳｉＣを用いた場合、ＳｉＣは、Ｓｉに比べバンドギャップが約３倍と大きく、２００℃以上の高温で使用できる。本実施形態では、密着補助膜１００の耐熱性を向上した半導体パッケージＰ１とすることにより、ＳｉＣよりなる半導体素子２０の特長を有効に発揮できることになる。   For example, when SiC is used as the semiconductor element 20, SiC has a band gap that is about three times that of Si and can be used at a high temperature of 200 ° C. or higher. In the present embodiment, by using the semiconductor package P1 in which the heat resistance of the adhesion assisting film 100 is improved, the features of the semiconductor element 20 made of SiC can be effectively exhibited.

（他の実施形態）
なお、密着補助膜１００としては、塗布して加熱により硬化させることで上記密着性を確保する機能を有するものならば、上記したポリイミドに限定されるものではない。たとえば、その他、ポリアミドイミド系、シアネート系の樹脂等が挙げられる。 (Other embodiments)
The adhesion auxiliary film 100 is not limited to the above-described polyimide as long as it has a function of ensuring the adhesion by applying and curing by heating. For example, other examples include polyamideimide-based and cyanate-based resins.

また、基材としては、半導体素子２０がはんだ付けできるものであればよく、上記したヒートシンク１０以外にも、リードフレームのアイランドでもよいし、その他、可能ならば各種の配線基板等であってもよい。   The base material may be any material as long as the semiconductor element 20 can be soldered. In addition to the heat sink 10 described above, a lead frame island may be used. Good.

また、半導体パッケージとしては、少なくとも半導体素子がはんだ付けされた基材をモールド樹脂４０で封止したものであればよく、可能ならば、上記図１におけるリード端子５０やボンディングワイヤ６０が省略された構成であってもよい。   Further, as the semiconductor package, it is sufficient that at least the base material to which the semiconductor element is soldered is sealed with the mold resin 40. If possible, the lead terminal 50 and the bonding wire 60 in FIG. 1 are omitted. It may be a configuration.

また、上記実施形態では、半導体素子２０の片面側のみにヒートシンク１０をはんだ付けした片面放熱タイプのパッケージを示した。ここで、半導体パッケージとしては、図１の半導体素子２０においてヒートシンク１０側とは反対側の面にも、図示しないもう１つのヒートシンクをはんだ付けしてなる両面放熱タイプのものであってもよい。この場合、当該もう１つのヒートシンクについて、同様に密着補助膜１００を設ければよい。   Moreover, in the said embodiment, the single-sided thermal radiation type package which soldered the heat sink 10 only to the single side | surface side of the semiconductor element 20 was shown. Here, the semiconductor package may be of a double-sided heat dissipation type in which another heat sink (not shown) is soldered to the surface opposite to the heat sink 10 side in the semiconductor element 20 of FIG. In this case, the adhesion auxiliary film 100 may be similarly provided for the other heat sink.

また、上記図１では、密着補助膜１００は、ヒートシンク１０の一面１１上に設けられていたが、さらに、ヒートシンク１０の表面のうちはんだ３０が配置される部位以外の部位であってモールド樹脂４０で封止される部位として、ヒートシンク１０の側面１３にも、密着補助膜１００を設けてもよい。   In FIG. 1, the adhesion assisting film 100 is provided on the one surface 11 of the heat sink 10, but the mold resin 40 is a part other than the part where the solder 30 is disposed on the surface of the heat sink 10. As a part sealed by the step, the adhesion auxiliary film 100 may be provided also on the side surface 13 of the heat sink 10.

また、上記図１では、ヒートシンク１０の他面１２側がモールド樹脂４０より露出するパッケージ、いわゆるハーフモールド構造のパッケージであったが、さらに、ヒートシンク１０の他面１２側もモールド樹脂４０で封止されたパッケージであってもよい。この場合、ヒートシンク１０の他面１２に対しても、上記同様に、密着補助膜１００を設けてやればよい。   In FIG. 1, the package is a package in which the other surface 12 side of the heat sink 10 is exposed from the mold resin 40, that is, a package having a so-called half mold structure. It may be a package. In this case, the adhesion auxiliary film 100 may be provided on the other surface 12 of the heat sink 10 as described above.

また、モールド樹脂４０および密着補助膜１００のガラス転移温度は、１８０℃以上であることが望ましい。これは、２００℃程度の高温においても、モールド樹脂４０と基材との剥離を抑制しやすいためである。   The glass transition temperatures of the mold resin 40 and the adhesion assisting film 100 are desirably 180 ° C. or higher. This is because peeling between the mold resin 40 and the base material is easily suppressed even at a high temperature of about 200 ° C.

また、本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。また、上記各実施形態は、互いに無関係なものではなく、組み合わせが明らかに不可な場合を除き、適宜組み合わせが可能であり、また、上記各実施形態は、上記の図示例に限定されるものではない。また、上記各実施形態において、実施形態を構成する要素は、特に必須であると明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。また、上記各実施形態において、実施形態の構成要素の個数、数値、量、範囲等の数値が言及されている場合、特に必須であると明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではない。また、上記各実施形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に特定の形状、位置関係等に限定される場合等を除き、その形状、位置関係等に限定されるものではない。   Further, the present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope described in the claims. The above embodiments are not irrelevant to each other, and can be combined as appropriate unless the combination is clearly impossible, and the above embodiments are not limited to the illustrated examples. Absent. In each of the above-described embodiments, it is needless to say that elements constituting the embodiment are not necessarily essential unless explicitly stated as essential and clearly considered essential in principle. Yes. Further, in each of the above embodiments, when numerical values such as the number, numerical value, quantity, range, etc. of the constituent elements of the embodiment are mentioned, it is clearly limited to a specific number when clearly indicated as essential and in principle. The number is not limited to the specific number except for the case. Further, in each of the above embodiments, when referring to the shape, positional relationship, etc. of the component, etc., the shape, unless otherwise specified and in principle limited to a specific shape, positional relationship, etc. It is not limited to the positional relationship or the like.

１０ 基材としてのヒートシンク
２０ 半導体素子
３０ はんだ
４０ モールド樹脂
１００ 密着補助膜 DESCRIPTION OF SYMBOLS 10 Heat sink as a base material 20 Semiconductor element 30 Solder 40 Mold resin 100 Adhesion assistance film

Claims (2)

基材（１０）と、
前記基材上にはんだ（３０）を介してはんだ付けされた半導体素子（２０）と、
前記基材および前記半導体素子を封止するモールド樹脂（４０）と、
前記基材と前記モールド樹脂との間に介在し、前記基材と前記モールド樹脂との密着性を確保するための熱硬化性材料よりなる密着補助膜（１００）と、を備える半導体パッケージを製造する半導体パッケージの製造方法であって、
前記基材および前記半導体素子を用意する用意工程と、
前記基材の表面のうち前記はんだが配置される部位以外の部位に、前記密着補助膜を塗布して配置する膜配置工程と、
前記塗布された密着補助膜を、前記はんだの融点よりも高い温度で硬化する硬化工程と、
しかる後、前記基材と前記半導体素子とを、前記はんだを介してはんだ付けするはんだ付け工程と、
前記はんだ付けされた前記基材および前記半導体素子を前記モールド樹脂で封止する封止工程と、を備えることを特徴とする半導体パッケージの製造方法。 A substrate (10);
A semiconductor element (20) soldered onto the substrate via solder (30);
A mold resin (40) for sealing the substrate and the semiconductor element;
Manufacturing a semiconductor package comprising an adhesion auxiliary film (100) made of a thermosetting material, which is interposed between the substrate and the mold resin, and ensures adhesion between the substrate and the mold resin. A method of manufacturing a semiconductor package comprising:
A preparation step of preparing the substrate and the semiconductor element;
A film placement step of applying and placing the adhesion auxiliary film on a portion of the surface of the substrate other than the portion where the solder is placed;
A curing step of curing the applied adhesion assisting film at a temperature higher than the melting point of the solder;
Thereafter, a soldering step of soldering the base material and the semiconductor element via the solder;
And a sealing step of sealing the soldered base material and the semiconductor element with the mold resin. 前記半導体パッケージにおいては、基材の外側にリード端子（５０）が設けられ、このリード端子と前記半導体素子とがボンディングワイヤ（６０）により接続されており、これらリード端子およびボンディングワイヤも前記モールド樹脂で封止されており、
膜配置工程では、前記リード端子の表面のうち前記ボンディングワイヤと接続される部位以外の部位に、前記密着補助膜を塗布して配置するようにし、
前記はんだ付け工程と前記封止工程との間に、前記リード端子と前記半導体素子とを前記ボンディングワイヤで接続するワイヤ接続工程を行うことを特徴とする請求項１に記載の半導体パッケージの製造方法。 In the semiconductor package, a lead terminal (50) is provided on the outside of the base material, and the lead terminal and the semiconductor element are connected by a bonding wire (60). Sealed with
In the film arranging step, the adhesion auxiliary film is applied and arranged on a portion other than the portion connected to the bonding wire on the surface of the lead terminal,
2. The method of manufacturing a semiconductor package according to claim 1, wherein a wire connection step of connecting the lead terminal and the semiconductor element with the bonding wire is performed between the soldering step and the sealing step. .
JP2013143533A 2013-07-09 2013-07-09 Semiconductor package manufacturing method Pending JP2015018860A (en)

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US11387210B2 (en) 2019-03-15 2022-07-12 Fuji Electric Co., Ltd. Semiconductor module and manufacturing method therefor

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