JP2015008254A - Circuit board, method of manufacturing the same, method of manufacturing semiconductor device, and method of manufacturing mounting substrate - Google Patents

Circuit board, method of manufacturing the same, method of manufacturing semiconductor device, and method of manufacturing mounting substrate Download PDF

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JP2015008254A
JP2015008254A JP2013133520A JP2013133520A JP2015008254A JP 2015008254 A JP2015008254 A JP 2015008254A JP 2013133520 A JP2013133520 A JP 2013133520A JP 2013133520 A JP2013133520 A JP 2013133520A JP 2015008254 A JP2015008254 A JP 2015008254A
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solder
circuit board
melting point
manufacturing
semiconductor device
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優樹 梅村
Yuki Umemura
優樹 梅村
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of obtaining a sufficient stand-off for filling an underfill and having a structure for improving reliability, in a semiconductor device manufactured by bonding a semiconductor chip having a narrow pitch bump structure to a circuit board via solder bumps by a flip-chip method, and to provide a method of manufacturing the same.SOLUTION: In a circuit board 2 including pads for electrical connection with a semiconductor chip 1, a solder bump is provided at the pad on a surface for electrically connecting with the semiconductor chip 1. The solder bump consists of a solder of two layers with different melting points. A lower-layer solder provided at a portion close to the circuit board 2 is made of a high-melting point solder 31, and an upper-layer solder provided at a portion close to the semiconductor chip 1 is made of a low-melting point solder 32.

Description

本発明は、狭ピッチ化するパッドを持つ半導体チップを実装するための回路基板とその製造方法および回路基板に半導体チップを実装した半導体装置の製造方法などに関する。   The present invention relates to a circuit board for mounting a semiconductor chip having pads with a narrow pitch, a manufacturing method thereof, a manufacturing method of a semiconductor device in which a semiconductor chip is mounted on the circuit board, and the like.

近年、半導体装置は高集積化が進行して、半導体実装技術も高密度化が求められている。この半導体装置の高密度実装技術には、ワイヤーボンディング技術、ＴＡＢ技術などが代表的には挙げられるが、最も高密度の実装技術として、フリップチップ実装技術が、コンピュータ機器などの半導体装置を高密度に実装する技術として多く用いられている。 In recent years, semiconductor devices have been highly integrated, and semiconductor packaging technology is also required to have high density. Typical examples of the high-density mounting technology for semiconductor devices include wire bonding technology and TAB technology. As the highest-density mounting technology, flip-chip mounting technology is used for high-density semiconductor devices such as computer equipment. It is often used as a technology to be mounted on.

フリップチップ実装技術は、高密度実装技術として広く公知の技術になっている。フリップチップ実装された半導体装置の基本的構造の一例を図１に示す。図１に示す様に、一般的なフリップチップ実装構造を有する半導体装置では、半導体チップ１、半導体チップ１上に設けられた端子電極であるパッド１１、パッド１１を除く半導体チップ１表面を被覆するパッシベーション膜１３、パッド１１上に設けられたバリアメタル層１２及びバリアメタル層１２上に突出形成されたはんだバンプ３と、対向する回路基板２上にはパッド１４が設けられ、パッド１４を除く部位にはソルダーレジスト膜１５が形成されており、半導体チップ１におけるはんだバンプ３と回路基板２におけるパッド１４とが接合され、その接合によって半導体チップ１と回路基板２の間に形成される空隙部がアンダーフィル１６により充填されている。 The flip chip mounting technique is widely known as a high density mounting technique. An example of the basic structure of a flip chip mounted semiconductor device is shown in FIG. As shown in FIG. 1, in a semiconductor device having a general flip chip mounting structure, a semiconductor chip 1, a pad 11 which is a terminal electrode provided on the semiconductor chip 1, and a surface of the semiconductor chip 1 excluding the pad 11 are covered. The passivation film 13, the barrier metal layer 12 provided on the pad 11, the solder bump 3 projectingly formed on the barrier metal layer 12, and the pad 14 is provided on the opposing circuit board 2, and the portion excluding the pad 14 A solder resist film 15 is formed, and the solder bumps 3 in the semiconductor chip 1 and the pads 14 in the circuit board 2 are joined, and a gap formed between the semiconductor chip 1 and the circuit board 2 by the joining is formed. Filled with underfill 16.

上記半導体装置の製造方法としては、はんだバンプを使用した接続方式では、回路基板のパッド上に予め予備はんだを形成しておき、その予備はんだと半導体チップのはんだバンプとの位置合わせを行う。これらの予備はんだとはんだバンプとをリフロー炉で溶融して接合する。予備はんだの搭載方法としてはペースト状のはんだを印刷し溶融させて搭載する方法や、はんだボールを搭載し溶融させる方法などが知られている。その後、アンダーフィルと呼ばれる封止樹脂をキャピラリーフロー工法によって、半導体チップと回路基板間の空隙部を充填して半導体装置を得る。 As a method for manufacturing the semiconductor device, in the connection method using solder bumps, preliminary solder is formed in advance on the pads of the circuit board, and the preliminary solder and the solder bumps of the semiconductor chip are aligned. These preliminary solders and solder bumps are melted and joined in a reflow furnace. As a pre-solder mounting method, a paste solder is printed and melted and mounted, or a solder ball is mounted and melted. Thereafter, a gap between the semiconductor chip and the circuit board is filled with a sealing resin called underfill by a capillary flow method to obtain a semiconductor device.

本説明では、予備はんだと半導体チップのはんだバンプとの位置合わせを行い、これらの予備はんだとはんだバンプとをリフロー炉で溶融して接合し、アンダーフィルをキャピラリ−フロー工法により充填することを一次実装と呼ぶ。 In this description, the primary soldering and the solder bump of the semiconductor chip are aligned, the preliminary solder and the solder bump are melted and joined in a reflow furnace, and the underfill is filled by the capillary flow method. Called implementation.

最近の高密度実装への要求は、年々高まっており、それに伴いはんだバンプの配置も狭ピッチ化が進んでいる。そのため上記のような予備はんだをリフロー炉で溶融させて接合する従来の実装が難しい場合が出てきている。上記実装方法では予備はんだとはんだバンプを接続する際に、搭載した全てのはんだが溶融する。また、半導体チップの自重が溶融したはんだに加わるため、隣接するはんだバンプが接触し、ショートする不具合が発生する問題がある。 Recently, the demand for high-density mounting has been increasing year by year, and accordingly, the pitch of solder bumps has been reduced. For this reason, there are cases where it is difficult to perform conventional mounting in which the above pre-solder is melted in a reflow furnace and joined. In the above mounting method, when the preliminary solder and the solder bump are connected, all the mounted solder is melted. Further, since the weight of the semiconductor chip is added to the melted solder, there is a problem in that adjacent solder bumps come into contact with each other to cause a short circuit.

はんだの量を少なくすることではんだバンプ同士の接触は避けることができるが、同時に半導体チップと回路基板間のギャップを狭めることになり、樹脂封止の際のボイド発生や、信頼性寿命の低下といった不具合が発生する問題がある。 By reducing the amount of solder, contact between solder bumps can be avoided, but at the same time the gap between the semiconductor chip and the circuit board will be narrowed, resulting in voids during resin sealing and reduced reliability life There is a problem that such a problem occurs.

また、近年このような接続に対して接続信頼性などの対策をとった構造として、半導体チップと回路基板との間にスタンドオフといわれる一定距離を確保した構造がある。特許文献１や特許文献２のように樹脂封止の際のボイド発生や、信頼性の高いフリップチップ接続構造を提供する技術が提案されている。特許文献１に記載の図をもとに、フリップチップ構造の半導体装置を模式的に示した断面図を図２に示す。図２において、半導体チップ１上にはパッド１１と、このパッド１１上に開口を有するパッシベーション膜１３が形成されている。更に、パッド１１上には、密着層２１を介して、銅（Ｃｕ）からなる柱状バンプ２２が形成されている。また、柱状バンプ２２の側面には、酸化膜等からなる濡れ防止膜２３が形成されている。このように、特許文献２では、バンプに銅（Ｃｕ）からなる柱状突起を用い、スタンドオフ（回路基板表面と半導体チップの回路基板側の表面との距離）を稼ぐことで、回路基板の接続時にアンダーフィル樹脂の充填を容易にし、且つ信頼性の向上を図る構造としている。しかしながら、特許文献２においては、このような応力緩和を目的とした構造を開示されているが、銅（Ｃｕ）からなる柱状バンプを使用しているため、バンプ自体が硬い材質であり、バンプの変形による応力の緩和が困難である。従って、スタンドオフを稼ぎアンダーフィル樹脂の充填性が向上しただけでは応力緩和が十分に図れず、層間絶縁膜にクラックが発生するという問題点がある。 In recent years, as a structure taking measures such as connection reliability for such a connection, there is a structure in which a certain distance called a stand-off is secured between the semiconductor chip and the circuit board. As disclosed in Patent Document 1 and Patent Document 2, techniques for generating voids during resin sealing and providing a flip-chip connection structure with high reliability have been proposed. FIG. 2 is a cross-sectional view schematically showing a flip-chip semiconductor device based on the diagram described in Patent Document 1. In FIG. In FIG. 2, a pad 11 and a passivation film 13 having an opening on the pad 11 are formed on the semiconductor chip 1. Furthermore, columnar bumps 22 made of copper (Cu) are formed on the pad 11 via an adhesion layer 21. Further, a wetting prevention film 23 made of an oxide film or the like is formed on the side surface of the columnar bump 22. As described above, in Patent Document 2, the connection between the circuit boards is obtained by using columnar protrusions made of copper (Cu) for the bumps and increasing the standoff (distance between the circuit board surface and the circuit board side surface of the semiconductor chip). In some cases, the underfill resin is easily filled and the reliability is improved. However, Patent Document 2 discloses a structure aiming at such stress relaxation. However, since a columnar bump made of copper (Cu) is used, the bump itself is a hard material, and the bump It is difficult to relieve stress due to deformation. Therefore, there is a problem that stress relaxation cannot be sufficiently achieved only by increasing the standoff and improving the filling property of the underfill resin, and cracks are generated in the interlayer insulating film.

特許第３８２９３２５号公報Japanese Patent No. 3829325 特開平３‐２２４３７号公報JP-A-3-22437

本発明は、かかる問題点に鑑みてなされたものであって、狭ピッチバンプ構造を備えた半導体チップをフリップチップ方式で回路基板にはんだバンプを介して接合することにより製造する半導体装置において、アンダーフィルの充填に充分なスタンドオフが得られ、信頼性が向上する構造の半導体装置とその製造方法を提供することを課題とする。   The present invention has been made in view of such problems, and in a semiconductor device manufactured by bonding a semiconductor chip having a narrow pitch bump structure to a circuit board via a solder bump in a flip-chip manner, It is an object of the present invention to provide a semiconductor device having a structure in which a standoff sufficient for filling with a fill is obtained and reliability is improved, and a manufacturing method thereof.

上記の課題を解決する手段として、請求項１に記載の発明は、フリップチップ方式で半導体チップを実装するための回路基板であって、半導体チップとの電気的接続を行うためのパッドを備えてなり、前記半導体チップとの電気的接続を行う面のパッドには、はんだバンプを備えており、前記はんだバンプは異なる融点を持つ２層のはんだからなり、前記回路基板に近い部位である下層のはんだは高融点はんだからなり、前記半導体チップに近い部位である上層のはんだは低融点はんだからなることを特徴とする回路基板である。   As means for solving the above-mentioned problems, the invention according to claim 1 is a circuit board for mounting a semiconductor chip by a flip chip method, and includes a pad for electrical connection with the semiconductor chip. The pads on the surface that is electrically connected to the semiconductor chip are provided with solder bumps, and the solder bumps are made of two layers of solder having different melting points, and the lower layer is a portion close to the circuit board. The circuit board is characterized in that the solder is made of a high melting point solder, and the upper layer solder that is close to the semiconductor chip is made of a low melting point solder.

また請求項２に記載の発明は、請求項１に記載の回路基板の製造方法であって、
前記回路基板の半導体チップを実装する側のパッド上に高融点はんだを形成するはんだ形成工程と、
高融点はんだの上に低融点はんだを形成する工程と、を備えてなることを特徴とする回路基板の製造方法である。 The invention according to claim 2 is a method of manufacturing a circuit board according to claim 1,
A solder forming step of forming a high melting point solder on a pad on the side of mounting the semiconductor chip of the circuit board;
And a step of forming a low melting point solder on the high melting point solder.

また、請求項３に記載の発明は、前記はんだ形成工程が、印刷工法またはボール搭載工法であることを特徴とする請求項２に記載の回路基板の製造方法である。   The invention according to claim 3 is the circuit board manufacturing method according to claim 2, wherein the solder forming step is a printing method or a ball mounting method.

また、請求項４に記載の発明は、請求項１に記載の回路基板に半導体チップを実装する半導体装置の製造方法であって、
低融点はんだがパッドに形成された半導体チップを前記回路基板にフリップチップ方式で実装するに際して、低融点はんだの融点以上、且つ高融点はんだの融点より低い温度で接合する工程と、
前記半導体チップと前記回路基板によって形成された隙間にアンダーフィルを充填する工
程と、を備えていることを特徴とする半導体装置の製造方法である。 According to a fourth aspect of the present invention, there is provided a manufacturing method of a semiconductor device in which a semiconductor chip is mounted on the circuit board according to the first aspect,
When a semiconductor chip having a low melting point solder formed on a pad is mounted on the circuit board by a flip chip method, the step of bonding at a temperature higher than the melting point of the low melting point solder and lower than the melting point of the high melting point solder;
And a step of filling an underfill in a gap formed by the semiconductor chip and the circuit board.

また、請求項５に記載の発明は、請求項４に記載の半導体装置の製造方法を用いて製造した半導体装置をフリップチップ方式でプリント配線基板に実装する実装基板の製造方法であって、前記半導体装置をフリップチップ方式で前記プリント配線基板に実装するに際して、前記高融点はんだの融点以上に加熱することを特徴とする実装基板の製造方法である。   The invention described in claim 5 is a method for manufacturing a mounting board in which a semiconductor device manufactured by using the method for manufacturing a semiconductor device according to claim 4 is mounted on a printed wiring board in a flip-chip manner. When mounting a semiconductor device on the printed wiring board by a flip-chip method, the mounting board manufacturing method is characterized in that the semiconductor device is heated above the melting point of the high melting point solder.

狭ピッチのバンプ構造を備えた半導体装置において、隣接するはんだバンプがショートすることなく、アンダーフィル樹脂の充填に充分なスタンドオフが得られ、半導体装置使用時において充分な信頼性を得ることのできる構造の回路基板とその製造方法および半導体装置の製造方法などを提供することが出来る。   In a semiconductor device having a narrow-pitch bump structure, a standoff sufficient for filling an underfill resin can be obtained without shorting adjacent solder bumps, and sufficient reliability can be obtained when the semiconductor device is used. A circuit board having a structure, a manufacturing method thereof, a manufacturing method of a semiconductor device, and the like can be provided.

従来の標準的な半導体装置を作製する工程における半導体装置の一例を示す概略断面図。FIG. 10 is a schematic cross-sectional view illustrating an example of a semiconductor device in a process of manufacturing a conventional standard semiconductor device. 従来の標準的なフリップチップ構造の半導体装置の一例を模式的に示した概略断面図。FIG. 10 is a schematic cross-sectional view schematically showing an example of a conventional semiconductor device having a standard flip chip structure. 本発明における回路基板の一例を示す概略断面図。1 is a schematic cross-sectional view showing an example of a circuit board in the present invention. 本発明における回路基板の製造方法の一例を示す概略断面図。The schematic sectional drawing which shows an example of the manufacturing method of the circuit board in this invention. 本発明における半導体装置の製造方法の一例を示す概略断面図。1 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the present invention. 本発明における実装基板の製造方法の一例を示す概略断面図。The schematic sectional drawing which shows an example of the manufacturing method of the mounting substrate in this invention.

以下、本発明の実施形態について、図面を参照して説明する。
図３は、本発明における回路基板の一例を示す概略断面図である。パッドピッチが狭い構造を備えた回路基板２において、回路基板２のパッド１４上に高融点はんだ３１が形成されており、更に高融点はんだ３１の外に低融点はんだ３２が形成されている。ここで、高融点はんだとは、溶け始める温度（固相線）が１８３℃を越えるはんだであって、一般にＳｎかＰbをベースにＡｇ、Ｓｂ、Ｉｎ等が配合されているはんだを指す。また、低融点はんだとは、溶け始める温度（固相線）が１８３℃未満のはんだであって、Ｓｎ、Ｐｂ以外にＣｄ、Ｂｉ、Ｉｎ等が配合されているはんだを指す。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 3 is a schematic cross-sectional view showing an example of a circuit board in the present invention. In the circuit board 2 having a structure with a narrow pad pitch, a high melting point solder 31 is formed on the pad 14 of the circuit board 2, and a low melting point solder 32 is formed outside the high melting point solder 31. Here, the high melting point solder means a solder whose melting temperature (solidus) exceeds 183 ° C. and generally contains Ag, Sb, In or the like based on Sn or Pb. The low melting point solder is a solder whose melting temperature (solidus) is less than 183 ° C., and which contains Cd, Bi, In, etc. in addition to Sn and Pb.

図４は、本発明における回路基板の製造方法の一例を示す概略断面図である。パッドピッチが狭い構造を備えた回路基板２に、高融点はんだ３１をはんだペースト印刷もしくはボール搭載工法によって搭載し、その後、高融点はんだ３１が溶融する温度でリフローすることで回路基板のパッド１４に接合する（図４（ａ）参照）。次に、その高融点はんだ３１の表面を、表面が算術平均粗さＲａ２００〜６００ｎｍのコイニング治具４を用いてコイニングする。高融点はんだ３１の表面を金属製のコイニング治具４でコイニングすることにより治具の表面形状が転写され、高融点はんだ３１に算術平均粗さＲａ２００〜６００ｎｍの表面が形成される。算術平均粗さＲａを２００〜６００ｎｍとすることで、高融点はんだ３１と接合する低融点はんだ３２の界面の密着力が向上し、一次実装中の界面での剥離およびクラックを抑制することができる。次に、低融点はんだ３２をはんだペースト印刷もしくはボール搭載工法により搭載し、低融点はんだ３２の融点以上、高融点はんだ３１の融点未満で加熱し、接合する。こうして半導体チップ１と回路基板２がはんだによって接合されて形成された空間にアンダーフィル１６を充填する。このようにして半導体装置４３を得る（図４（ｃ）参照）。 FIG. 4 is a schematic cross-sectional view showing an example of a circuit board manufacturing method according to the present invention. The high melting point solder 31 is mounted on the circuit board 2 having a structure with a narrow pad pitch by solder paste printing or a ball mounting method, and then reflowed at a temperature at which the high melting point solder 31 melts, thereby being applied to the pads 14 of the circuit board. Join (see FIG. 4A). Next, the surface of the high melting point solder 31 is coined by using a coining jig 4 whose surface has an arithmetic average roughness Ra of 200 to 600 nm. By coining the surface of the high melting point solder 31 with a metal coining jig 4, the surface shape of the jig is transferred, and a surface having an arithmetic average roughness Ra of 200 to 600 nm is formed on the high melting point solder 31. By setting the arithmetic average roughness Ra to 200 to 600 nm, the adhesion at the interface between the low melting point solder 32 and the high melting point solder 31 is improved, and peeling and cracking at the interface during primary mounting can be suppressed. . Next, the low melting point solder 32 is mounted by solder paste printing or a ball mounting method, and is heated and bonded at a temperature equal to or higher than the melting point of the low melting point solder 32 and lower than the melting point of the high melting point solder 31. Thus, the underfill 16 is filled in the space formed by joining the semiconductor chip 1 and the circuit board 2 with the solder. In this way, the semiconductor device 43 is obtained (see FIG. 4C).

図５は、本発明における半導体装置の製造方法の一例を示した概略断面図である。パッド
１４上に高融点はんだ３１が形成されており、高融点はんだ３１の上に低融点はんだ３２が形成されているバンプが形成された回路基板４１と、低融点はんだ３２がパッド１４に形成された、はんだがパッド１２に形成された半導体チップ４２を目合せして接触させた状態で、リフロー装置を用いて低融点はんだ３２の融点以上、高融点はんだ３１の融点未満で加熱する（図５（ａ）参照）。このとき、バンプが形成された回路基板４１およびはんだがパッドに形成された半導体チップ４２の低融点はんだ３２は融点以上となり、溶融して結合する（図５（ｂ）参照）。一方、バンプが形成された回路基板４１の高融点はんだ３１は融点未満であるため溶融しない。そのため接合時に溶融するはんだは低融点はんだのみとなり、溶融するはんだの量を少なくすることができるので、隣接するバンプとのショートを防ぐことが出来る。このようにして半導体チップ１と回路基板２の間に隙間が形成され、この隙間にアンダーフィル１６をキャピラリーフロー工法で充填し、半導体装置４３を得る（図５（ｃ）参照）。このとき、充分なスタンドオフが得られ、はんだがパッドに形成された半導体チップ４２とバンプが形成された回路基板４１が一定間隔を確保できているため、問題なく充填することができる。 FIG. 5 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the present invention. A high-melting-point solder 31 is formed on the pad 14, a circuit board 41 on which bumps are formed, on which a low-melting-point solder 32 is formed on the high-melting-point solder 31, and the low-melting-point solder 32 is formed on the pad 14. Further, with the semiconductor chip 42 formed on the pad 12 aligned and in contact with the solder, the solder is heated at a temperature higher than the melting point of the low melting point solder 32 and lower than the melting point of the high melting point solder 31 using the reflow apparatus (FIG. 5). (See (a)). At this time, the circuit board 41 on which the bumps are formed and the low melting point solder 32 of the semiconductor chip 42 on which the solder is formed on the pads have a melting point or higher and melt and bond (see FIG. 5B). On the other hand, since the high melting point solder 31 of the circuit board 41 on which the bumps are formed is less than the melting point, it does not melt. Therefore, only the low melting point solder is melted at the time of joining, and the amount of solder to be melted can be reduced, so that a short circuit with an adjacent bump can be prevented. In this way, a gap is formed between the semiconductor chip 1 and the circuit board 2, and the gap is filled with the underfill 16 by a capillary flow method to obtain the semiconductor device 43 (see FIG. 5C). At this time, a sufficient standoff is obtained, and the semiconductor chip 42 on which the solder is formed on the pad and the circuit board 41 on which the bump is formed can secure a certain distance, and therefore can be filled without any problem.

図６は本発明における実装基板の製造方法の一例を示す概略断面図である。一次実装した半導体装置４３をマザーボードなどのようなプリント配線基板４４に実装する際に、高融点はんだ３１の融点以上に加熱し接合することで、高融点はんだ３１と低融点はんだ３２が溶融され、両者が混合して合金化することで、はんだ３３が形成される。アンダーフィル充填後にはんだを溶融させることで、低融点はんだと高融点はんだが溶融し、Ｓｎ以外の添加成分がバンプ全体に拡散し、両者の界面が明確でなくなることで、一体化した状態となり、半導体装置使用時における高融点はんだ３１と低融点はんだ３２の界面でのクラック発生を抑止することが出来る。また、図１に示すような一般的な半導体装置では、半導体チップ１と回路基板２の熱膨張係数の差に起因する応力が半導体チップのパッド１１とはんだバンプ３の界面および回路基板のパッド１４とはんだバンプ３の界面に集中するが、形状が図６（ｃ）のはんだ３３のように、２つの球体を合体させてできるだるま状の形状になることで、応力集中が分散され信頼性向上につながる。また、バンプがすべてはんだで構成されているため、充分な接合部での応力緩和を行うことができ、信頼性向上につながる。   FIG. 6 is a schematic cross-sectional view showing an example of a method for manufacturing a mounting board in the present invention. When the primary mounted semiconductor device 43 is mounted on a printed wiring board 44 such as a mother board or the like, the high melting point solder 31 and the low melting point solder 32 are melted by heating and bonding to the melting point of the high melting point solder 31 or higher. The solder 33 is formed by mixing and alloying both. By melting the solder after filling the underfill, the low melting point solder and the high melting point solder are melted, the additive components other than Sn are diffused throughout the bumps, and the interface between the two becomes unclear. It is possible to suppress the occurrence of cracks at the interface between the high melting point solder 31 and the low melting point solder 32 when the semiconductor device is used. Further, in a general semiconductor device as shown in FIG. 1, the stress caused by the difference in thermal expansion coefficient between the semiconductor chip 1 and the circuit board 2 causes the interface between the pad 11 of the semiconductor chip and the solder bump 3 and the pad 14 of the circuit board. Concentrates at the interface between the solder bumps 3 and the shape is like a solder 33 in FIG. 6 (c). By combining the two spheres into a daruma shape, stress concentration is dispersed and reliability is improved. Leads to. In addition, since all the bumps are made of solder, the stress can be sufficiently relaxed at the joined portion, leading to an improvement in reliability.

このようにして、狭ピッチバンプ構造を備えた半導体装置においてアンダーフィルの充填に充分なスタンドオフが得られ、信頼性の向上する構造の半導体装置とその製造方法および実装基板の製造方法を提供することが出来る。 In this manner, a semiconductor device having a narrow pitch bump structure, a standoff sufficient for filling an underfill is obtained, and a semiconductor device having a structure in which reliability is improved, a manufacturing method thereof, and a mounting substrate manufacturing method are provided. I can do it.

以下に実施例を示して本発明を詳しく説明する。
まず図４に記載の、本発明における回路基板の製造方法に則り回路基板を製造した。まず、パッドピッチ１００μｍ、パッド径７０μｍの構造を備えた回路基板２に、２種のはんだの内の高融点はんだ３１として、Ｓｎ−３．５Ａｇはんだペーストをスクリーン印刷により４０μｍ厚で搭載し、高融点はんだ３１がＳｎ−３．５Ａｇはんだが溶融する温度、本実施例では２３０℃でリフローすることでパッド１４に接合した。 Hereinafter, the present invention will be described in detail with reference to examples.
First, a circuit board was manufactured according to the circuit board manufacturing method of the present invention shown in FIG. First, Sn-3.5Ag solder paste is mounted on a circuit board 2 having a pad pitch of 100 μm and a pad diameter of 70 μm as a high melting point solder 31 of two types of solder by screen printing to a thickness of 40 μm. The melting point solder 31 was joined to the pad 14 by reflowing at a temperature at which the Sn-3.5Ag solder melts, that is, 230 ° C. in this example.

次に算術平均粗さＲａ２００〜６００ｎｍの表面粗さを持つ金属製の板であるコイニング治具４を用いてコイニングした。 Next, it coined using the coining jig | tool 4 which is a metal board with arithmetic mean roughness Ra200-600nm surface roughness.

次に、低融点はんだ３２としてＳｎ−５８Ｂｉはんだペーストをスクリーン印刷により２０μｍ厚で搭載し、低融点はんだ３２の液相温度である１４１℃以上、高融点はんだ３１の固相温度である２２１℃未満で加熱、接合する。本実施例では１８０℃で実施しバンプが形成された回路基板４１を得た。 Next, Sn-58Bi solder paste is mounted as a low melting point solder 32 by screen printing to a thickness of 20 μm, the liquid phase temperature of the low melting point solder 32 is 141 ° C. or higher, and the solid phase temperature of the high melting point solder 31 is less than 221 ° C. Heat and bond with. In this example, the circuit board 41 was obtained which was carried out at 180 ° C. and on which bumps were formed.

次に図５に記載の本発明における半導体装置の製造方法に則り、半導体装置を製造した。バンプが形成された回路基板４１と、低融点はんだ３２であるＳｎ−５８Ｂｉはんだが回路基板のパッド１４上に２０μｍ厚で形成されたはんだがパッドに形成された半導体チップ４２とを、リフロー装置を用いて低融点はんだ３２の融点以上、高融点はんだ３１の融点未満の温度である１８０℃で加熱、接合した。このとき、バンプが形成された回路基板４１およびはんだがパッドに形成された半導体チップ４２のそれぞれの低融点はんだ３２は融点以上となるため溶融し、接合した。一方、回路基板の高融点はんだ３１は融点未満であるため溶融は見られなかった。そのため接合時に溶融するはんだの体積を少なくすることができ、隣のバンプとの接触を防ぐことが出来た。このようにして半導体チップ１と回路基板２の間に形成された隙間に、アンダーフィルをキャピラリーフロー方式で充填し、半導体装置４３を得た。このとき、バンプ高さは７０μｍ程度を示しており、充分なスタンドオフが得られているため問題なく充填することができた。 Next, a semiconductor device was manufactured according to the method for manufacturing a semiconductor device according to the present invention shown in FIG. A circuit board 41 having bumps and a semiconductor chip 42 in which Sn-58Bi solder, which is a low melting point solder 32, is formed on the pads 14 of the circuit board in a thickness of 20 μm are formed on the pads. It was heated and joined at 180 ° C., which is a temperature higher than the melting point of the low melting point solder 32 and lower than the melting point of the high melting point solder 31. At this time, the low-melting-point solder 32 of the circuit board 41 on which the bumps were formed and the semiconductor chip 42 on which the solder was formed on the pads became higher than the melting point, and thus melted and joined. On the other hand, since the high melting point solder 31 of the circuit board was less than the melting point, no melting was observed. Therefore, the volume of solder that melts at the time of joining can be reduced, and contact with adjacent bumps can be prevented. In this way, the gap formed between the semiconductor chip 1 and the circuit board 2 was filled with underfill by a capillary flow method, and the semiconductor device 43 was obtained. At this time, the bump height was about 70 μm, and a sufficient standoff was obtained, so that it could be filled without any problem.

次に図６に記載の、本発明における半導体装置の製造方法に則り半導体装置を製造した。リフロー装置を用いて、半導体装置４３をプリント配線基板４４に実装する際に高融点はんだ３１の液相温度以上となる２３５℃で加熱、接合をおこなった。半導体装置４３とプリント配線基板４４の接合にはＳｎ−３．０Ａｇ−０．５Ｃｕはんだを用いた。 Next, a semiconductor device was manufactured according to the method for manufacturing a semiconductor device according to the present invention shown in FIG. When the semiconductor device 43 was mounted on the printed wiring board 44 using a reflow device, heating and bonding were performed at 235 ° C., which is equal to or higher than the liquid phase temperature of the high melting point solder 31. Sn-3.0Ag-0.5Cu solder was used for joining the semiconductor device 43 and the printed wiring board 44.

以上のようにして狭ピッチバンプ構造を備えた半導体装置においてアンダーフィルの充填に充分なスタンドオフが得られ、信頼性の向上する構造の半導体装置及びその製造方法を提供することが出来た。 As described above, a semiconductor device having a narrow pitch bump structure can provide a stand-off sufficient for filling an underfill, and can provide a semiconductor device having a structure with improved reliability and a method for manufacturing the same.

１…半導体チップ
２…回路基板
３…はんだバンプ
４…コイニング治具
１１…半導体チップのパッド
１２…バリアメタル層
１３…パッシベーション膜
１４…回路基板のパッド
１５…ソルダーレジスト膜
１６…アンダーフィル
２１…密着層
２２…銅（Ｃｕ）からなる柱状バンプ
２３…ぬれ防止膜
３１…高融点はんだ
３２…低融点はんだ
３３…はんだ
４１…バンプが形成された回路基板
４２…はんだがパッドに形成された半導体チップ
４３…半導体装置
４４…プリント配線基板 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Circuit board 3 ... Solder bump 4 ... Coining jig | tool 11 ... Semiconductor chip pad 12 ... Barrier metal layer 13 ... Passivation film 14 ... Circuit board pad 15 ... Solder resist film 16 ... Underfill 21 ... Adhesion Layer 22 ... Columnar bumps 23 made of copper (Cu) ... Wetting prevention film 31 ... High melting point solder 32 ... Low melting point solder 33 ... Solder 41 ... Circuit board 42 on which bumps are formed ... Semiconductor chip 43 on which solder is formed on pads ... Semiconductor device 44 ... Printed wiring board

Claims (5)

フリップチップ方式で半導体チップを実装するための回路基板であって、半導体チップとの電気的接続を行うためのパッドを備えてなり、前記半導体チップとの電気的接続を行う面のパッドには、はんだバンプを備えており、前記はんだバンプは異なる融点を持つ２層のはんだからなり、前記回路基板に近い部位である下層のはんだは高融点はんだからなり、前記半導体チップに近い部位である上層のはんだは低融点はんだからなることを特徴とする回路基板。   A circuit board for mounting a semiconductor chip by a flip chip method, comprising a pad for electrical connection with the semiconductor chip, and a pad on the surface for electrical connection with the semiconductor chip, Solder bumps are provided, the solder bumps are composed of two layers of solder having different melting points, the lower layer solder that is close to the circuit board is made of high melting point solder, and the upper layer that is close to the semiconductor chip A circuit board characterized in that the solder is made of low melting point solder. 請求項１に記載の回路基板の製造方法であって、
前記回路基板の半導体チップを実装する側のパッド上に高融点はんだを形成するはんだ形成工程と、
高融点はんだの上に低融点はんだを形成する工程と、を備えてなることを特徴とする回路基板の製造方法。 It is a manufacturing method of the circuit board according to claim 1, Comprising:
A solder forming step of forming a high melting point solder on a pad on the side of mounting the semiconductor chip of the circuit board;
Forming a low melting point solder on the high melting point solder, and a method of manufacturing a circuit board. 前記はんだ形成工程が、印刷工法またはボール搭載工法であることを特徴とする請求項２に記載の回路基板の製造方法。   The method for manufacturing a circuit board according to claim 2, wherein the solder forming step is a printing method or a ball mounting method. 請求項１に記載の回路基板に半導体チップを実装する半導体装置の製造方法であって、低融点はんだがパッドに形成された半導体チップを前記回路基板にフリップチップ方式で実装するに際して、低融点はんだの融点以上、且つ高融点はんだの融点より低い温度で接合する工程と、
前記半導体チップと前記回路基板によって形成された隙間にアンダーフィルを充填する工程と、を備えていることを特徴とする半導体装置の製造方法。 2. A method of manufacturing a semiconductor device, wherein a semiconductor chip is mounted on a circuit board according to claim 1, wherein the low melting point solder is mounted on the circuit board by a flip chip method. Bonding at a temperature equal to or higher than the melting point and lower than the melting point of the high melting point solder;
Filling a gap formed by the semiconductor chip and the circuit board with an underfill, and a method for manufacturing a semiconductor device. 請求項４に記載の半導体装置の製造方法を用いて製造した半導体装置をフリップチップ方式でプリント配線基板に実装する実装基板の製造方法であって、前記半導体装置をフリップチップ方式で前記プリント配線基板に実装するに際して、前記高融点はんだの融点以上に加熱することを特徴とする実装基板の製造方法。 A manufacturing method of a mounting board for mounting a semiconductor device manufactured by using the manufacturing method of a semiconductor device according to claim 4 on a printed wiring board by a flip-chip method, wherein the semiconductor device is flip-chip type by the printed wiring board. When mounting on a mounting board, the mounting board is heated to a melting point or higher of the high melting point solder.
JP2013133520A 2013-06-26 2013-06-26 Circuit board, method of manufacturing the same, method of manufacturing semiconductor device, and method of manufacturing mounting substrate Pending JP2015008254A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017092110A (en) * 2015-11-04 2017-05-25 ローム株式会社 Electronic component
JP2018200528A (en) * 2017-05-26 2018-12-20 凸版印刷株式会社 Ic module, ic card, and manufacturing method of them
CN109352112A (en) * 2018-11-06 2019-02-19 中国电子科技集团公司第三十八研究所 A kind of substrate precision welding two-component solder and its welding method
WO2023140075A1 (en) * 2022-01-24 2023-07-27 株式会社村田製作所 Elastic wiring substrate and method for manufacturing elastic wiring substrate
JP7390737B2 (en) 2021-12-07 2023-12-04 シーピー化成株式会社 packaging containers

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017092110A (en) * 2015-11-04 2017-05-25 ローム株式会社 Electronic component
JP2018200528A (en) * 2017-05-26 2018-12-20 凸版印刷株式会社 Ic module, ic card, and manufacturing method of them
CN109352112A (en) * 2018-11-06 2019-02-19 中国电子科技集团公司第三十八研究所 A kind of substrate precision welding two-component solder and its welding method
JP7390737B2 (en) 2021-12-07 2023-12-04 シーピー化成株式会社 packaging containers
WO2023140075A1 (en) * 2022-01-24 2023-07-27 株式会社村田製作所 Elastic wiring substrate and method for manufacturing elastic wiring substrate

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