CN103765579B - ***级封装器件的制造方法和***级封装器件 - Google Patents

***级封装器件的制造方法和***级封装器件 Download PDF

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CN103765579B
CN103765579B CN201280032667.9A CN201280032667A CN103765579B CN 103765579 B CN103765579 B CN 103765579B CN 201280032667 A CN201280032667 A CN 201280032667A CN 103765579 B CN103765579 B CN 103765579B
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tube core
resizing
package device
equations
core structure
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CN103765579A (zh
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海基·库斯玛
萨米·努尔米
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Murata Manufacturing Co Ltd
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VTI Technologies Oy
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0074—3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C19/00—Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
    • G01C19/56—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
    • G01C19/5783—Mountings or housings not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L19/00—Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
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    • G01L19/148—Details about the circuit board integration, e.g. integrated with the diaphragm surface or encapsulation
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    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P1/00—Details of instruments
    • G01P1/02—Housings
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    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P1/00—Details of instruments
    • G01P1/02—Housings
    • G01P1/026—Housings for speed measuring devices, e.g. pulse generator
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
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    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/0802—Details
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0228—Inertial sensors
    • B81B2201/0235—Accelerometers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0228—Inertial sensors
    • B81B2201/025—Inertial sensors not provided for in B81B2201/0235 - B81B2201/0242
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0257—Microphones or microspeakers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0264—Pressure sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/03—Microengines and actuators
    • B81B2201/036—Micropumps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/012—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being separate parts in the same package
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
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    • B81B2207/095—Feed-through, via through the lid
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
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Abstract

本发明涉及制造***级封装器件的方法以及***级封装器件。在该方法中，将至少一个具有预定尺寸的第一类管芯、至少一个具有预定尺寸的第二类管芯以及***级封装器件的至少一个其它部件包含到***级封装器件中。选择所述第一类管芯和所述第二类管芯中的至少一者以用于重定尺寸。向所选择的管芯的至少一侧添加材料，使得所添加的材料和所选择的管芯形成重定尺寸的管芯结构。在所述重定尺寸的管芯结构上形成连接层。对所述重定尺寸的管芯结构进行定尺寸，以允许将未被选择的管芯以及所述至少一个其它部件安装成经由所述连接层与所述重定尺寸的管芯结构接触。

Description

***级封装器件的制造方法和***级封装器件
技术领域
本发明涉及微电子学领域，更具体地涉及制造***级封装器件(system-in-package)的方法以及***级封装器件，该***级封装器件包括至少一个具有预定尺寸的第一类管芯(die)、至少一个具有预定尺寸的第二类管芯和***级封装器件的至少一个其它部件。
背景技术
在不同的部件制造领域中，受限的空间和不断增加的电路集成度从多个方面对电子产品的制造提出了要求。表面安装部件的尺寸一直在减小，由此促进了大量的部件被集成到印制线路板上。在微机电***(MEMS)领域中也正在发生类似的物理尺寸减小趋势。当对安装空间的要求的增加甚至快于部件尺寸的减小时，设计的进展已经引起非常高水平的集成并最终引起堆叠结构。
专利文献EP1951609说明了由彼此上下堆叠的MEMS管芯和集成电路(IC)形成的***级封装器件。图1示出了采用这种已知结构的***级封装器件，在该已知结构中，外部电气接触部设置在两个管芯中的较大的一者的表面上。当这两个管芯中的一个管芯显著地小于另一个管芯而由此在较大的管芯的表面上为接触区域留出空间时，这类***级封装器件是可应用的。为了实际地应用，较小的管芯必须非常薄，其厚度小于0.2mm。
专利文献US6405592B1给出了现有技术的另一个示例。同样，只有两个管芯的某些尺寸比例是允许的。
为了在商业上可行的应用，***级封装器件中包含的管芯具有不同的来源，并且它们被用于***级封装器件的制造之前它们的尺寸就早已预先确定。只要***级封装器件的构造简单，并且将要被封装的管芯在尺寸上合适地匹配使得任何必要的部件或布线(例如，外部电气连接件)可以被设置在较大的管芯上，那么，专利文献EP1951609的解决方案就是可应用的。然而，当管芯在尺寸上非常接近时，由于没有用于其它必要元件(例如，用于提供***级封装器件的必要输入/输出功能的接触构件)的空间，所以不能使用常规的方法。由于这种不匹配问题，许多在功能上有利的以及所期望的***级封装构造还没有在商业上变得可用。
发明内容
因而，本发明的目的在于提供用于制造***级封装器件的改进方法，以及使用该方法制造的***级封装器件。本发明的目的是通过由各个独立权利要求界定的方法和***级封装器件实现的。在从属权利要求中公开了本发明的优选实施例。
本发明的实施例包括一种制造***级封装器件的方法，所述方法包括：将至少一个具有预定尺寸的第一类管芯、至少一个具有预定尺寸的第二类管芯以及所述***级封装器件的至少一个其它部件包含到***级封装器件中；选择所述第一类管芯和所述第二类管芯中的至少一者以用于重定尺寸；向所选择的管芯的至少一侧添加材料，使得所添加的材料和所选择的管芯形成重定尺寸的管芯结构；在所述重定尺寸的管芯结构上形成连接层；对所述重定尺寸的管芯结构进行定尺寸，以允许将未被选择的管芯以及所述至少一个其它部件安装成经由所述连接层与所述重定尺寸的管芯结构接触。
在一个方面，该方法还包括：在第一原始晶片上制造出第一多个所述第一类管芯，所述第一类管芯在所述第一原始晶片上具有第一配额，一个所述第一类管芯的预定尺寸由所述第一配额确定；在第二原始晶片上制造出第二多个所述第二类管芯，所述第二类管芯在所述第二原始晶片上具有第二配额，一个所述第二类管芯的预定尺寸由所述第二配额确定。
在一个方面，所述***级封装器件的所述至少一个其它部件是用于所述***级封装器件的输入操作和输出操作的连接元件。
在一个方面，所述方法包括将两个以上的管芯包含到所述重定尺寸的管芯结构中。
在一个方面，所述方法包括将两个以上的管芯安装成经由所述连接层与所述重定尺寸的管芯结构接触。
在一个方面，所述方法包括将包含液体通道的管芯包含到所述***级封装器件的所述重定尺寸的管芯结构中。
在一个方面，所述方法包括将包含下面的元件中的至少一者的管芯包含到所述***级封装器件的所述重定尺寸的管芯结构中：光学元件、运动传感器、压力传感器、定时器件、滤波器器件、加速计、磁力计、微泵和扩音器。
在一个方面，所述方法包括通过穿过所述重定尺寸的管芯结构的密封剂贯穿通孔将所述连接元件连接到所述连接层。
在一个方面，所述第一类管芯或所述第二类管芯包括下面的元件中的至少一者：MEMS器件、集成半导体电路、ASIC电路、振荡器、光学器件、光电器件、磁性器件、换能器、传感器、滤波器、开关板、布线板、磁致伸缩元件、电致伸缩元件、压电器件。
本发明的实施例还包括一种***级封装器件，其包括：至少一个第一类管芯；至少一个第二类管芯；***级封装器件的至少一个其它部件；被包含到重定尺寸的管芯结构中的第一类管芯和第二类管芯中的至少一者，所述重定尺寸的管芯结构是通过将固体材料添加到所述第一类管芯和所述第二类管芯中的所述至少一者的至少一侧而形成的；连接层，其位于所述重定尺寸的管芯结构上；未被选择的管芯和所述至少一个其它部件，它们被安装成经由所述连接层与所述重定尺寸的管芯结构相接触。
在一个方面，所述第一类管芯的尺寸由所述第一类管芯在第一原始晶片中的第一配额确定；所述第二类管芯的尺寸由所述第二类管芯在第二原始晶片中的第二配额确定。
在一个方面，所述***级封装器件的所述至少一个其它部件是用于所述***级封装器件的输入操作和输出操作的连接元件。
在一个方面，所述重定尺寸的管芯结构包括两个以上的管芯。
在一个方面，两个以上的管芯经由所述连接层与所述重定尺寸的管芯结构接触。
在一个方面，所述重定尺寸的管芯结构包含用于提供液体通道的管芯。
在一个方面，所述***级封装器件包含具有下面元件中的至少一者的管芯：光学元件、运动传感器、压力传感器、定时器件、滤波器器件、加速计、磁力计、微泵和扩音器。
在一个方面，所述连接元件经由密封剂贯穿通孔连接到所述连接层，所述密封剂贯穿通孔穿过所述重定尺寸的管芯结构。
在一个方面，所述第一类管芯或所述第二类管芯包括下面元件中的至少一者：MEMS器件、集成半导体电路、ASIC电路、振荡器、光学器件、光电器件、磁性器件、换能器、传感器、滤波器、开关板、布线板、磁致伸缩元件、电致伸缩元件、压电器件。
附图说明
下面，将参照附图更详细地对实施例进行说明，其中
图1示出了现有技术的***级封装器件的构造；
图2示出了根据本发明实施例的***级封装器件；
图3-10示出了用于制造***级封装器件的方法的实施例的步骤；
图11示出了可利用提出的新方法来实现的新构造；
图12示出了可利用提出的新方法来实现的另一个新构造；
图13示出了延伸的管芯层包括两个管芯的另一实施例；
图14示出了连接的管芯层包括两个管芯的另一实施例；
图15示出了管芯包括用于液体的通道的另一实施例；
图16示出了管芯包括光学元件的另一实施例；
图17示出了***级封装器件的可能构造；
图18示出了***级封装器件另一种构造；
图19示出了***级封装器件另一种构造；以及
图20示出了***级封装器件另一种构造。
具体实施方式
下面的实施例均是示例性的。尽管说明书可能提及“某一”、“一个”或“一些”实施例，但是，这并不必然意味着每一个这类表述是针对相同的实施例而言，或者该特征仅适用于单个实施例。不同实施例的单个特征可以进行组合以提供另外的实施例。
下面，将利用根据本发明的各种实施例的器件构造的简单示例来说明本发明的特征。只对与实施例的说明有关的元件进行详细说明。方法和器件的各种实施可包括本领域技术人员已知的元件，且可以在本文中不予特别说明。
图2示出了利用根据本发明实施例的方法制造的***级封装器件的基本构造。在图2中，MEMS管芯用来代表具有预定尺寸的第一类管芯200，且IC管芯用来代表具有预定尺寸的第二类管芯202。这里，管芯的种类意味着在***级封装器件的生产过程之外将管芯设计和定尺寸成具有特定功能。基于此，该第一类管芯和第二类管芯不必在尺寸上匹配以便被封装到***级封装器件中。管芯的尺寸通常由它们在各自的原始晶片中的配额(allotment)来决定。从图2可以理解，第一类管芯200和第二类管芯202之间的初始尺寸差异非常小，以至于在堆叠之后，没有足够的用于***级封装器件的功能所需要的任何其它部件的空间。通常地，这意味着管芯的组合不能被包括在***级封装器件中，即使就它们的功能来说是兼容的，并且从生产成本的观点来说，它们的组合是高度期望的。
在本发明的实施例中，为了克服这种问题，在***级封装器件的生产过程中补充了如下阶段：通过向第一类管芯和第二类管芯中的至少一者的至少一侧固定地添加低成本材料204，来调整这些管芯之间的尺寸差异。典型地，低成本材料是塑封的塑性材料，其至少部分地使经选择以用于尺寸调整的管芯嵌入其中。该低成本的材料与经选择的管芯一起形成重定尺寸的管芯结构206，在管芯结构206上可以构建其它管芯以及***级封装器件的操作所需的任何必要的部件和布线。图2示出了MEMS管芯200被选择以用于尺寸调整的示例，但是，自然地，范围不限于任何特别的管芯种类的扩展。
图3至图10示出了制造***级封装器件的方法的实施例中的步骤。在该示例性的实施例中，重定尺寸的管芯结构是采用源自扇出型晶片级封装技术(FO-WLP，fan-outwafer-level packaging)处理形成的。FO-WLP是经开发并用于增加个体IC管芯的扇出的专门封装技术。发明人已经发现，可以将FO-WLP处理步骤中的一部分步骤运用到***级封装器件的生产过程中从而以经济的方式克服***级封装器件的完全不同类型的管芯之间的匹配问题。然而，值得注意的是，范围不限于FO-WLP的使用，也可以采用其它的用于将低成本材料固定到至少一个管芯的至少一侧的方法，而不偏离保护范围。
首先，生产出重定尺寸的管芯结构。为此，根据具体的配额，可以将第一晶片300切片成具有预定尺寸的管芯。在示例性的实施例中，第一类管芯产生自第一类型的晶片，这里指IC晶片。可以挑选这些第一类管芯302并将其放置在带304上，使得它们的电气接触区域靠着带(图3)。调整带上的第一类管芯之间的距离以提供重定尺寸的管芯结构的新尺寸，并且根据***级封装器件的设计调整新尺寸。更具体地，根据***级封装器件的至少一个其它管芯层(die layer)中的元件的尺寸，调整新尺寸。这里，术语“管芯层”是指***级封装器件构造中的包括至少一个管芯的层。第一类管芯的靠着带的表面是重定尺寸的管芯的一部分表面，并且提供用于与第二类管芯连接的电气接触区域。此后，在带304上，可将塑性材料306模塑在管芯302上以覆盖管芯并填满管芯之间的空间(图4)。形成了新的重构的基板或晶片，该基板或晶片包括多个重定尺寸的管芯结构。可将带移除，由此IC切片(IC-dice)的电气接触区域露出(图5)。
此后，可以用已知的方式提供用于将第一类管芯的电气接触区域与后续的***级封装层进行电气连接的连接构件。例如，连接构件可以被实施为重分布层，其包括导电材料310的层和绝缘材料308的层，导电材料层与绝缘材料层沉积和图案化在重构晶片的被移除了带的表面上。在重分布层中，在绝缘材料中形成的开口312可用于提供导电材料310与IC管芯302之间的电气连接(图6)。可以在重构晶片的相对侧对塑性材料进行减薄操作(图7)。该减薄操作可以一直延续直到露出管芯的背侧为止。
在本示例中，包括第二类管芯的管芯层是如下管芯层，基于该管芯层对重定尺寸的管芯结构的新尺寸进行调整。这里，该管芯层的制造可以从***级封装器件的接触元件的沉积开始，在这里，接触元件是导电材料310上的底部凸块金属化和焊料凸块(underbump metallization and solder bump)314(图8)。此后，可以安装将要被包括到相同的***级封装器件的第二类管芯316。假设第二类管芯316产生自第二晶片，其被独立地设计，且出于形成特定的***级封装器件的目的，因此不对其尺寸和配额进行特别的调整。因而，第二类管芯的尺寸是由初始的第二晶片的尺寸和配额预先确定的。第二类管芯可以是IC管芯或MEMS管芯，且它们可以包括诸如倒装芯片凸块(flip-chip bump)等电气连接件318。可以将第二类管芯316面向下地装配在重构的晶片上，使得通过电气连接件318和导电材料310使重定尺寸的管芯结构和第二类管芯电气连接。由于经过调整的新尺寸，第二类管芯和接触元件最佳地与重定尺寸的管芯结构匹配，并且形成了功能性封装器件。底部填充材料320(图10)可被施加到第二类管芯316和重构晶片之间的空间。最终，可以对重构晶片进行切片以形成大量的类似于图2示出的器件的***级封装器件。
借助于所提出的方法，通过被单独地预先定义了尺寸的管芯种类来高效地和经济地生产具有两个或更多的管芯的***级封装器件。这显著地增加了***级封装器件的设计上的多样性；更宽范围的管芯可以被组合到***级封装器件中，而不同的管芯层中的管芯的尺寸不匹配(size-mismatch)不会限制可能的构造的实施。设计上的通用性能够实现宽范围的经济可行的新的***构造。以简单的方式且没有实质上增加生产成本的方式实现了增加的通用性。已经发现，可以实现具有高的管芯面积比(die area ratio)(例如，对于IC/MEMS结构是0.5～2)的***级封装器件。在此范围内，高容量的管芯供应链变得可用。
图11和12示出了利用所提出的新方法实现的有利的***级封装构造。图11和图12中的附图标记对应于图3至图10中的相同元件。在图11的构造中，一个种类的具有预定义尺寸的管芯316已经被封装到具有另一种类的稍大的管芯302的***中，且在图12的构造中，同样的管芯316已经被封装到具有其它种类的较小的管芯302的***中。由于针对重定尺寸的管芯结构自由选择管芯以及调节将被封装的管芯之间的尺寸差异的可能性，在设计中，只需考虑管芯相对于特定的管芯层的功能适用性和经济适用性，在生产中，可以使用上述方法来实现管芯之间的适当的尺寸匹配。
此外，提出的解决方案提供一种方法以提高所生产的优质***级封装器件的产量。该方法提供将第一类管芯放置到带上的阶段(图3)。在此阶段之前，可以对第一类管芯进行预先测试。通过只将已经成功地预先测试的第一类管芯包括进后续的处理中，最终，只有已知的良好的管芯才会被包括到重构的晶片中。例如，在图4中，放置在带上的MEMS管芯302可以是预先测试的，从而才可以挑选出只有已知的良好的MEMS管芯。
增加的多样性不仅仅允许人们为***级封装器件的连续管芯层自由地选择不同尺寸的管芯。所提出的方法还能够在***级封装器件的层中包括两个或更多的平行的管芯。这在图13和图14中示出。图13和图14示出了包括通过重分布层404连接的第一管芯层400和第二管芯层402的***级封装器件。在图13的示例中，第一管芯层包括两个管芯，而第二管芯层包括一个管芯。为了第一管芯层400的管芯与第二管芯层402的管芯之间的合适的尺寸调整，第一管芯层400的管芯至少部分地被装入塑性封装块中以形成重定尺寸的管芯结构。结构的新尺寸被调整成使得可以构造第二管芯层402的管芯以及***级封装器件的任何必要布线。为此，第一管芯层400的管芯可以放置在带上以便重构晶片包含用于每个***级封装器件的两个管芯。对于本领域技术人员来说，清楚的是，重构晶片也可以包含多于两个的将被平行地包括在个体***级封装器件中的管芯，该管芯是通过塑性封装块的手段调整的。
在图14中，第一管芯层包括两个管芯，而第二管芯层包括一个管芯。可以通过将用于一个***级封装器件的两个或更多的第二类管芯面向下地在安装在重构晶片上来实现这种构造。
值得注意的是，利用常规的方法，关于这种多管芯的(multiple-die)管芯层构造的尺寸不匹配的问题是非常严重的，只有非常有限数量的具有预定义尺寸的功能性部件已经被组合到***级封装器件中。借助于所提出的方法，现在，可以以经济可行的方式设计并制造各种不同的功能性构造。
所提出的方法不仅仅消除了由具有不匹配表面尺寸的管芯引起的问题。对管芯层进行重定尺寸的可能性对于如下情况也是有价值的：由于将要被组合的管芯中的较小者的过大的厚度而妨碍了管芯的组合。如图12所示，这种小而厚的管芯可以被放置到第一管芯层(重构的晶片)中，而较大却较薄的管芯可以被放置到第二管芯层。这种问题在管芯包括需要空间并由此增加管芯的厚度的集成功能性元件的***级封装器件中是常见的。
图15示出了如下示例性的实施例，在该实施例中，管芯的尺寸被构造成将用于挥发性物质(液体、气体)的流体通道包括到***级封装器件中。这种用于流体的通道在例如压力传感器、扩音器、微泵和其它的液体和气体的处理和/或测量器件中是需要的。在这些***级封装器件中，由于许多经济可行的传感器的管芯的尺寸与所需的IC管芯的尺寸的不适当的匹配，所以在这些***级封装器件中遇到了非常严重的不匹配问题。例如，经济可行的压力传感器管芯406典型地比相应的IC管芯小得多且也比后者厚，通常在0.5-1mm的范围内。由于管芯之间表面区域的不同，可以采用本技术方案的情况。然而，在这种情况下，由于相对厚的传感器管芯应该位于较大的IC管芯的上方，所以IO凸块(IO-bump)的尺寸应该为0.5mm以上，这是不可实施的。图15示出了在未考虑所包括的管芯的尺寸的情况下在可对***级封装器件中的管芯的次序进行设计时如何避免这个问题。
图15的***级封装器件包括通过重分布层404连接的第一管芯层400和第二管芯层402。在重构晶片中，用于液体或气体的入口的通道406是形成在第一管芯层400中的开口，在本示例中，通道406位于管芯408的背侧。这里，术语“背侧”是指与电气接触所处的一侧相对的一侧。通道可以在将管芯装配在带上以制造重构晶片之前形成。在这种情况下，在模塑处理期间，必须通过保护材料层来保护开口，以避免模塑混合物进入开口。也可以在模塑处理之后在管芯408上制造开口406。管芯408也可以包括多个开口。可选地，图15的器件可以包括压力传感器、微泵、扩音器或任何其它的用于处理或测量液体或气体的性质的器件。新的方法展示了用于制造采用了流体输入到其中的***级封装器件的实用及经济可行的方式。
图16示出了另外的如下实施例，在该实施例中，***级封装器件包括光学元件500，该光学元件500例如是光源、探测器、滤波器、透镜、棱镜、偏光器、光栅、视窗或其它相似的光学或光电元件。在这个示例性的实施例中，光学元件被组合到重定尺寸的管芯结构中。光学元件还可以包括诸如分光计、自动聚焦的透镜或波束扫描器件、图像稳定器或显示器件等光机电元件(opto-electro-mechanical element)。光学元件可以在上表面和/或下表面上具有光路。根据实施例，光学元件可以具有可用于改变光路的电致伸缩特性和/或磁致伸缩特性。由于所提出的方法，可以以经济可行的方式实现图16示出的优化的管芯的组合。图16的实施例可被用来提供自动聚焦的透镜***、光学图像稳定器***、分光计、显示器件、光源或辐射探测器或它们合适的组合。
重定尺寸的管芯结构的尺寸确定不仅仅基于对上层管芯以及其它部件的尺寸的共同增加。图17至图20示出了***级封装器件的另外的可能构造。在这些实施例中，用作连接构件的IO凸块600没有直接安装在重定尺寸的管芯结构上的重分布层上，而是放置在重分布层下方。这些IO凸块通过密封剂贯穿通孔(through-encapsulant via)602和位于重定尺寸的管芯结构另一侧的另一连接层604连接到重分布层。该穿过密封剂的通孔可以延伸穿过重定尺寸的管芯结构。
前面的实施例中说明的管芯层还可以被组合在一个***级封装器件中以便形成功能的组合集。管芯种类的选择以及针对管芯的选择取决于***级封装器件的所需应用，并且对本应用领域的技术人员来说是熟悉的。例如，该功能集合可以提供用于加速度、角度范围、地球磁场和大气压力的的组合传感器。这些器件可用于导航***。
可选地，***级封装器件的实施例可以提供诸如加速计、角速率传感器或具有前述两种功能的组合传感器等惯性传感器。重构晶片上的管芯可以是用于这种传感器功能的MEMS管芯，而面向下地安装在重构晶片上的管芯可以是用于惯性传感器功能的IC管芯。
可选地，***级封装器件的实施例可以提供用于生成频率信号或时间信号的定时器件、用于电信号的频率滤波的滤波器器件或用于测量***或射频电路的可调电容器或开关。
可选地，***级封装器件的实施例可以提供具有单独的加速计的惯性传感器管芯、角速率传感器管芯以及接口电路管芯。其还可以提供具有用于倾斜补偿的加速计管芯、磁力计管芯和电路的罗盘仪。该器件还可以在多于两个管芯中提供具有加速计、角速率传感器、磁力计以及电路的功能的多自由度的传感器。
根据本发明的实施例的***级封装器件可以包括下面类型的管芯：MEMS器件、半导体集成电路、ASIC电路、振荡器、光学器件、光电器件、磁性器件、换能器、传感器、滤波器、开关板、布线板、磁致伸缩元件、电致伸缩元件、压电器件。
可以针对如下至少一个功能性来提供提供***级封装：
-功能性元件的形状在振动运动中的周期性变化，
-响应于控制信号，功能性元件的形状从第一形状状态到第二形状状态的静态变化，
-功能性元件的周期性位置改变，
-响应于控制信号，功能性元件从第一静态状态到第二状态的位置改变，
-用于电磁辐射的功能性元件在该电磁辐射的波长范围内的透射性和/或不透射性，
-用作电磁辐射的辐射源，
-用作机械波的换能器，
-用作能被开启和/或关闭的开关层，
-用作衰减层，
-用作开关板，
-用作布线板。
这里说明的***级封装器件的构造可以被包括到照相机、便携式电话、PDA、计算机、便携式器件、导航仪、天线电路、振荡器、谐振器、滤波器单位、存储器元件、无线电器件、激光器器件、光学控制器、指针、陀螺仪、加速度传感器、雷达元件、枪炮、导弹、飞机、汽车、舰船、摩托车、机械式发动机、电动式发动机、喷气式发动机、火箭发动机、伺服式传感器、气动式传感器、压力传感器、位置传感器、加热器件、通风器件、湿度传感器、称量计、工具、泵、建筑物以及机器人、静电器件、磁性器件、时钟、定时器、升降机、自动扶梯、起重机、速度计、角速率计或加速度传感器。上述清单并未穷尽，但是，目的是针对堆叠的和/或重定尺寸的结构为本领域的技术人员作出大致的介绍。
对本领域的技术人员来说，明显的是，由于本技术的优势，可以以多种方式实施发明的构思。本发明和本发明的实施例不限于上述的示例，而是可以在权利要求的范围内变化。

Claims (9)

1.一种制造***级封装器件的方法，所述方法包括：
将至少一个具有预定尺寸的第一类管芯、至少一个具有预定尺寸的第二类管芯以及用于所述***级封装器件的输入操作和输出操作的连接元件包含到所述***级封装器件中；其特征在于，
选择所述第一类管芯以用于重定尺寸，所选择的所述第一类管芯包含流体通道；
向所选择的所述第一类管芯的至少一侧添加材料，使得所添加的材料和所选择的所述第一类管芯形成重定尺寸的管芯结构；
在所述重定尺寸的管芯结构上形成连接层；
对所述重定尺寸的管芯结构进行定尺寸，以允许将未被选择的所述至少一个第二类管芯以及所述连接元件安装成经由所述连接层与所述重定尺寸的管芯结构接触，
通过从与所述连接层相对的表面移除所添加的材料来对所述重定尺寸的管芯结构的所添加的材料进行减薄，使得所选择的所述第一类管芯的背侧露出，所选择的所述第一类管芯的所述背侧包含所述流体通道。
2.根据权利要求1所述的方法，其中，所述方法还包括：
在第一原始晶片上制造出第一多个所述第一类管芯，所述第一类管芯在所述第一原始晶片上具有第一配额，一个所述第一类管芯的预定尺寸由所述第一配额确定；
在第二原始晶片上制造出第二多个所述第二类管芯，所述第二类管芯在所述第二原始晶片上具有第二配额，一个所述第二类管芯的预定尺寸由所述第二配额确定。
3.根据权利要求1或2所述的方法，其中，所述方法包括：
将包含下面的元件中的至少一者的所述第一类管芯包含到所述***级封装器件的所述重定尺寸的管芯结构中：压力传感器、滤波器器件、微泵和扩音器。
4.根据权利要求1所述的方法，其中，所述方法包括：
通过穿过所述重定尺寸的管芯结构的密封剂贯穿通孔将所述连接元件连接到所述连接层。
5.根据权利要求1或2所述的方法，其中，所述第一类管芯或所述第二类管芯包括下面的元件中的至少一者：MEMS器件、集成半导体电路、ASIC电路、振荡器、光学器件、光电器件、磁性器件、换能器、传感器、滤波器、开关板、布线板、磁致伸缩元件、电致伸缩元件、压电器件。
6.一种***级封装器件，其包括：
至少一个第一类管芯；
至少一个第二类管芯；
用于所述***级封装器件的输入操作和输出操作的连接元件；
连接层；
至少一个所述第一类管芯被包含到重定尺寸的管芯结构中，所述重定尺寸的管芯结构是通过将固体材料添加到所述第一类管芯的至少一侧而形成的；
所述重定尺寸的管芯结构包括第一表面和第二表面，其中所述第二表面与所述第一表面相对；
所述连接层位于所述重定尺寸的管芯结构的所述第一表面上；
所述重定尺寸的管芯结构的所述第二表面被减薄，使得所述第一类管芯的背侧露出，所述第一类管芯的露出的所述背侧包含流体通道；
所述第二类管芯和所述连接元件被安装成经由所述连接层与所述重定尺寸的管芯结构相接触。
7.根据权利要求6所述的***级封装器件，其中，所述***级封装器件包含具有下面元件中的至少一者的管芯：压力传感器、滤波器器件、微泵和扩音器。
8.根据权利要求6所述的***级封装器件，其中，所述连接元件经由密封剂贯穿通孔连接到所述连接层，所述密封剂贯穿通孔穿过所述重定尺寸的管芯结构。
9.根据权利要求6-8中任一项所述的***级封装器件，其中，所述第一类管芯或所述第二类管芯包括下面元件中的至少一者：MEMS器件、集成半导体电路、ASIC电路、振荡器、光学器件、光电器件、磁性器件、换能器、传感器、滤波器、开关板、布线板、磁致伸缩元件、电致伸缩元件、压电器件。
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