JP2014239164A - 半導体装置、表示デバイスモジュール、及び、表示デバイスモジュールの製造方法 - Google Patents
半導体装置、表示デバイスモジュール、及び、表示デバイスモジュールの製造方法 Download PDFInfo
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- JP2014239164A JP2014239164A JP2013121233A JP2013121233A JP2014239164A JP 2014239164 A JP2014239164 A JP 2014239164A JP 2013121233 A JP2013121233 A JP 2013121233A JP 2013121233 A JP2013121233 A JP 2013121233A JP 2014239164 A JP2014239164 A JP 2014239164A
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Abstract
Description
本実施形態では、異方性導電材料としてACF(anisotropic conductive film)51が用いられ、半導体チップ10がACF51を用いてガラス基板43に接合される。このとき、半導体チップ10のバンプ11は、ACF51に含まれる導電性粒子を介して配線46に電気的に接続される。同様に、バンプ12は、ACF51に含まれる導電性粒子を介して配線47に電気的に接続される。
10a、10b:長辺
10c、10d:短辺
11 :バンプ
11a :電源バンプ
11b :接地バンプ
12 :バンプ
13 :入力側バンプ配置領域
14 :出力側バンプ配置領域
15 :液晶駆動回路
16 :ロジック回路
17 :ソース駆動回路
18 :ゲート駆動回路
19 :周辺回路
20 :電源回路
21 :電源配線群
21A :電源配線群
21B :電源配線群
22 :VDD電源線
23 :GND電源線
24、25:バンプ
31 :層間絶縁膜
32 :表面保護層
32a、32b:開口
33 :UBM層
34 :導体層
35 :UBM層
36 :導体層
40 :表示デバイスモジュール
41 :LCDパネル
41a :表示部
42 :FPC
43 :ガラス基板
45 :スペーサ
46、47:配線
48 :配線
100 :半導体チップ
Claims (11)
- 互いに平行な一対の長辺と、前記一対の長辺に垂直な一対の短辺とを有する半導体チップと、
前記半導体チップの、前記一対の長辺のうちの一方に沿って設けられた第1パッド配置領域に配置された複数の第1バンプと、
前記半導体チップの、前記一対の長辺のうちの他方に沿って設けられた第2パッド配置領域に配置された複数の第2バンプと、
前記半導体チップの、前記第1パッド配置領域と前記第2パッド配置領域の間の領域に、前記一対の長辺に平行に延伸するように設けられた複数の第1電源線と、
前記半導体チップに集積化された複数の第3バンプ
とを具備し、
前記複数の第3バンプのそれぞれは、前記複数の第1電源線を短絡するように設けられている
半導体装置。 - 請求項1に記載の半導体装置であって、
更に、
前記第1パッド配置領域と前記第2パッド配置領域の間の領域に、前記一対の長辺に平行に延伸するように設けられた複数の第2電源線と、
前記半導体チップに集積化された複数の第4バンプ
とを具備し、
前記複数の第1電源線は、電源電圧が供給される電源線であり、
前記複数の第2電源線は、接地電位を有している電源線であり、
前記複数の第4バンプのそれぞれは、前記複数の第2電源線を短絡するように設けられている
半導体装置。 - 請求項2に記載の半導体装置であって、
前記複数の第1電源線と前記複数の第2電源線とは、前記一対の短辺の方向に交互に並んで配置された
半導体装置。 - 請求項3に記載の半導体装置であって、
前記複数の第3バンプのそれぞれは、前記複数の第2電源線の上方において前記複数の第2電源線を交差するように設けられ、
前記複数の第4バンプのそれぞれは、前記複数の第1電源線の上方において前記複数の第1電源線を交差するように設けられた
半導体装置。 - 請求項2乃至4のいずれかに記載の半導体装置であって、
前記第1バンプ、前記第2バンプ、前記第3バンプ、及び、前記第4バンプは、同一の高さを有している
半導体装置。 - 表示パネルと、
前記表示パネルのガラス基板に接合された半導体装置
とを具備し、
前記半導体装置は、
互いに平行な一対の長辺と、前記一対の長辺に垂直な一対の短辺とを有する半導体チップと、
前記半導体チップの、前記一対の長辺のうちの一方に沿って設けられた第1パッド配置領域に配置された複数の第1バンプと、
前記半導体チップの、前記一対の長辺のうちの他方に沿って設けられた第2パッド配置領域に配置された複数の第2バンプと、
前記半導体チップの、前記第1パッド配置領域と前記第2パッド配置領域の間の領域に、前記一対の長辺に平行に延伸するように設けられた複数の第1電源線と、
前記半導体チップに集積化された複数の第3バンプ
とを備え、
前記半導体チップが、前記複数の第1バンプ、前記複数の第2バンプ、及び、前記複数の第3バンプが、前記ガラス基板に対向するように前記ガラス基板に接合され、
前記第1バンプは、前記ガラス基板の上に形成された第1配線に接合され、
前記第2バンプは、前記ガラス基板の上に形成された第2配線に接合され、
前記複数の第3バンプのそれぞれは、前記複数の第1電源線を短絡するように設けられている
表示デバイスモジュール。 - 請求項6に記載の表示デバイスモジュールであって、
前記半導体チップと前記ガラス基板とが、主として、導電性粒子と前記導電性粒子が分散された接着剤とで構成される異方性導電材料を用いて接合されている
表示デバイスモジュール。 - 請求項7に記載の表示デバイスモジュールであって、
前記半導体チップの厚さが200μm以下であり、
前記一対の短辺の長さが1mm以上である
表示デバイスモジュール。 - 表示パネルのガラス基板に半導体装置を接合する工程を具備し、
前記半導体装置は、
互いに平行な一対の長辺と、前記一対の長辺に垂直な一対の短辺とを有する半導体チップと、
前記半導体チップの、前記一対の長辺のうちの一方に沿って設けられた第1パッド配置領域に配置された複数の第1バンプと、
前記半導体チップの、前記一対の長辺のうちの他方に沿って設けられた第2パッド配置領域に配置された複数の第2バンプと、
前記半導体チップの、前記第1パッド配置領域と前記第2パッド配置領域の間の領域に、前記一対の長辺に平行に延伸するように設けられた複数の第1電源線と、
前記半導体チップに集積化された複数の第3バンプ
とを具備し、
前記複数の第3バンプのそれぞれは、前記複数の第1電源線を短絡するように設けられ、
前記半導体装置は、前記複数の第1バンプ、前記複数の第2バンプ、及び、前記複数の第3バンプが、前記ガラス基板に対向するように前記ガラス基板に接合され、
前記接合する工程において、前記第1バンプは、前記ガラス基板の上に形成された第1配線に接合され、前記第2バンプは、前記ガラス基板の上に形成された第2配線に接合される
表示デバイスモジュールの製造方法。 - 請求項9に記載の表示デバイスモジュールの製造方法であって、
前記接合する工程において、前記半導体チップと前記ガラス基板とが、主として導電性粒子と前記導電性粒子が分散された接着剤とで構成される異方性導電材料を用いて接合される
表示デバイスモジュールの製造方法。 - 請求項10に記載の表示デバイスモジュールであって、
前記半導体チップの厚さが200μm以下であり、
前記一対の短辺の長さが1mm以上である
表示デバイスモジュールの製造方法。
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