JP2014011454A - ダイオード回路を通じて相互接続されるドレインおよび分離構造体を有する半導体デバイスおよびドライバ回路ならびにその製造方法 - Google Patents
ダイオード回路を通じて相互接続されるドレインおよび分離構造体を有する半導体デバイスおよびドライバ回路ならびにその製造方法 Download PDFInfo
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Abstract
【解決手段】半導体基板210と、基板上面212の下の埋め込み層220と、基板上面と埋め込み層との間のシンカ領域222であって、シンカ領域および埋め込み層によって分離構造体が形成される、シンカ領域と、半導体基板において、分離構造体によって収容される該半導体基板の部分内に位置するアクティブデバイスであって、アクティブデバイスはドレイン領域236を備える。
【選択図】図2
Description
下記の詳細な説明は単なる例示に過ぎず、実施形態またはさまざまな実施形態の適用および使用を限定することは意図されていない。さらに、上記技術分野もしくは背景技術または下記の詳細な説明において提示される、いかなる表示または暗示された理論によっても束縛されることは意図されていない。
Claims (22)
- 半導体デバイスであって、
第1の導電型および基板上面を有する半導体基板と、
前記基板上面の下の埋め込み層であって、該埋め込み層は前記第1の導電型と異なる第2の導電型を有する、前記埋め込み層と、
前記基板上面と前記埋め込み層との間のシンカ領域であって、該シンカ領域は前記第2の導電型を有し、該シンカ領域および前記埋め込み層によって分離構造体が形成される、シンカ領域と、
前記半導体基板において、前記分離構造体によって収容される該半導体基板の部分内に位置するアクティブデバイスであって、該アクティブデバイスは前記第2の導電型のドレイン領域を含む、前記アクティブデバイスと、
前記分離構造体と前記ドレイン領域との間に接続されるダイオード回路とを備える、半導体デバイス。 - 前記ダイオード回路は、
分離領域と結合されるショットキーコンタクトから形成されるショットキーダイオードを備える、請求項1に記載の半導体デバイス。 - 前記ダイオード回路は、
前記ショットキーダイオードに直列な抵抗ネットワークをさらに備える、請求項2に記載の半導体デバイス。 - 前記ダイオード回路は、
前記ショットキーダイオードに並列な抵抗ネットワークをさらに備える、請求項2に記載の半導体デバイス。 - 前記ダイオード回路は、
前記ショットキーダイオードに直列な抵抗ネットワークと、
前記ショットキーダイオードに並列な抵抗ネットワークとをさらに備える、請求項2に記載の半導体デバイス。 - 前記シンカ領域内に延びるとともに部分的に該シンカ領域をまたぐ、前記第1の導電型のさらなる領域をさらに備え、前記ダイオード回路は、前記ショットキーダイオードと、前記さらなる領域と前記シンカ領域との間に形成されるPN接合ダイオードとを含む、請求項2に記載の半導体デバイス。
- 前記シンカ領域内に延びるとともに部分的に該シンカ領域の内壁において該シンカ領域をまたぐ前記第1の導電型の第1のさらなる領域と、
前記シンカ領域内に延びるとともに部分的に該シンカ領域の外壁において該シンカ領域をまたぐ前記第1の導電型の第2のさらなる領域とをさらに備え、前記シンカ領域の一部分が、前記基板上面において前記第1のさらなる領域と前記第2のさらなる領域との間に存在し、前記ダイオード回路は前記ショットキーダイオードと、前記第1のさらなる領域と前記シンカ領域との間に形成される第1のPN接合ダイオードと、前記第2のさらなる領域と前記シンカ領域との間に形成される第2のPN接合ダイオードとを含む、請求項2に記載の半導体デバイス。 - 前記シンカ領域は、前記アクティブ領域を実質的に取り囲むリングとして形成され、前記ショットキーコンタクトは、前記リングの第1の部分に位置付けられ、前記デバイスは、
1つまたは複数の追加のショットキーコンタクトであって、前記第1の部分から、および互いから空間的に分離される、前記リングの複数の部分に位置付けられる前記追加のショットキーコンタクトと、
前記シンカ領域の上面において前記基板上面から前記シンカ領域内へ延びる前記第1の導電型の複数のさらなる領域とをさらに備え、前記複数のさらなる領域は前記ショットキーコンタクトとの間に散在される、前記リングの他の部分に位置付けられる、請求項2に記載の半導体デバイス。 - 前記シンカ領域内に延びる前記第1の導電型のさらなる領域をさらに備え、前記ダイオード回路は、前記さらなる領域と前記シンカ領域との間に形成されるPN接合ダイオードを含む、請求項1に記載の半導体デバイス。
- 前記ダイオード回路は、前記ドレイン領域と前記シンカ領域との間に相互接続される多結晶シリコンダイオードを含む、請求項1に記載の半導体デバイス。
- 前記アクティブデバイスは、
前記アクティブ領域の中央部分における第2の導電型のドリフト領域であって、前記基板上面から前記半導体基板内へ延びる、前記ドリフト領域と、
前記基板上面から前記ドリフト領域内へ延びる前記ドレイン領域と、
前記ドリフト領域と前記分離構造体との間において前記基板上面から前記半導体基板内へ延びる前記第1の導電型のボディ領域と、
前記基板上面から前記ボディ領域内へ延びる前記第2の導電型のソース領域と
前記ボディ領域における前記第1の導電型のボディコンタクト領域であって、前記ソース領域と前記分離構造体との間で前記基板上面から前記半導体基板内へ延びる前記ボディコンタクト領域を含む、請求項1に記載の半導体デバイス。 - ドライバ回路であって、
第1の導電型および基板上面を有する半導体基板に形成される第1の横方向拡散金属酸化膜半導体電界効果トランジスタ(LDMOSFET)であって、該第1のLDMOSFETは、
前記基板上面の下の埋め込み層であって、該埋め込み層は前記第1の導電型と異なる第2の導電型を有する、前記埋め込み層と、
前記基板上面と前記埋め込み層との間のシンカ領域であって、該シンカ領域は前記第2の導電型を有し、該シンカ領域および前記埋め込み層によって分離構造体が形成される、シンカ領域と、
前記半導体基板において、前記分離構造体によって収容される該半導体基板の部分内に位置するアクティブデバイスであって、該アクティブデバイスは前記第2の導電型のドレイン領域を備える、アクティブデバイスと、
前記分離構造体と前記ドレイン領域との間に接続されるダイオード回路とを備える、ドライバ回路。 - 前記ダイオード回路は、
分離領域と結合されるショットキーコンタクトから形成されるショットキーダイオードを備える、請求項12に記載のドライバ回路。 - 前記シンカ領域内に延びる前記第1の導電型のさらなる領域をさらに備え、前記ダイオード回路は、前記さらなる領域と前記シンカ領域との間に形成されるPN接合ダイオードを含む、請求項12に記載のドライバ回路。
- 前記ダイオード回路は、前記ドレイン領域と前記シンカ領域との間に相互接続される多結晶シリコンダイオードを含む、請求項12に記載のドライバ回路。
- 前記ダイオード回路は、
ダイオードと、
前記ダイオードに直列な抵抗ネットワークとを備える、請求項12に記載のドライバ回路。 - 前記ダイオード回路は、
ダイオードと、
前記ダイオードに並列な抵抗ネットワークとを備える、請求項12に記載のドライバ回路。 - 前記ダイオード回路は、
ダイオードと、
前記ダイオードに直列な抵抗ネットワークと、
前記ダイオードに並列な抵抗ネットワークとを備える、請求項12に記載のドライバ回路。 - 半導体デバイスを形成するための方法であって、
第1の導電型を有する半導体基板の基板上面の下に埋め込み層を形成する埋め込み層形成工程であって、該埋め込み層は前記第1の導電型と異なる第2の導電型を有する、前記工程と、
前記基板上面と前記埋め込み層との間にシンカ領域を形成するシンカ領域形成工程であって、該シンカ領域は前記第2の導電型を有し、該シンカ領域および前記埋め込み層によって分離構造体が形成される、前記工程と、
前記半導体基板において、前記分離構造体によって収容される該半導体基板の部分内に位置するアクティブデバイスを形成するアクティブデバイス形成工程であって、該アクティブデバイスは前記第2の導電型のドレイン領域を備える、前記工程と、
前記分離構造体と前記ドレイン領域との間に接続されるダイオード回路を形成するダイオード回路形成工程とを含む、方法。 - 前記ダイオード回路形成工程は、
前記分離領域と結合されるショットキーコンタクトを形成する工程を含む、請求項19に記載の方法。 - 前記ダイオード回路形成工程は、
前記シンカ領域内に延びる前記第1の導電型のさらなる領域を形成する工程を含み、前記ダイオード回路は、前記さらなる領域と前記シンカ領域との間に形成されるPN接合ダイオードを含む、請求項19に記載の方法。 - 前記ダイオード回路形成工程は、
前記ドレイン領域と前記シンカ領域との間に多結晶シリコンダイオードを形成するとともに相互接続する工程を含む、請求項19に記載の方法。
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