JP2012151457A - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP2012151457A JP2012151457A JP2011278588A JP2011278588A JP2012151457A JP 2012151457 A JP2012151457 A JP 2012151457A JP 2011278588 A JP2011278588 A JP 2011278588A JP 2011278588 A JP2011278588 A JP 2011278588A JP 2012151457 A JP2012151457 A JP 2012151457A
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- oxide semiconductor
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Abstract
【解決手段】非晶質領域である一対の第2の酸化物半導体領域と、一対の第2の酸化物半導体領域に挟まれた第1の酸化物半導体領域と、を有する酸化物半導体膜と、ゲート絶縁膜と、ゲート絶縁膜を介して第1の酸化物半導体領域上に設けられるゲート電極と、を有する半導体装置において、第2の酸化物半導体領域には、水素または希ガスのいずれかの元素が添加されている。
【選択図】図1
Description
本実施の形態では、図1及び図2を用いて、イオン添加されていない第1の酸化物半導体領域からなるチャネル領域を有するトップゲート構造のトランジスタにおいて、チャネル領域と同一層に設けられるイオン添加された第2の酸化物半導体領域でソース領域及びドレイン領域を構成した例を説明する。
次に、図1に示したトランジスタの作製方法について、図2を用いて説明する。
本実施の形態では、実施の形態1で示したトランジスタと異なるトランジスタの例について図3及び図4を用いて説明する。
次に、図3に示したトランジスタの作製方法について、図4を用いて説明する。
本実施の形態では、実施の形態1及び実施の形態2で示したトランジスタと異なるトランジスタの例について図5及び図6を用いて説明する。
次に、図5に示したトランジスタの作製方法について、図6を用いて説明する。
本実施の形態では、図7を用いて、イオン添加した酸化物半導体を用いた抵抗素子について説明する。
本実施の形態では、CAAC−OS膜である酸化物半導体膜の形成方法について、実施の形態1乃至実施の形態4で用いた以外の方法について、以下に説明する。
本実施の形態では、実施の形態1乃至実施の形態3に示した酸化物半導体膜を用いたトランジスタの電気特性への影響について、バンド図を用いて説明する。
図10(A)に半導体装置を構成する記憶素子(以下、メモリセルとも記す)の回路図の一例を示す。メモリセルは、酸化物半導体以外の材料をチャネル形成領域に用いたトランジスタ1160と酸化物半導体をチャネル形成領域に用いたトランジスタ1162によって構成される。
本実施の形態では、容量素子を有するメモリセルの回路図の一例を示す。図12(A)に示すメモリセル1170は、第1の配線SL、第2の配線BL、第3の配線S1、第4の配線S2と、第5の配線WLと、トランジスタ1171(第1のトランジスタ)と、トランジスタ1172(第2のトランジスタ)と、容量素子1173とから構成されている。トランジスタ1171は、酸化物半導体以外の材料をチャネル形成領域に用いており、トランジスタ1172はチャネル形成領域に酸化物半導体を用いている。
本実施の形態では、先の実施の形態に示すトランジスタを用いた半導体装置の例について、図13を参照して説明する。
酸化物半導体をチャネル形成領域に用いたトランジスタを少なくとも一部に用いてCPU(Central Processing Unit)を構成することができる。
102 下地絶縁膜
112 ゲート絶縁膜
114 ゲート電極
116 配線
122 酸化物半導体領域
124 層間絶縁膜
126 酸化物半導体領域
130 コンタクトホール
140 酸化物半導体膜
150 イオン
151 トランジスタ
152 トランジスタ
153 トランジスタ
190 酸化物半導体膜
212 ゲート絶縁膜
214 ゲート電極
216 ドレイン電極
222 酸化物半導体領域
224 層間絶縁膜
226 酸化物半導体領域
240 酸化物半導体膜
290 酸化物半導体膜
312 ゲート絶縁膜
314 ゲート電極
316 ドレイン電極
319 絶縁膜
322 酸化物半導体領域
324 層間絶縁膜
326 酸化物半導体領域
340 酸化物半導体膜
390 酸化物半導体膜
401 酸化物半導体膜
403 導電膜
410 抵抗素子
420 抵抗素子
421 酸化物半導体膜
423 導電膜
425 絶縁膜
1100 メモリセル
1110 メモリセルアレイ
1111 配線駆動回路
1112 回路
1113 配線駆動回路
1120 メモリセルアレイ
1130 メモリセル
1131 トランジスタ
1132 容量素子
1140 メモリセルアレイ
1141 スイッチング素子
1142 記憶素子
1143 記憶素子群
1150 メモリセル
1151 トランジスタ
1152 トランジスタ
1153 トランジスタ
1154 トランジスタ
1155 トランジスタ
1156 トランジスタ
1160 トランジスタ
1161 トランジスタ
1162 トランジスタ
1163 トランジスタ
1164 トランジスタ
1170 メモリセル
1171 トランジスタ
1172 トランジスタ
1173 容量素子
1180 メモリセル
1181 トランジスタ
1182 トランジスタ
1183 容量素子
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
Claims (14)
- 基板と、
前記基板上の、第1の酸化物半導体領域と前記第1の酸化物半導体領域を挟む一対の第2の酸化物半導体領域と、を有する酸化物半導体膜と、
前記酸化物半導体膜と接するゲート絶縁膜と、
前記ゲート絶縁膜を介して前記第1の酸化物半導体領域と重畳して設けられるゲート電極と、を有し、
前記第2の酸化物半導体領域は非晶質領域であり、
前記第1の酸化物半導体領域は非単結晶であり、かつc軸配向の結晶領域を有することを特徴とする半導体装置。 - 請求項1において、
前記酸化物半導体膜は、前記ゲート電極と前記基板との間に設けられ、
一対の前記第2の酸化物半導体領域に電気的に接続するソース電極及びドレイン電極と、を有し、
前記ソース電極及び前記ドレイン電極は、前記酸化物半導体膜と前記基板との間に設けられており、
前記ゲート電極と、前記ソース電極及び前記ドレイン電極は重畳していないことを特徴とする半導体装置。 - 請求項1において、
前記ゲート電極は、前記基板と前記酸化物半導体膜との間に設けられており、
一対の前記第2の酸化物半導体領域に電気的に接続するソース電極及びドレイン電極と、
前記第1の酸化物半導体領域と接し、且つ前記酸化物半導体膜及び前記ゲート絶縁膜を介して、前記ゲート電極と重畳する絶縁膜と、を有し、
前記酸化物半導体膜は、前記ソース電極及び前記ドレイン電極と、前記ゲート絶縁膜と、の間に設けられていることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第2の酸化物半導体領域に、希ガス元素から選ばれた、少なくとも一種以上の元素が、5×1018atoms/cm3以上1×1022atoms/cm3以下含まれていることを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記第2の酸化物半導体領域に、水素が5×1018atoms/cm3以上1×1022atoms/cm3以下含まれていることを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一において、
一対の前記第2の酸化物半導体領域はトランジスタのソース領域及びドレイン領域であり、前記第1の酸化物半導体領域は前記トランジスタのチャネル領域であることを特徴とする半導体装置。 - 請求項1乃至請求項6のいずれか一において、
前記第1の酸化物半導体領域及び前記第2の酸化物半導体領域は、In、Ga、Sn及びZnから選ばれた二種以上の元素を含むことを特徴とする半導体装置。 - 絶縁表面上に酸化物半導体膜を形成し、
加熱処理を行って、前記酸化物半導体膜を非単結晶であり、かつc軸配向の結晶領域を有する結晶構造とし、
前記加熱処理を行った酸化物半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極をマスクとして、前記加熱処理を行った酸化物半導体膜にイオンを添加することで、一対の第2の酸化物半導体領域を形成し、
前記第2の酸化物半導体領域は、非晶質領域であることを特徴とする半導体装置の作製方法。 - 絶縁表面上にソース電極及びドレイン電極を形成し、
前記ソース電極及び前記ドレイン電極上に酸化物半導体膜を形成し、
加熱処理を行って、前記酸化物半導体膜を非単結晶であり、かつc軸配向の結晶領域を有する結晶構造とし、
前記加熱処理を行った酸化物半導体膜上にゲート絶縁膜を形成し
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極をマスクとして、前記加熱処理を行った酸化物半導体膜にイオンを添加することで、一対の第2の酸化物半導体領域を形成し、
前記第2の酸化物半導体領域は、非晶質領域であり、
前記ゲート電極と、前記ソース電極及び前記ドレイン電極は重畳しないことを特徴とする半導体装置の作製方法。 - 絶縁表面上にゲート電極を形成し、
前記ゲート電極上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上に酸化物半導体膜を形成し、
加熱処理を行って、前記酸化物半導体膜を非単結晶であり、かつc軸配向の結晶領域を有する結晶構造とし、
前記加熱処理を行った酸化物半導体膜上に第1の絶縁膜を形成し、
前記第1の絶縁膜を加工して、前記ゲート電極と重畳する第2の絶縁膜を形成し、
前記第2の絶縁膜をマスクとして、前記加熱処理を行った酸化物半導体膜にイオンを添加することで、一対の第2の酸化物半導体領域を形成し、
前記第2の酸化物半導体領域は、非晶質領域であり、
平面形状において、前記ゲート電極の端部の内側に前記第2の絶縁膜の端部が位置することを特徴とする半導体装置の作製方法。 - 請求項8または請求項9において、
前記イオンは、希ガス元素から選ばれた、少なくとも一種以上の元素からなることを特徴とする半導体装置の作製方法。 - 請求項8乃至請求項10のいずれか一において、
前記イオンは、水素からなることを特徴とする半導体装置の作製方法。 - 請求項8乃至請求項12のいずれか一において、
前記第2の酸化物半導体領域はトランジスタのソース領域及びドレイン領域であり、前記第1の酸化物半導体領域は前記トランジスタのチャネル領域であることを特徴とする半導体装置の作製方法。 - 請求項8乃至請求項13のいずれか一において、
前記酸化物半導体膜は、In、Ga、Sn及びZnから選ばれた二種以上の元素を含
むことを特徴とする半導体装置の作製方法。
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