JP2012146749A - Pretreatment method in direct drawing process of organic film pattern onto semiconductor substrate - Google Patents
Pretreatment method in direct drawing process of organic film pattern onto semiconductor substrate Download PDFInfo
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本発明は、相互に異なる材料からなる複数の膜パターンを備える半導体基板表面に、さらに有機膜パターンを直接描画法により形成する膜形成プロセスの前処理方法に関する。 The present invention relates to a pretreatment method of a film forming process in which an organic film pattern is further formed by a direct drawing method on a semiconductor substrate surface having a plurality of film patterns made of different materials.
半導体デバイスを製造するプロセスにおいて、半導体基板表面に選択的な半導体領域の形成、酸化膜パターンの形成、電極膜配線やその上に被覆する有機膜パターンなどを形成する際には、フォトリソグラフィ技術を繰り返し用いる必要がある。フォトリソグラフィ技術により前述のようなパターンを形成するためには、非常に高価なフォトリソグラフィ装置を必要とする。さらに、前述のパターン形成のためには、半導体基板表面に形成した膜上に感光性のレジストを塗布し、フォトマスクと光などを用いて、まずレジストにパターンを露光し現像しベーキングし、続いて、このレジストパターンをマスクにしてエッチングにより前記膜に目的のパターンを形成する。このような膜パターンの形成は前述の高価なフォトリソグラフィ装置とともに、使用するレジストも高価であって使用効率も悪く、ほとんど廃棄することになるので、製造コストが高いものになっていた。 In the process of manufacturing semiconductor devices, photolithographic technology is used when forming a selective semiconductor region on the surface of a semiconductor substrate, forming an oxide film pattern, forming an electrode film wiring, or an organic film pattern covering the electrode film. Must be used repeatedly. In order to form the above-described pattern by the photolithography technique, a very expensive photolithography apparatus is required. Furthermore, for the above-mentioned pattern formation, a photosensitive resist is applied on the film formed on the surface of the semiconductor substrate, and using a photomask and light, the pattern is first exposed, developed and baked, then Then, a desired pattern is formed on the film by etching using the resist pattern as a mask. The formation of such a film pattern, together with the expensive photolithography apparatus described above, is expensive because the resist used is also expensive and inefficient in use and is almost discarded.
そこで、なるべく、フォトリソグラフィ工程を少なくするために、フォトリソグラフィを使用せずに、液状の有機膜材料を直接パターン状に吹き付け塗布して目的のパターン膜を形成する、たとえばインクジェット法などを含むディスペンサー法による直接描画法でのパターン形成方法が開発されている（特許文献１、２、３）。これらの特許文献ではさらに、この直接描画法では、膜パターンに断線や短絡が生じないように形成するために、半導体基板は、予め液滴との接触角を３０度以下にして良好な濡れ性、親水性表面となるように前処理されていることが好ましいとあり、さらに具体的な表面前処理の方法として、酸素雰囲気中でプラズマ照射する方法が好ましいことも示唆されている。 Therefore, in order to reduce the photolithography process as much as possible, a dispenser including, for example, an ink jet method is used to form a desired pattern film by directly spraying and applying a liquid organic film material in a pattern without using photolithography. A pattern forming method based on a direct drawing method using a method has been developed (Patent Documents 1, 2, and 3). Further, in these patent documents, in this direct drawing method, in order to form a film pattern so as not to be disconnected or short-circuited, the semiconductor substrate has a good wettability with a contact angle with a droplet of 30 degrees or less in advance. It is suggested that the surface is preferably pretreated so as to have a hydrophilic surface, and it is also suggested that a plasma irradiation method in an oxygen atmosphere is preferable as a more specific surface pretreatment method.
しかしながら、半導体の製造プロセスではＳｉ（シリコン）、ＳｉＯ２（シリコン酸化物）、Ａｌ（アルミニウム）、Ａｌ−Ｓｉ（シリコンを含有するアルミニウム合金）、Ａｌ−Ｃｕ（銅を含有するアルミニウム合金）、Ｔｉ（チタン）、Ｎｉ（ニッケル）、Ａｕ（金）、ＳｉＮ（Ｓｉ３Ｎ４等のシリコン窒化物）などの２種類以上のそれぞれ異なる材料で構成されている複数のパターン膜を有する半導体基板表面上に、さらに、レジスト膜やパッシベーション膜としてのポリイミド膜等の有機膜を形成するプロセスを必要とすることがある。この場合、前記有機膜を直接描画法によりパターン膜を形成しようとすると、半導体基板表面にある複数の膜パターンがそれぞれ異なる材料で構成されていることに起因して、濡れ性にバラツキが生じ、その結果、描画性や有機膜との密着性に問題が発生することがある。このような課題についてまでは、前記特許文献１では言及されていない。 However, Si in the semiconductor manufacturing process (silicon), SiO 2 (silicon oxide), Al (aluminum), (aluminum alloy containing silicon) Al-Si, Al-Cu ( aluminum alloy containing copper), Ti On the surface of a semiconductor substrate having a plurality of pattern films made of two or more different materials such as (titanium), Ni (nickel), Au (gold), SiN (silicon nitride such as Si 3 N 4 ) In addition, a process for forming an organic film such as a resist film or a polyimide film as a passivation film may be required. In this case, when an attempt is made to form a pattern film by direct drawing on the organic film, a plurality of film patterns on the surface of the semiconductor substrate are composed of different materials, resulting in variations in wettability, As a result, a problem may occur in the drawability and the adhesion with the organic film. Such a problem is not mentioned in Patent Document 1.
本発明は以上述べた点に鑑みてなされたものであり、本発明の目的は、直接描画法によりレジストの膜パターンやパッシベーション用などの有機膜パターンを形成する際に発生し易い描画性や密着性の問題を防ぐことのできる半導体基板への有機膜パターンの直接描画プロセスにおける前処理方法を提供することにある。 The present invention has been made in view of the above points, and an object of the present invention is to provide a drawability and adhesion that are likely to occur when forming a resist film pattern or an organic film pattern for passivation by a direct drawing method. It is an object of the present invention to provide a pretreatment method in a direct drawing process of an organic film pattern on a semiconductor substrate, which can prevent the problem of sexuality.
前記課題を達成するために、本発明では、相互に異なる材料で構成された複数のパターン膜で覆われた半導体基板表面上に、前記複数のパターン膜上に跨って積層される有機膜パターンを直接描画法により形成する際に、前処理として前記半導体基板表面を、プラズマ生成ガスとして酸素と窒素を用いてアッシングし、続いて水素と窒素をプラズマ生成ガスとして用いてクリーニング処理を行う半導体基板への有機膜パターンの直接描画プロセスにおける前処理方法とする（請求項１）。前記相互に異なる材料がＳｉ、ＳｉＯ２、Ａｌ、ＡｌＳｉ、ＡｌＣｕ、Ｔｉ、Ａｕ、ＳｉＮから選ばれるいずれかであることが好ましい（請求項２）。前記有機膜がレジストまたはポリイミドであることも好ましい（請求項３）。また、前記プラズマ生成ガスの流量比、酸素／窒素が０．４乃至４０．０の範囲の値であることが望ましい（請求項４）。また、前記プラズマ生成ガスの流量比、水素／窒素が０．４乃至４０．０の範囲の値であることが好ましい（請求項５）。さらに前記相互に異なる材料で構成された複数のパターン膜で覆われた半導体基板の前記複数のパターン膜表面の純水によるそれぞれの接触角がいずれも４０度以下であることがより好ましい（請求項６）。 In order to achieve the above object, in the present invention, an organic film pattern laminated on a plurality of pattern films is formed on a semiconductor substrate surface covered with a plurality of pattern films made of different materials. When forming by the direct drawing method, the semiconductor substrate surface is subjected to ashing using oxygen and nitrogen as plasma generating gases as a pretreatment, and subsequently subjected to a cleaning process using hydrogen and nitrogen as plasma generating gases. This is a pretreatment method in the direct drawing process of the organic film pattern. It is preferable that the mutually different materials are any one selected from Si, SiO 2 , Al, AlSi, AlCu, Ti, Au, and SiN. It is also preferable that the organic film is a resist or a polyimide. Further, it is desirable that the flow rate ratio of the plasma generation gas and oxygen / nitrogen be in the range of 0.4 to 40.0. Further, it is preferable that the flow rate ratio of the plasma generation gas and the hydrogen / nitrogen are in the range of 0.4 to 40.0. Furthermore, it is more preferable that the contact angles of pure water on the surface of the plurality of pattern films of the semiconductor substrate covered with the plurality of pattern films made of different materials are 40 degrees or less. 6).
本発明によれば、直接描画法によりレジストの膜パターンやパッシベーション用などの有機膜パターンを形成する際に発生し易い描画性や密着性の問題を防ぐ半導体基板への有機膜パターンの直接描画プロセスにおける前処理方法を提供することができる。 According to the present invention, a direct drawing process of an organic film pattern on a semiconductor substrate that prevents the problems of drawing properties and adhesion that are likely to occur when forming an organic film pattern such as a resist film pattern or a passivation film by a direct drawing method. A pre-processing method can be provided.
以下、本発明の半導体基板への有機膜パターンの直接描画プロセスにおける前処理方法にかかる実施例について、図面を参照して詳細に説明する。本発明はその要旨を超えない限り、以下に説明する実施例の記載に限定されるものではない。 Hereinafter, embodiments according to a pretreatment method in a direct drawing process of an organic film pattern on a semiconductor substrate of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
半導体デバイスを製造するプロセスにおいて、半導体基板表面にレジストやポリイミド等の有機膜パターンを直接描画法で形成する場合、有機膜パターンの密着度を高めるためには、有機膜をスピンコーターなどで塗布形成する従来のプロセスに比べて、下地の半導体基板表面のクリーニングが特に重要になる。図１の半導体基板の平面図、断面図に示すように、半導体基板１の表面に既に形成されている種々のパターン膜のそれぞれ表面性状、たとえば清浄度や濡れ性を均一にしておく必要がある。しかし、半導体基板の表面に実際に形成されている、たとえばＳｉ、ＳｉＯ２、Ａｌ、Ａｌ−Ｓｉ、Ａｌ−Ｃｕ、Ｔｉ、Ｎｉ、Ａｕ、ＳｉＮ（Ｓｉ３Ｎ４等）等からなる２種類以上の互いに異なる材料でそれぞれ構成されている複数のパターン膜の表面には、その濡れ性に関してバラツキが認められる。このようなバラツキを有する前記複数のパターン膜の表面性状を均一にする方法として、以下説明するようなプラズマ処理が有効であることを見つけたことが、本発明を成すきっかけである。 In the process of manufacturing a semiconductor device, when an organic film pattern such as resist or polyimide is directly formed on the surface of a semiconductor substrate by a drawing method, the organic film is applied and formed with a spin coater or the like in order to increase the adhesion of the organic film pattern. As compared with the conventional process, cleaning of the surface of the underlying semiconductor substrate is particularly important. As shown in the plan view and the cross-sectional view of the semiconductor substrate in FIG. 1, it is necessary to make the surface properties, such as cleanliness and wettability, of the various pattern films already formed on the surface of the semiconductor substrate 1 uniform. . However, two or more kinds of Si, SiO 2 , Al, Al—Si, Al—Cu, Ti, Ni, Au, SiN (Si 3 N 4 etc.) etc. that are actually formed on the surface of the semiconductor substrate. Variations are observed in the wettability of the surfaces of the plurality of pattern films respectively made of different materials. The discovery of the effectiveness of plasma treatment as described below as a method for making the surface properties of the plurality of pattern films having such variations uniform is the trigger for the present invention.
プラズマ処理の特徴として、アッシングの工程とクリーニングの工程を連続して行えることにある。このような連続プロセスとすることにより、半導体基板上の前記複数のパターン膜表面の濡れ性のバラツキがパターン膜表面に残っている残渣物質の除去（アッシング）と清浄化工程（クリーニング）を別々に行なった場合よりも２０％〜３０％程度低減させることができる。 As a feature of the plasma processing, an ashing process and a cleaning process can be performed continuously. By adopting such a continuous process, the removal (ashing) and cleaning process (cleaning) of the residual substances remaining on the pattern film surface due to the variation in wettability of the plurality of pattern film surfaces on the semiconductor substrate are performed separately. It can be reduced by about 20% to 30% compared to the case where it is performed.
このプラズマ処理の工程フローを図２に示す。前記複数のパターン膜が形成された半導体基板をプラズマ装置内のチャンバーに設置し、チャンバー内を減圧して１０Ｐａ〜１００Ｐａ程度にする（ａ）。次に、プラズマ生成ガスである酸素と窒素を、酸素１００ｍｌ／分と窒素３０ｍｌ／分で３０秒間注入する（ｂ）。この注入ガス雰囲気で１２０秒間、暴露して半導体基板表面に付着している有機汚染物質を酸化によりアッシングし、ＣＯ２やＨ２Ｏなどをガスとして基板表面から除去する（ｃ）。プラズマに暴露させる時間は６０秒〜１８０秒の範囲から選ぶことができる。生成ガスとしての酸素と窒素の好ましい流量比、酸素／窒素は、基板表面の膜材料、膜の表面状態により、最小値が０．４であり、最大値が４０．０である範囲の中から選択する。より好ましい比の範囲は１．０以上２０．０以下、さらに好ましくは２．０以上１０．０以下である。本実施例１の場合は、酸素／窒素が１００（ｍｌ／分）／３０（ｍｌ／分）≒３．３である。その後、アッシングにより生じた生成物（ＣＯ２やＨ２Ｏ等）ガスをチャンバーから除去する（ｄ）。 The process flow of this plasma processing is shown in FIG. The semiconductor substrate on which the plurality of pattern films are formed is placed in a chamber in a plasma apparatus, and the pressure in the chamber is reduced to about 10 Pa to 100 Pa (a). Next, oxygen and nitrogen, which are plasma generation gases, are injected for 30 seconds at 100 ml / min of oxygen and 30 ml / min of nitrogen (b). Organic contaminants exposed to the surface of the semiconductor substrate by being exposed for 120 seconds in this implantation gas atmosphere are ashed by oxidation, and CO 2 and H 2 O are removed from the substrate surface as gases (c). The exposure time to the plasma can be selected from the range of 60 seconds to 180 seconds. The preferred flow rate ratio of oxygen and nitrogen as the product gas, oxygen / nitrogen is within the range where the minimum value is 0.4 and the maximum value is 40.0, depending on the film material of the substrate surface and the surface condition of the film. select. A more preferable range of the ratio is 1.0 or more and 20.0 or less, and further preferably 2.0 or more and 10.0 or less. In the case of Example 1, oxygen / nitrogen is 100 (ml / min) / 30 (ml / min) ≈3.3. Thereafter, the product gas (CO 2 , H 2 O, etc.) generated by ashing is removed from the chamber (d).
次に、プラズマ生成ガスである水素１００ｍｌ／分と窒素３０ｍｌ／分で３０秒間注入する（ｅ）。この注入ガス雰囲気で２４０秒間、半導体基板表面を暴露して、基板表面に付着している自然酸化膜や前述のアッシングにより形成された酸化膜などを還元して除去する（クリーニング、と呼ぶ）（ｆ）。プラズマに暴露させる時間は１２０秒〜３６０秒の範囲から選ぶことができる。この際の水素と窒素の好ましい流量比、水素／窒素は、基板表面の膜材料、膜の表面状態により、最小値が０．４であり、最大値が４０．０である範囲の中から選択する。より好ましい比の範囲は１．０以上２０．０以下、さらに好ましくは２．０以上１０．０以下である。本実施例１の場合は、水素／窒素が１００（ｍｌ／分）／３０（ｍｌ／分）≒３．３である。その後、ガス排気と窒素による置換を窒素４０ｍｌ／分で１０〜１５分間行い、クリーニングにより生じた生成物（Ｈ２Ｏ等）を除去して窒素と入れ替える（ｇ）。常圧（大気圧）に戻す（ｈ）。 Next, hydrogen is injected as a plasma generating gas at 100 ml / min and nitrogen at 30 ml / min for 30 seconds (e). The semiconductor substrate surface is exposed for 240 seconds in this implantation gas atmosphere, and the natural oxide film adhering to the substrate surface or the oxide film formed by the above-mentioned ashing is reduced and removed (referred to as cleaning) ( f). The exposure time to the plasma can be selected from the range of 120 seconds to 360 seconds. In this case, the preferred flow rate ratio of hydrogen and nitrogen, hydrogen / nitrogen, is selected from the range where the minimum value is 0.4 and the maximum value is 40.0 depending on the film material of the substrate surface and the surface condition of the film. To do. A more preferable range of the ratio is 1.0 or more and 20.0 or less, and further preferably 2.0 or more and 10.0 or less. In the case of Example 1, hydrogen / nitrogen is 100 (ml / min) / 30 (ml / min) ≈3.3. Thereafter, gas evacuation and replacement with nitrogen are performed at 40 ml / min for 10 to 15 minutes to remove products (H 2 O and the like) generated by cleaning and replace with nitrogen (g). Return to normal pressure (atmospheric pressure) (h).
図３は、半導体基板表面のパターン膜の種類と純水による接触角と関係を示す図である。パターンの種類は、鏡面仕上げの表面に膜を形成していないシリコン基板（以下、ベアＳｉと呼ぶ）において、Ｓｉを１％含有するＡｌ（Ａｌ−Ｓｉ）膜を表面に形成した基板と、同じく熱酸化により表面に酸化膜（ＳｉＯ２）を形成した基板と、ベアＳｉの３種類である。これらの基板について、前述の工程フローに従ってプラズマ処理を行い、処理後の基板表面にて純水による接触角の測定を行った。また、比較のために、プラズマ処理を行っていない上記３種類の基板についても、同じ測定を行った。このプラズマ処理フローにより、図３に示すように、基板表面の接触角が、プラズマ処理前の２８度〜７６度という大きいバラツキから、プラズマ処理後の３４度〜３８度と言うように小さいバラツキ範囲におさまるようになった。また、接触角も４０度に近い４０度以下の場合に濡れ性が向上し、半導体基板面内の異なる膜パターン表面の濡れ性のバラツキも無くなることが分かった。濡れ性が良くなった状態の表面に、レジストやポリイミド等の有機膜を描画すると、描画時の濡れ広がり方が均一になりラインの直線性が向上すると共に、有機膜の密着性も向上させることが可能となる。 FIG. 3 is a diagram showing the relationship between the type of pattern film on the surface of the semiconductor substrate and the contact angle with pure water. The type of pattern is the same as that of a substrate in which an Al (Al-Si) film containing 1% Si is formed on the surface of a silicon substrate (hereinafter referred to as bare Si) on which no mirror-finished film is formed. There are three types: a substrate on which an oxide film (SiO 2 ) is formed on the surface by thermal oxidation, and bare Si. These substrates were subjected to plasma treatment according to the above-described process flow, and the contact angle with pure water was measured on the treated substrate surface. For comparison, the same measurement was performed on the three types of substrates that were not subjected to plasma treatment. With this plasma processing flow, as shown in FIG. 3, the contact angle of the substrate surface is as small as 28 degrees to 76 degrees before the plasma processing and 34 degrees to 38 degrees after the plasma processing. I came to fit in. It was also found that when the contact angle is 40 degrees or less, which is close to 40 degrees, the wettability is improved, and there is no variation in wettability between different film pattern surfaces in the semiconductor substrate surface. When an organic film such as resist or polyimide is drawn on the surface with improved wettability, the wet spread at the time of drawing becomes uniform and the linearity of the line is improved, and the adhesion of the organic film is also improved. Is possible.
このように、本発明では、直接描画による有機膜パターン形成の前処理として、通常知られている酸素ガスプラズマを用いた親水性表面にするための前処理だけでなく、直前の処理として、非親水性処理と言われる水素プラズマ処理を前処理に取り入れると、密着性が意外にも向上することを見つけてなされたものである。 Thus, in the present invention, as a pretreatment for forming an organic film pattern by direct drawing, not only a pretreatment for forming a hydrophilic surface using oxygen gas plasma, which is generally known, When hydrogen plasma treatment, which is called hydrophilic treatment, is incorporated in the pretreatment, it has been found that adhesion is unexpectedly improved.
以上説明したように、実施例１に記載の発明によれば、半導体基板表面の濡れ性が均一になり、描画性が向上する。また、描画時の直線性が向上するため、直接描画法を用いた工法ではより微細化が可能になる。また、フォトリソグラフィ工程自体を必要としないので、高価なフォトリソグラフィ設備一式が不要になることと、フォトリソグラフィ工程でのウエット処理時に使用される高価なレジストを含む薬品を使用する必要がないので、コストダウンにつながる。さらに作業時間の短縮もできる。 As described above, according to the invention described in Example 1, the wettability of the surface of the semiconductor substrate becomes uniform, and the drawing property is improved. Further, since the linearity at the time of drawing is improved, the method using the direct drawing method can be further miniaturized. In addition, since the photolithography process itself is not required, a set of expensive photolithography equipment is not necessary, and it is not necessary to use chemicals including an expensive resist used during wet processing in the photolithography process. This leads to cost reduction. In addition, the work time can be shortened.
１ 半導体基板
２ 酸化膜
３ Ａｌ膜
４ ＳｉＮ膜
５ ポリイミド膜
Ａ−Ａ’ 切断線
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Oxide film 3 Al film 4 SiN film 5 Polyimide film AA 'Cutting line
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| JP2011002353A JP2012146749A (en) | 2011-01-07 | 2011-01-07 | Pretreatment method in direct drawing process of organic film pattern onto semiconductor substrate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016518275A (en) * | 2013-04-24 | 2016-06-23 | オセ−テクノロジーズ・ベー・ヴエーＯｃｅ’−Ｎｅｄｅｒｌａｎｄ Ｂｅｓｌｏｔｅｎ Ｖｅｎｎｏｏｔｓｈａｐ | Method and apparatus for surface pretreatment of ink receiving substrate, printing method, and printer |
| WO2017029961A1 (en) * | 2015-08-17 | 2017-02-23 | 株式会社 アルバック | Substrate processing method and substrate processing device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003084123A (en) * | 2001-06-29 | 2003-03-19 | Seiko Epson Corp | Color filter substrate, method for manufacturing color filter substrate, liquid crystal display device, electrooptical device, method for manufacturing electrooptical device and electronic apparatus |
| JP2003082133A (en) * | 2001-09-13 | 2003-03-19 | Toppan Printing Co Ltd | Method for surface treatment of plastic film |
| JP2003241676A (en) * | 1996-09-19 | 2003-08-29 | Seiko Epson Corp | Method of manufacturing display element and method of manufacturing substrate for display element |
| JP2006332036A (en) * | 2005-04-25 | 2006-12-07 | Showa Denko Kk | Method for manufacturing display device |
| JP2010050310A (en) * | 2008-08-22 | 2010-03-04 | Fujitsu Microelectronics Ltd | Method of manufacturing semiconductor device |
-
2011
- 2011-01-07 JP JP2011002353A patent/JP2012146749A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003241676A (en) * | 1996-09-19 | 2003-08-29 | Seiko Epson Corp | Method of manufacturing display element and method of manufacturing substrate for display element |
| JP2003084123A (en) * | 2001-06-29 | 2003-03-19 | Seiko Epson Corp | Color filter substrate, method for manufacturing color filter substrate, liquid crystal display device, electrooptical device, method for manufacturing electrooptical device and electronic apparatus |
| JP2003082133A (en) * | 2001-09-13 | 2003-03-19 | Toppan Printing Co Ltd | Method for surface treatment of plastic film |
| JP2006332036A (en) * | 2005-04-25 | 2006-12-07 | Showa Denko Kk | Method for manufacturing display device |
| JP2010050310A (en) * | 2008-08-22 | 2010-03-04 | Fujitsu Microelectronics Ltd | Method of manufacturing semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016518275A (en) * | 2013-04-24 | 2016-06-23 | オセ−テクノロジーズ・ベー・ヴエーＯｃｅ’−Ｎｅｄｅｒｌａｎｄ Ｂｅｓｌｏｔｅｎ Ｖｅｎｎｏｏｔｓｈａｐ | Method and apparatus for surface pretreatment of ink receiving substrate, printing method, and printer |
| WO2017029961A1 (en) * | 2015-08-17 | 2017-02-23 | 株式会社 アルバック | Substrate processing method and substrate processing device |
| CN107924833A (en) * | 2015-08-17 | 2018-04-17 | 株式会社爱发科 | Substrate processing method using same and substrate board treatment |
| JPWO2017029961A1 (en) * | 2015-08-17 | 2018-05-24 | 株式会社アルバック | Substrate processing method and substrate processing apparatus |
| CN107924833B (en) * | 2015-08-17 | 2021-11-09 | 株式会社爱发科 | Substrate processing method and substrate processing apparatus |
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