JP2012049575A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2012049575A JP2012049575A JP2011268663A JP2011268663A JP2012049575A JP 2012049575 A JP2012049575 A JP 2012049575A JP 2011268663 A JP2011268663 A JP 2011268663A JP 2011268663 A JP2011268663 A JP 2011268663A JP 2012049575 A JP2012049575 A JP 2012049575A
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- bonding material
- semiconductor element
- thickness
- die bonding
- die
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】 リードフレーム11と半導体素子12とを接合するダイボンディング材13の厚さを40μm以上、好ましくは70μm以上とする。または、半導体素子12の厚さを200μm以下とする。あるいは、ダイボンディング材13の厚さを40μm以上、好ましくは70μm以上とするとともに、半導体素子12の厚さを200μm以下とする。このようにダイボンディング材13を厚くするか、半導体素子12を薄くすることによって、半導体素子12やダイボンディング材13に発生する熱応力を抑制する。
【選択図】 図2
Description
ただし、A=(G/h)×((1/(E2×t2))+(1/(E1×t1)))
ここで、第1の物質1をリードフレーム、第2の物質2を半導体素子、接合材3をダイボンディング材とすると、上記式(1)より明らかなように、ダイボンディング材の厚さ(h)を大きくするか、半導体素子の厚さ(t2)を小さくするか、またはダイボンディング材を厚くし、かつ半導体素子を薄くすれば、ダイボンディング材によりリードフレームに半導体素子を接合した物体の温度による歪み(γ)が小さくなる。したがって、この物体に発生する熱応力が小さくなる。
12 半導体素子
13 ダイボンディング材
14 モールド樹脂
Claims (2)
- Agペーストを介してリードフレームに半導体素子を接合し、それをモールド樹脂中に封入した半導体装置であって、
前記Agペーストは、その厚さは70μm以上であり、前記半導体素子の厚さは200μm以下であることを特徴とする半導体装置。 - 前記半導体素子は、縦型構造のデバイスであることを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011268663A JP2012049575A (ja) | 2011-12-08 | 2011-12-08 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011268663A JP2012049575A (ja) | 2011-12-08 | 2011-12-08 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001151906A Division JP2002353378A (ja) | 2001-05-22 | 2001-05-22 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2012049575A true JP2012049575A (ja) | 2012-03-08 |
Family
ID=45904014
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011268663A Pending JP2012049575A (ja) | 2011-12-08 | 2011-12-08 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP2012049575A (ja) |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5487178A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Construction of bonding part between semiconductor pellet and electrode plate |
JPS60136231A (ja) * | 1983-12-24 | 1985-07-19 | Toshiba Corp | 半導体装置 |
JPH0341742A (ja) * | 1989-07-10 | 1991-02-22 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH0344040A (ja) * | 1989-07-12 | 1991-02-25 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH0670375A (ja) * | 1992-08-19 | 1994-03-11 | Furukawa Electric Co Ltd:The | 給電制御装置 |
JPH07245399A (ja) * | 1994-03-08 | 1995-09-19 | Rohm Co Ltd | 縦型半導体装置 |
JPH0823002A (ja) * | 1994-07-05 | 1996-01-23 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH08222585A (ja) * | 1995-02-14 | 1996-08-30 | Nec Corp | 半導体装置 |
JPH08288503A (ja) * | 1995-04-11 | 1996-11-01 | Rohm Co Ltd | プレーナ型高耐圧縦型素子を有する半導体装置およびその製造方法 |
JPH11150135A (ja) * | 1997-11-17 | 1999-06-02 | Nec Corp | 熱伝導性が良好な導電性ペースト及び電子部品 |
JPH11158448A (ja) * | 1997-11-28 | 1999-06-15 | Sony Corp | 導電性接着剤およびこれを用いた電子部品 |
JP2000012566A (ja) * | 1998-06-24 | 2000-01-14 | Nec Kansai Ltd | 半導体装置 |
JP2000294519A (ja) * | 1999-04-09 | 2000-10-20 | Oki Electric Ind Co Ltd | 半導体装置、半導体装置の製造方法、およびその実装方法 |
WO2001024261A1 (en) * | 1999-09-28 | 2001-04-05 | Microchip Technology Incorporated | Method for reducing die cracking in integrated circuits |
-
2011
- 2011-12-08 JP JP2011268663A patent/JP2012049575A/ja active Pending
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5487178A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Construction of bonding part between semiconductor pellet and electrode plate |
JPS60136231A (ja) * | 1983-12-24 | 1985-07-19 | Toshiba Corp | 半導体装置 |
JPH0341742A (ja) * | 1989-07-10 | 1991-02-22 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH0344040A (ja) * | 1989-07-12 | 1991-02-25 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH0670375A (ja) * | 1992-08-19 | 1994-03-11 | Furukawa Electric Co Ltd:The | 給電制御装置 |
JPH07245399A (ja) * | 1994-03-08 | 1995-09-19 | Rohm Co Ltd | 縦型半導体装置 |
JPH0823002A (ja) * | 1994-07-05 | 1996-01-23 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH08222585A (ja) * | 1995-02-14 | 1996-08-30 | Nec Corp | 半導体装置 |
JPH08288503A (ja) * | 1995-04-11 | 1996-11-01 | Rohm Co Ltd | プレーナ型高耐圧縦型素子を有する半導体装置およびその製造方法 |
JPH11150135A (ja) * | 1997-11-17 | 1999-06-02 | Nec Corp | 熱伝導性が良好な導電性ペースト及び電子部品 |
JPH11158448A (ja) * | 1997-11-28 | 1999-06-15 | Sony Corp | 導電性接着剤およびこれを用いた電子部品 |
JP2000012566A (ja) * | 1998-06-24 | 2000-01-14 | Nec Kansai Ltd | 半導体装置 |
JP2000294519A (ja) * | 1999-04-09 | 2000-10-20 | Oki Electric Ind Co Ltd | 半導体装置、半導体装置の製造方法、およびその実装方法 |
WO2001024261A1 (en) * | 1999-09-28 | 2001-04-05 | Microchip Technology Incorporated | Method for reducing die cracking in integrated circuits |
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