JP2012028674A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

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Publication number
JP2012028674A
JP2012028674A JP2010168079A JP2010168079A JP2012028674A JP 2012028674 A JP2012028674 A JP 2012028674A JP 2010168079 A JP2010168079 A JP 2010168079A JP 2010168079 A JP2010168079 A JP 2010168079A JP 2012028674 A JP2012028674 A JP 2012028674A
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Prior art keywords
buffer plate
semiconductor element
semiconductor device
linear expansion
expansion coefficient
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JP2010168079A
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Japanese (ja)
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JP5542567B2 (en
Inventor
Ko Sano
耕 佐野
Kenichi Hayashi
建一 林
Toshiaki Shinohara
利彰 篠原
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high peak temperature, which is highly reliable even if an amount of temperature variation increases.SOLUTION: A semiconductor device comprises a semiconductor element 3, a first impingement plate 7A with one face bonded to an electrode of the semiconductor element 3 via a bonding member 6a, a second impingement plate 7B with one face bonded to the other face of the first impingement plate 7A via a bonding member 6b, a wiring member 4 bonded to the other face of the second impingement plate 7B. The first impingement plate 7A has a linear expansion coefficient αwhich is between a linear expansion coefficient αof the semiconductor element 3 and a linear expansion coefficient αof the wiring member 4, and the difference between the linear expansion coefficient αand the linear expansion coefficient αof the semiconductor element 3 is smaller than a first predetermined value. The second impingement plate 7B has a linear expansion coefficient αwhich is between the linear expansion coefficient αof the first impingement plate 7A and the linear expansion coefficient αof the wiring member 4, and the difference between the linear expansion coefficient αand the linear coefficient αis smaller than a second predetermined value that is larger than the first predetermined value.

Description

本発明は、半導体装置に関し、特に、半導体素子上にワイヤ接合のための電極部材を配置した半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an electrode member for wire bonding is arranged on a semiconductor element and a method for manufacturing the same.

半導体装置の中でも電力用半導体装置は、鉄道車両、ハイブリッドカー、電気自動車等の車両、家電機器、産業用機械等において、比較的大きな電力を制御、整流するために利用されている。従って、電力用半導体装置に使用される半導体素子は４００Ｖ以上の耐電圧を確保しながら、１００Ａ／ｃｍ２を超える高い電流密度で通電することが求められる。そのため、近年はシリコン（Ｓｉ）に代わる半導体材料としてワイドバンドギャップ半導体材料である炭化珪素（ＳｉＣ）が注目されており、ＳｉＣからなる半導体素子は５００Ａ／ｃｍ２を超える電流密度での動作が可能である。また、ＳｉＣは１５０℃〜３００℃の高温状態でも安定動作が可能であり、高電流密度動作と高温動作の両立が可能な半導体材料として期待されている。 Among semiconductor devices, power semiconductor devices are used to control and rectify relatively large power in vehicles such as railway vehicles, hybrid cars, and electric vehicles, home appliances, and industrial machines. Therefore, a semiconductor element used in a power semiconductor device is required to be energized at a high current density exceeding 100 A / cm 2 while ensuring a withstand voltage of 400 V or higher. Therefore, in recent years, silicon carbide (SiC), which is a wide band gap semiconductor material, has attracted attention as a semiconductor material that replaces silicon (Si), and a semiconductor element made of SiC can operate at a current density exceeding 500 A / cm 2. It is. Further, SiC is capable of stable operation even at a high temperature of 150 ° C. to 300 ° C., and is expected as a semiconductor material capable of achieving both high current density operation and high temperature operation.

一方、電力用を含め半導体装置では、半導体素子の下面の電極面を絶縁基板上の回路パターンにはんだ接合し、上面の電極面にアルミニウムのワイヤを超音波接合して半導体素子の給電経路を形成することが一般的に行われてきた。しかし、アルミニウムの線膨張係数は２３〜２４ｐｐｍ／Ｋ程度であり、半導体素子として使用されるＳｉやＳｉＣなどの線膨張係数が３〜５ｐｐｍ／Ｋと較べて異なるので、オン（通電）、オフ（遮断）の繰り返しの熱応力によって、ワイヤ内部に亀裂が進展し、やがて破断に到ることが知られている。これは、パワーサイクル試験と呼ばれる断続的なパルス電流負荷を与えることで破断に対する耐久性を評価することが出来ることから、以降パワーサイクル寿命と呼ぶことにする。   On the other hand, in semiconductor devices including those for electric power, the lower electrode surface of the semiconductor element is solder-bonded to the circuit pattern on the insulating substrate, and an aluminum wire is ultrasonically bonded to the upper electrode surface to form a power supply path for the semiconductor element. It has generally been done. However, since the linear expansion coefficient of aluminum is about 23 to 24 ppm / K and the linear expansion coefficient of Si or SiC used as a semiconductor element is different from 3 to 5 ppm / K, it is on (energized), off ( It is known that cracks develop inside the wire due to repeated thermal stress (breaking) and eventually break. This is hereinafter referred to as a power cycle life because durability against breakage can be evaluated by applying an intermittent pulse current load called a power cycle test.

パワーサイクル寿命は、熱応力に起因した亀裂に関する現象であることから、半導体素子の温度変化量に大きく依存する。また、半導体素子の最高到達温度が高くなるとパワーサイクル寿命は短い傾向となる。上述したように、ワイドバンドギャップ半導体においては、高温での動作が期待されるため、Ｓｉデバイスと比較すると、高い最高到達温度と大きな温度変化量に耐えうる配線構造が必須となる。これは、たとえば従来のＳｉ半導体に対して最高到達温度を１２５℃、温度変化量を８０Ｋと設定して設けられた配線構造を、ワイドバンドギャップ半導体における動作条件である最高到達温度が１７５℃、温度変化量が１３０Ｋの条件で使用すると、パワーサイクル寿命が１／１０以下まで低下することになる。つまり、電力用半導体装置のような大電流を扱う半導体装置では、ワイドバンドギャップ半導体の機能を発揮できるような厳しい温度条件に対しては、従来のＳｉ半導体に対して用いられてきたアルミニウムワイヤの超音波接合のような配線構造では十分な寿命を得ることができなかった。   Since the power cycle life is a phenomenon related to cracks caused by thermal stress, it greatly depends on the temperature change amount of the semiconductor element. In addition, the power cycle life tends to be short as the maximum temperature of the semiconductor element increases. As described above, since a wide band gap semiconductor is expected to operate at a high temperature, a wiring structure that can withstand a high maximum temperature and a large amount of temperature change is essential as compared with a Si device. This is because, for example, a wiring structure provided with a maximum temperature of 125 ° C. and a temperature change of 80 K with respect to a conventional Si semiconductor has a maximum temperature of 175 ° C., which is an operating condition in a wide band gap semiconductor. When the temperature change amount is 130K, the power cycle life is reduced to 1/10 or less. In other words, in a semiconductor device that handles a large current such as a power semiconductor device, an aluminum wire that has been used for a conventional Si semiconductor can be used under severe temperature conditions that can function as a wide bandgap semiconductor. With a wiring structure such as ultrasonic bonding, a sufficient life could not be obtained.

そこで、ワイヤに代わって平板状のリード部材と半導体素子との接合部に半導体素子の線膨張係数に近い応力緩衝板を挿入し、熱サイクル時の接合部に生じる熱応力を緩和する半導体装置が提案されている（例えば、特許文献１または特許文献２参照。）。また、ワイヤを接合するための電極を弾性率の低い導電性樹脂を介して半導体素子上に配置し、半導体素子と電極間にかかる熱応力を緩和するようにしたパワー半導体モジュールが提案されている（例えば、特許文献３参照。）。   In view of this, a semiconductor device that relieves thermal stress generated at the joint during thermal cycling by inserting a stress buffer plate close to the linear expansion coefficient of the semiconductor element at the joint between the flat lead member and the semiconductor element instead of the wire. (For example, refer to Patent Document 1 or Patent Document 2). Further, a power semiconductor module has been proposed in which an electrode for bonding a wire is arranged on a semiconductor element via a conductive resin having a low elastic modulus so as to relieve thermal stress applied between the semiconductor element and the electrode. (For example, refer to Patent Document 3).

特開平１１−１６３０４５号公報（段落００３４、図２）Japanese Patent Laid-Open No. 11-163045 (paragraph 0034, FIG. 2) 特開２０００−３３２０６７号公報（段落０００７、００１２〜００１４、図１）JP 2000-332067 (paragraphs 0007, 0012 to 0014, FIG. 1) 特開平１１−１６３０４５号公報（段落００１８〜００１９、図１）Japanese Patent Laid-Open No. 11-163045 (paragraphs 0018 to 0019, FIG. 1)

しかしながら、緩衝部材の線膨張係数を半導体素子に近づければ、半導体素子と緩衝部材と接合部の繰り返し熱応力に対する寿命は長くなるが、緩衝部材とリード部材との熱応力を抑制することは困難となる。逆に、緩衝部材の線膨張係数をリード部材に近づけるとリード部材接合部の繰り返し熱応力寿命は長くなるが、半導体素子と緩衝部材との熱応力を抑制することは困難となる。つまり、パワーサイクル寿命を最適化するには、このトレードオフ関係から両者の寿命がほぼ等しくなる点を選ぶ必要がある。これはすなわち、パワーサイクル寿命が線膨張係数のトレードオフによって限界点を持っていることを意味している。このような状況にあっては、ワイドバンドギャップ半導体における高温動作で必要な、１０倍以上のパワーサイクル性能を得ることは不可能であった。また、弾性率の低い導電性樹脂を挿入する場合、樹脂は高温で劣化しやすいので信頼性が低下するとともに、金属部材と比較して抵抗が高いために電力ロスが発生して効率が低下するという問題があった。   However, if the linear expansion coefficient of the buffer member is close to that of the semiconductor element, the life against repeated thermal stresses of the semiconductor element, the buffer member, and the joint is increased, but it is difficult to suppress the thermal stress between the buffer member and the lead member. It becomes. Conversely, when the linear expansion coefficient of the buffer member is made closer to the lead member, the repeated thermal stress life of the lead member joint becomes longer, but it becomes difficult to suppress the thermal stress between the semiconductor element and the buffer member. In other words, in order to optimize the power cycle life, it is necessary to select a point at which the two lifespans are almost equal from this trade-off relationship. This means that the power cycle life has a limit point due to the linear expansion coefficient trade-off. Under such circumstances, it has been impossible to obtain a power cycle performance more than 10 times that is necessary for high-temperature operation in a wide band gap semiconductor. In addition, when a conductive resin having a low elastic modulus is inserted, the resin is easily deteriorated at a high temperature, so that the reliability is lowered, and since the resistance is higher than that of the metal member, a power loss is generated and the efficiency is lowered. There was a problem.

本発明は、上記のような課題を解決するためになされたもので、最高到達温度が高く、温度変化量が大きくなっても、信頼性の高い半導体装置を得ることを目的としている。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a highly reliable semiconductor device even when the maximum temperature reached is high and the temperature change amount is large.

本発明の半導体装置は、絶縁基板の回路面に一方の面が接合された半導体素子と、前記半導体素子の他方の面に形成された電極に、接合材を介して、一方の面が接合された第１の緩衝板と、前記第１の緩衝板の他方の面に、接合材を介して、一方の面が接合された第２の緩衝板と、前記第２の緩衝板の他方の面に接合された配線部材と、を備え、前記第１の緩衝板は、前記半導体素子の線膨張係数と前記配線部材の線膨張係数の間であって、前記半導体素子の線膨張係数との差が第１の所定値より小さい線膨張係数を有し、前記第２の緩衝板は、前記第１の緩衝板の線膨張係数と前記配線部材の線膨張係数の間であって、前記配線部材の線膨張係数との差が、前記第１の所定値より大きな第２の所定値より小さい線膨張係数を有する、ことを特徴とする。   In the semiconductor device of the present invention, one surface is bonded to the semiconductor element having one surface bonded to the circuit surface of the insulating substrate and the electrode formed on the other surface of the semiconductor element via a bonding material. A first buffer plate, a second buffer plate having one surface bonded to the other surface of the first buffer plate via a bonding material, and the other surface of the second buffer plate The first buffer plate is between the linear expansion coefficient of the semiconductor element and the linear expansion coefficient of the wiring member, and the difference between the linear expansion coefficient of the semiconductor element Has a linear expansion coefficient smaller than a first predetermined value, and the second buffer plate is between the linear expansion coefficient of the first buffer plate and the linear expansion coefficient of the wiring member, and the wiring member A difference in linear expansion coefficient between the first predetermined value and the second predetermined value is smaller than the second predetermined value. And butterflies.

本発明の半導体装置によれば、半導体素子と配線部材間に配置する２枚の応力緩衝板のうち、半導体素子側の応力緩衝板の線膨張係数は半導体素子の線膨張係数に応じて設定し、配線部材側の応力緩衝板の線膨張係数は、半導体素子の線膨張係数と独立して配線部材の線膨張係数に応じて設定するので、接合部にかかる熱応力を適切に緩和し、最高到達温度が高く、温度変化量が大きくなっても、信頼性の高い半導体装置を得ることができる。   According to the semiconductor device of the present invention, of the two stress buffer plates arranged between the semiconductor element and the wiring member, the linear expansion coefficient of the stress buffer plate on the semiconductor element side is set according to the linear expansion coefficient of the semiconductor element. The linear expansion coefficient of the stress buffer plate on the wiring member side is set according to the linear expansion coefficient of the wiring member independently of the linear expansion coefficient of the semiconductor element. Even when the ultimate temperature is high and the amount of temperature change is large, a highly reliable semiconductor device can be obtained.

本発明の実施の形態１にかかる電力用半導体装置および電極部材の構成を説明するための図である。It is a figure for demonstrating the structure of the power semiconductor device and electrode member concerning Embodiment 1 of this invention. 本発明の実施の形態２にかかる電力用半導体装置および電極部材の構成を説明するための図である。It is a figure for demonstrating the structure of the semiconductor device for electric power and electrode member concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる電力用半導体装置を製造する方法を説明するための部分断面図である。It is a fragmentary sectional view for demonstrating the method to manufacture the power semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態３にかかる電力用半導体装置および電極部材の構成を説明するための図である。It is a figure for demonstrating the structure of the semiconductor device for electric power and electrode member concerning Embodiment 3 of this invention. 本発明の実施の形態３にかかる電力用半導体装置における接合材の構成を説明するための断面図である。It is sectional drawing for demonstrating the structure of the joining material in the semiconductor device for electric power concerning Embodiment 3 of this invention.

実施の形態１．
図１は、本発明の実施の形態１にかかる電力用半導体装置を説明するためのもので、電力用半導体装置のうちの、絶縁基板の回路パターンに接合、つまり実装されるとともに、上面に応力緩衝機能を有する電極部材が接合された半導体素子と、電極部材を介して半導体素子と絶縁基板の他の回路パターン部分とを電気接続する１本のボンディングワイヤ部分を示しており、図１（ａ）は上面図、図１（ｂ）は図１（ａ）のＡ−Ａ線による断面図である。なお、２つの応力緩衝板を接合材を介して層状に張り合わされたものを電極部材と呼んでいるが、必ずしも電極部材単体として存在する必要はなく、半導体装置内で電極部材に相当する部分が構成されていればよい。また、表裏に回路パターンを有する絶縁性セラミックス板全体を絶縁基板と呼ぶことにする。 Embodiment 1 FIG.
FIG. 1 is a diagram for explaining a power semiconductor device according to a first embodiment of the present invention. In the power semiconductor device, the power semiconductor device is bonded to a circuit pattern of an insulating substrate, that is, mounted, and stress is applied to the upper surface. 1A shows a semiconductor element to which an electrode member having a buffer function is bonded, and one bonding wire portion that electrically connects the semiconductor element and another circuit pattern portion of the insulating substrate through the electrode member. ) Is a top view, and FIG. 1B is a cross-sectional view taken along line AA of FIG. Note that the two stress buffer plates laminated in layers through the bonding material are called electrode members. However, the electrode members do not necessarily exist as a single member, and the portion corresponding to the electrode member in the semiconductor device is not necessarily present. It only has to be configured. The whole insulating ceramic plate having circuit patterns on the front and back is called an insulating substrate.

電力用半導体装置１０は、図１に示すように、窒化アルミニウム、窒化ケイ素、アルミナなどのセラミックス材料からなる絶縁基板１の回路面１ｆ上に図示しないろう材などで接合された回路パターン２ａ、２ｂ（後述する２ｒも含め、まとめて２）が配置されている。回路パターンは銅、アルミニウムなどの導電性材料またはそれらを主成分とする合金材料からなる。さらに、回路パターン２の表面は、酸化防止やはんだ材料の濡れ性を考慮して、ニッケルなどのめっき被膜が形成されている。また、図示しないが絶縁基板１の回路面１ｆの反対側の面（図では回路パターン２ｒが形成されている面）には放熱板が形成されていても良い。   As shown in FIG. 1, the power semiconductor device 10 includes circuit patterns 2a and 2b bonded to a circuit surface 1f of an insulating substrate 1 made of a ceramic material such as aluminum nitride, silicon nitride, and alumina by a brazing material (not shown). (Collectively 2 including 2r described later) is arranged. The circuit pattern is made of a conductive material such as copper or aluminum or an alloy material containing them as a main component. Further, the surface of the circuit pattern 2 is formed with a plating film such as nickel in consideration of oxidation prevention and wettability of the solder material. Although not shown, a heat sink may be formed on the surface of the insulating substrate 1 opposite to the circuit surface 1f (the surface on which the circuit pattern 2r is formed in the drawing).

図１では、回路パターン２ａ上にダイボンド用はんだ５を介して半導体素子（チップ）３が接続されている。半導体素子３は、シリコンウエハを基材とした一般的な素子でも良いが、本発明においては炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）、またはダイヤモンドといったシリコンと較べてバンドギャップが広い、いわゆるワイドバンドギャップ半導体材料への適用を目的としており、特に炭化ケイ素を用いた半導体素子に適用される。デバイス種類としては、ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect-Transistor）のようなスイッチング素子、またはダイオードのような整流素子である。ＭＯＳＦＥＴの場合、半導体素子３の回路パターン２ａ側の面にはドレイン電極が形成されている。そして、ドレイン電極と反対側（図で上側）の面には、ゲート電極やソース電極が、領域を分けて形成されているが、本発明の実施の形態の特徴を分かりやすくするため、上側の面には、大電流が流れるソース電極に着目して説明する。なお、ドレイン電極の表面には、はんだ６ａとの接合を良好とするための複合金属膜が形成されている。ソース電極の表面にも、図示しない厚さ数μｍの薄いアルミニウム、銅などの電極膜やチタン、モリブデン、ニッケル、金などの薄膜層が形成されている。   In FIG. 1, a semiconductor element (chip) 3 is connected to a circuit pattern 2 a via a die bonding solder 5. The semiconductor element 3 may be a general element based on a silicon wafer. In the present invention, the semiconductor element 3 has a wider band gap than silicon such as silicon carbide (SiC), gallium nitride (GaN), or diamond. It is intended to be applied to a band gap semiconductor material, and is particularly applied to a semiconductor element using silicon carbide. Device types include switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field-Effect-Transistors), or rectifying elements such as diodes. In the case of MOSFET, a drain electrode is formed on the surface of the semiconductor element 3 on the circuit pattern 2a side. The gate electrode and the source electrode are formed on the surface opposite to the drain electrode (upper side in the figure), but the upper electrode is formed in order to make the characteristics of the embodiment of the present invention easier to understand. The surface will be described focusing on the source electrode through which a large current flows. Note that a composite metal film is formed on the surface of the drain electrode to improve the bonding with the solder 6a. On the surface of the source electrode, a thin electrode film such as aluminum and copper having a thickness of several μm and a thin film layer such as titanium, molybdenum, nickel and gold (not shown) are also formed.

そして、半導体素子３の上側の面には、接合材であるはんだ６ａを介して第１の緩衝板である応力緩衝板７Ａが接続されている。応力緩衝板７Ａは、ワイヤ等の配線部材よりも半導体素子３と線膨張係数が近い低熱膨張性の金属材料からなる。応力緩衝板７Ａの上（半導体素子３の反対側面）には、接合材であるはんだ６ｂを介して第２の緩衝板である応力緩衝板７Ｂが接続されている。そして、応力緩衝板７Ｂの上面には、配線部材であるアルミないし銅のワイヤ４またはリボンが超音波接合される。応力緩衝板７Ｂは半導体素子３よりもワイヤ４またはリボンに線膨張係数が近い金属材料からなる。つまり、半導体素子３は、線膨張係数が異なる２枚の応力緩衝板７Ａ、７Ｂが接合材によって接合されることによって構成された電極部材７を介してワイヤ４と接合されている。なお、図１では、説明を簡略化するため、１本のワイヤ４しか示していないが、ワイヤは通常、電流容量を確保するため、複数本を並べて配置する。また、図示していないが、ワイヤのループ形状の大きさを変えて、多数のワイヤを配置することも一般的に行われる。   A stress buffer plate 7A as a first buffer plate is connected to the upper surface of the semiconductor element 3 via a solder 6a as a bonding material. The stress buffer plate 7A is made of a low thermal expansion metal material having a linear expansion coefficient closer to that of the semiconductor element 3 than a wiring member such as a wire. A stress buffer plate 7B as a second buffer plate is connected to the stress buffer plate 7A (on the opposite side of the semiconductor element 3) via a solder 6b as a bonding material. An aluminum or copper wire 4 or ribbon as a wiring member is ultrasonically bonded to the upper surface of the stress buffer plate 7B. The stress buffer plate 7B is made of a metal material having a linear expansion coefficient closer to that of the wire 4 or ribbon than that of the semiconductor element 3. That is, the semiconductor element 3 is joined to the wire 4 via the electrode member 7 configured by joining two stress buffer plates 7A and 7B having different linear expansion coefficients by the joining material. In FIG. 1, only one wire 4 is shown for the sake of simplicity, but a plurality of wires are usually arranged side by side in order to ensure current capacity. Although not shown, it is also common to arrange a large number of wires by changing the size of the loop shape of the wires.

電極部材７を構成する応力緩衝板７Ａ、７Ｂのうち、ワイヤ４側に配置される第２の緩衝板である応力緩衝板７Ｂは、例えば、銅、アルミまたはそれらを含む合金材料、または低膨張係数材を含むクラッド材などからなる。また、半導体素子３側に配置される第１の緩衝板である応力緩衝板７Ａは、例えばモリブデン、ないしモリブデンを含有する合金またはクラッド材、及びインバー合金を含むクラッド材などからなる。なお、半導体素子３と応力緩衝板７Ａとを接合するはんだ６ａ、および応力緩衝板７Ａと応力緩衝板７Ｂとを接合するはんだ６ｂ（まとめて６）は、例えば銀を主成分とする焼結性フィラーやろう材といった、はんだに分類されない接合材であっても良い。基本的には、接合後の剛性や降伏応力が被接合材（半導体素子３、応力緩衝板７Ａ、７Ｂ）よりも低く、接合後も被接合材が元の機械特性（線膨張係数）を維持できるような一般的な導電性の接合材料であればよい。   Of the stress buffer plates 7A and 7B constituting the electrode member 7, the stress buffer plate 7B as the second buffer plate disposed on the wire 4 side is, for example, copper, aluminum, an alloy material containing them, or low expansion. It consists of a clad material including a coefficient material. The stress buffer plate 7A, which is the first buffer plate disposed on the semiconductor element 3 side, is made of, for example, molybdenum, an alloy or clad material containing molybdenum, and a clad material containing Invar alloy. Note that the solder 6a for joining the semiconductor element 3 and the stress buffer plate 7A and the solder 6b (collectively 6) for joining the stress buffer plate 7A and the stress buffer plate 7B are, for example, sinterability mainly composed of silver. Bonding materials not classified into solder, such as fillers and brazing materials, may be used. Basically, the rigidity and yield stress after bonding are lower than the material to be bonded (semiconductor element 3, stress buffer plates 7A and 7B), and the material to be bonded maintains the original mechanical characteristics (linear expansion coefficient) after bonding. Any general conductive bonding material can be used.

ここで、半導体素子３からワイヤ４にかけて層状に重なった各部材の線膨張係数を整理する。
半導体素子３の線膨張係数をαＣ、応力緩衝板７Ａの線膨張係数をαＢＡ、応力緩衝板７Ｂの線膨張係数をαＢＢ、ワイヤ４の線膨張係数をαＷとすると、各部材の線膨張係数が、式（１）に示すように、半導体素子３からワイヤ４にかけて順次大きくなるように応力緩衝板７Ａ、７Ｂの線膨張係数を調整している。
αＣ＜αＢＡ＜αＢＢ＜αＷ ・・・（１）
ただし、ここでは応力緩衝板によく用いられるインバー合金の線膨張係数の温度依存性を考慮して、常温である２０℃での線膨張係数を基準とする。 Here, the linear expansion coefficient of each member overlapped in layers from the semiconductor element 3 to the wire 4 is arranged.
When the linear expansion coefficient of the semiconductor element 3 is α C , the linear expansion coefficient of the stress buffer plate 7A is α BA , the linear expansion coefficient of the stress buffer plate 7B is α BB , and the linear expansion coefficient of the wire 4 is α W , As shown in Expression (1), the linear expansion coefficients of the stress buffer plates 7A and 7B are adjusted so that the linear expansion coefficient gradually increases from the semiconductor element 3 to the wire 4.
α C <α BA <α BB <α W (1)
However, in consideration of the temperature dependence of the linear expansion coefficient of Invar alloy often used for stress buffer plates, the linear expansion coefficient at 20 ° C., which is normal temperature, is used as a reference.

このような構成にした理由、およびさらに詳細な設定について述べる。
電極部材７の接合に用いるはんだ６内では、パワーサイクルにともなう繰り返し熱疲労により、クラックが進展する。はんだ６が接合する部材間の線膨張係数の差が大きい場合は、接合面に平行な水平方向に亀裂が進展して応力緩衝板７Ａ、７Ｂが剥離してしまうが、線膨張係数の差が小さい場合は、接合面に垂直な方向に亀裂が進展する現象がみられる。すなわち、半導体素子側の応力緩衝板７Ａの線膨張係数αＢＡを半導体素子３の線膨張係数αＣに近づけることにより、オン、オフを繰り返すことで生じる温度サイクルにともなうはんだ６ａにかかる水平方向の亀裂を生じさせる熱応力を小さくすることができる。使用温度範囲内で両者の線膨張係数差（αＢＡ−αＣ）が５ｐｐｍ／Ｋを下回るようにすると、はんだ６ａの接合面に平行なせん断応力が著しく低下し、接合面に平行に進展する亀裂が発生しにくくなる。その場合は、はんだ６ａの厚み方向（接合面に垂直）に亀裂を生じることがあるが、厚み方向の亀裂は接合面方向と異なり、電気抵抗と熱伝導に対する影響が小さくて済む。すなわち、半導体素子３の固定、通電、放熱の各機能が損なわれる割合が少ないため、亀裂が生じてもただちに半導体装置の動作が停止することがなく、信頼性の高い接合を得ることが出来る。 The reason for such a configuration and more detailed setting will be described.
In the solder 6 used for joining the electrode member 7, cracks develop due to repeated thermal fatigue accompanying the power cycle. When the difference in the coefficient of linear expansion between the members to which the solder 6 is joined is large, cracks develop in the horizontal direction parallel to the joining surface and the stress buffer plates 7A and 7B are peeled off. When it is small, there is a phenomenon in which cracks propagate in a direction perpendicular to the joint surface. That is, by bringing the linear expansion coefficient α BA of the stress buffer plate 7A on the semiconductor element side closer to the linear expansion coefficient α C of the semiconductor element 3, the horizontal direction applied to the solder 6a due to the temperature cycle caused by repeated on and off. The thermal stress that causes cracks can be reduced. When the difference in linear expansion coefficient (α BA −α C ) between the two is less than 5 ppm / K within the operating temperature range, the shear stress parallel to the joint surface of the solder 6a is remarkably reduced and develops parallel to the joint surface. Cracks are less likely to occur. In that case, cracks may occur in the thickness direction of the solder 6a (perpendicular to the joint surface). However, unlike the joint surface direction, the cracks in the thickness direction have less influence on electrical resistance and heat conduction. That is, since the rate at which the functions of fixing, energizing, and radiating the semiconductor element 3 are impaired is small, the operation of the semiconductor device does not stop immediately even if a crack occurs, and a highly reliable bond can be obtained.

すなわち、以下の式（２）に示すように設定すると、半導体素子３と応力緩衝板７Ａ間の接合信頼性を著しく向上させることができる。
αＢＡ−αＣ＜５ [ｐｐｍ／Ｋ ＠２０℃] ・・・（２） That is, when the setting is made as shown in the following formula (2), the bonding reliability between the semiconductor element 3 and the stress buffer plate 7A can be remarkably improved.
α BA −α C <5 [ppm / K @ 20 ° C.] (2)

しかしながら、式（２）が成立するように調整した場合でも、例えば半導体素子３上面の電極（たとえばＭＯＳ−ＦＥＴのソース電極）がアルミニウムである場合は、はんだの縦割れ（接合面に垂直な割れ）に伴う変形の影響を受ける可能性がある。具体的には、アルミ層がスライドする現象や、アルミ層がはんだ中にめり込む現象である。また、半導体素子３内のゲート配線構造に応力が掛かって、半導体素子３内部が損傷を受ける可能性がある。そのため、半導体素子３と応力緩衝板７Ａとを接合するはんだ６ａに降伏応力ないし耐力の小さい材料を用いるようにする。これにより、縦割りが生じても半導体素子３の電極への影響を抑制することができる。しかし、降伏応力の小さいはんだ材料は、縦割れ現象をむしろ増大させることがあるため、長期的な信頼性を考慮すると、こうしたはんだ材料を２層用いることは不利である。そこで、応力緩衝板７Ａと応力緩衝板７Ｂとを接合するはんだ６ｂには、はんだ６ａと異なり降伏応力の大きな材料を用いることとする。これは、はんだ６ａと６ｂは同じ材料を用いる必要はなく、応力緩衝板７Ａと応力緩衝板７Ｂとの間ではアルミ層変形およびゲート配線構造の損傷を考慮する必要がないため、はんだ６ｂには、はんだ６ａより降伏応力の大きい材料を用いることが出来るからである。すなわち、半導体素子３と応力緩衝板７Ａとを接合するはんだ６ａの降伏応力をＹａ、応力緩衝板７Ａと応力緩衝板７Ｂとを接合するはんだ６ｂの降伏応力をＹｂとすると、式（３）のような関係にすればよい。
Ｙｂ＞Ｙａ ・・・（３） However, even when the adjustment is made so that the formula (2) is satisfied, for example, when the electrode on the upper surface of the semiconductor element 3 (for example, the source electrode of the MOS-FET) is aluminum, the vertical crack of the solder (the crack perpendicular to the joint surface) ) May be affected by deformation. Specifically, there are a phenomenon in which the aluminum layer slides and a phenomenon in which the aluminum layer sinks into the solder. In addition, stress is applied to the gate wiring structure in the semiconductor element 3, and the inside of the semiconductor element 3 may be damaged. Therefore, a material having a low yield stress or proof stress is used for the solder 6a that joins the semiconductor element 3 and the stress buffer plate 7A. Thereby, even if vertical division occurs, the influence on the electrode of the semiconductor element 3 can be suppressed. However, a solder material having a low yield stress may rather increase the longitudinal cracking phenomenon, so it is disadvantageous to use two layers of such a solder material in consideration of long-term reliability. Therefore, unlike the solder 6a, a material having a large yield stress is used for the solder 6b that joins the stress buffer plate 7A and the stress buffer plate 7B. This is because the solder 6a and 6b do not need to use the same material, and it is not necessary to consider the aluminum layer deformation and the damage of the gate wiring structure between the stress buffer plate 7A and the stress buffer plate 7B. This is because a material having a higher yield stress than the solder 6a can be used. That is, if the yield stress of the solder 6a that joins the semiconductor element 3 and the stress buffer plate 7A is Ya and the yield stress of the solder 6b that joins the stress buffer plate 7A and the stress buffer plate 7B is Yb, the equation (3) The relationship should be as follows.
Yb> Ya (3)

降伏応力Ｙは０．２％耐力（応力−ひずみ線図において、除荷時の永久ひずみが０．２％になる応力）に置き換えて考えることが可能であり、定量的には、半導体素子３と応力緩衝板７Ａとを接合するはんだ６ａの２０℃における０．２％耐力が２８ＭＰａ以下であることが好ましい。   Yield stress Y can be considered by replacing it with 0.2% proof stress (in the stress-strain diagram, the stress at which the permanent strain upon unloading is 0.2%). It is preferable that the 0.2% proof stress at 20 ° C. of the solder 6a that joins the stress buffer plate 7A is 28 MPa or less.

なお、半導体素子３の上面電極がアルミニウムではなく、銅などの高強度金属材料であっても、ＭＯＳＦＥＴのゲート構造の損傷などを考慮すると、上記の式（３）を満たすことで信頼性向上を図ることが可能になる。   Even if the upper surface electrode of the semiconductor element 3 is not aluminum but is made of a high-strength metal material such as copper, the reliability can be improved by satisfying the above formula (3) in consideration of damage to the gate structure of the MOSFET. It becomes possible to plan.

さらに、本発明の実施の形態１にかかる電力用半導体装置１０では、半導体素子３と直接接合しない応力緩衝板７Ｂ上にワイヤ４を接合するようにした。そのため、応力緩衝板７Ｂと配線部材であるワイヤ４との線膨張係数差を半導体素子３と応力緩衝板７Ａとの線膨張係数と独立して調整することができ、ワイヤボンディングの条件も半導体素子３への影響を考慮せず設定できる。そのため、さらに接合信頼性を向上させることができた。
以下、詳細に説明する。 Furthermore, in the power semiconductor device 10 according to the first exemplary embodiment of the present invention, the wire 4 is bonded onto the stress buffer plate 7B that is not directly bonded to the semiconductor element 3. Therefore, the difference in linear expansion coefficient between the stress buffer plate 7B and the wire 4 serving as the wiring member can be adjusted independently of the linear expansion coefficient between the semiconductor element 3 and the stress buffer plate 7A, and the wire bonding conditions are also the semiconductor element. 3 can be set without considering the effect on 3. Therefore, the joining reliability could be further improved.
Details will be described below.

一例として応力緩衝板７Ｂに銅を用い、酸化防止のためニッケルめっきを施して一般的なアルミワイヤを接合させる場合、応力緩衝板７Ｂとアルミワイヤ４の線膨張係数差（αＷ−αＢＢ）は、式（４）に示すように、８ｐｐｍ／Ｋ未満に抑えることができる。
αＷ−αＢＢ＜８ [ｐｐｍ／Ｋ ＠２０℃] ・・・（４） As an example, when copper is used for the stress buffer plate 7B, nickel plating is applied to prevent oxidation, and a general aluminum wire is joined, a difference in linear expansion coefficient between the stress buffer plate 7B and the aluminum wire 4 (α W −α BB ) Can be suppressed to less than 8 ppm / K, as shown in Equation (4).
α W −α BB <8 [ppm / K @ 20 ° C.] (4)

この場合、応力緩衝板７Ｂの物性は、上述した式（２）、（３）に独立して設定できるので、式（２）、（３）を満足させた状態で式（４）を満足させるように応力緩衝板７Ｂの線膨張係数を調整すれば、応力が低減され、半導体素子３上に直接ワイヤ４を接合する場合に比べて４０倍以上のパワーサイクル寿命を実現することが出来る。実際には、直径４００μｍ以下のアルミワイヤであれば、はんだ等の接合材の寿命を考慮して、式（５）を満たすような範囲であれば、ワイヤ４の接合部寿命として十分な性能を得ることができる。
αＷ−αＢＢ＜１３ [ｐｐｍ／Ｋ ＠２０℃] ・・・（５） In this case, since the physical properties of the stress buffer plate 7B can be set independently in the above-described equations (2) and (3), the equation (4) is satisfied in a state where the equations (2) and (3) are satisfied. Thus, by adjusting the linear expansion coefficient of the stress buffer plate 7B, the stress is reduced, and a power cycle life of 40 times or more compared with the case where the wire 4 is directly bonded onto the semiconductor element 3 can be realized. In practice, if the aluminum wire has a diameter of 400 μm or less, considering the life of the bonding material such as solder, the performance satisfying the expression (5) is sufficient as the life of the joint of the wire 4. Obtainable.
α W −α BB <13 [ppm / K @ 20 ° C.] (5)

さらに、ワイヤボンディングの際の超音波接合を半導体素子３に直接行うのではないため、超音波エネルギーが半導体素子３の一部分に集中して伝播したり、一部分に荷重がかかったりすることによる素子破壊現象を考慮する必要がない。したがって、超音波エネルギーを素子のダメージを気にせず大きく（最適化）することでワイヤ４を大きく変形させ、ワイヤ接合面積を十分に拡大することができるので、さらにパワーサイクル寿命を向上させることができる。このことは、大きい超音波エネルギーを要する太いワイヤの接合が可能になることも意味している。そのため、半導体素子３へ直接接合する場合、ゲート配線を有する電極面に対して適用に制約のあった、例えば直径５００μｍ以上のアルミワイヤでも電極部材７を介することで適用可能となり、大電流通電を行うことが出来る。同様に、接合時の超音波エネルギーの大きい幅２ｍｍ以上、厚み２００μｍ以上のアルミリボンを接合することも可能になる。リボン材料はアルミのほか、銅や銅とアルミのクラッド材を用いてもよい。   Furthermore, since the ultrasonic bonding at the time of wire bonding is not performed directly on the semiconductor element 3, the ultrasonic energy concentrates on a part of the semiconductor element 3 and propagates or a load is applied to the part. There is no need to consider the phenomenon. Therefore, by increasing (optimizing) the ultrasonic energy without worrying about damage to the element, the wire 4 can be greatly deformed and the wire bonding area can be sufficiently expanded, so that the power cycle life can be further improved. it can. This also means that thick wires that require large ultrasonic energy can be joined. Therefore, when bonding directly to the semiconductor element 3, for example, an aluminum wire having a diameter of 500 μm or more, which is limited in application to the electrode surface having the gate wiring, can be applied through the electrode member 7, and a large current can be applied. Can be done. Similarly, it is possible to join an aluminum ribbon having a width of 2 mm or more and a thickness of 200 μm or more with a large ultrasonic energy during joining. In addition to aluminum, the ribbon material may be copper or a clad material of copper and aluminum.

また、半導体素子の動作可能な最高温度に達する時間は短いため、熱伝導による温度分布は定常的なものではなく過渡的なものになる。したがって、ワイヤ４の接合部が発熱原である半導体素子３の表面から距離をおいた構造では、動作時の半導体素子３の発熱によるワイヤ接合部の温度上昇が抑制される。このため、半導体素子３の直上にワイヤ接合する場合や、半導体素子３上に接合された緩衝板に直接ワイヤを接合する場合に較べて熱応力が低減される。特に、応力緩衝板に熱伝導率の低いインバー合金を含む材料を用いると、この効果が顕著となる。   Further, since the time to reach the maximum temperature at which the semiconductor element can operate is short, the temperature distribution due to heat conduction is not steady but transient. Therefore, in the structure in which the bonding portion of the wire 4 is spaced from the surface of the semiconductor element 3 that is the heat generation source, the temperature increase of the wire bonding portion due to the heat generation of the semiconductor element 3 during operation is suppressed. For this reason, thermal stress is reduced as compared with the case where the wire is bonded directly above the semiconductor element 3 or the case where the wire is directly bonded to the buffer plate bonded onto the semiconductor element 3. In particular, when a material containing an Invar alloy having a low thermal conductivity is used for the stress buffer plate, this effect becomes remarkable.

応力緩衝板７Ａ、７Ｂには、前述の通り比較的安価な、銅、インバー合金、銅の三層構成のクラッド材を用いることが可能であり、各応力緩衝板の線膨張係数は、クラッド材の構成により調整でき、低熱膨張材と高熱膨張材の厚みの比率を変えることで制御することが出来る。たとえば、低熱膨張材であるインバー合金を高熱膨張材である銅で挟んだクラッド材中の厚み比率を１：３：１とすると、クラッド材全体の線膨張係数はおよそ７ｐｐｍ／Ｋとなり、式（２）を満足する応力緩衝板７Ａを得ることができる。同様に、高熱膨張材の比率を上げるように厚み比率を調整することで、式（４）を満足する応力緩衝板７Ｂを得ることができる。銅とインバーの組み合わせで応力緩衝板７Ａ、７Ｂを製作する場合、応力緩衝板７Ａにおける銅の総厚みに対するインバー合金の厚みの比率をＲＡ、応力緩衝板７Ｂにおける銅の総厚みに対するインバー合金の厚みの比率をＲＢとすると、ＲＢ＜ＲＡとなるようにすれば、αＢＡ＜αＢＢの関係が成り立つように調整することができる。 As the stress buffer plates 7A and 7B, it is possible to use a relatively inexpensive clad material having a three-layer structure of copper, an invar alloy, and copper as described above. The linear expansion coefficient of each stress buffer plate is determined by the clad material. And can be controlled by changing the thickness ratio between the low thermal expansion material and the high thermal expansion material. For example, if the thickness ratio in a clad material in which an invar alloy that is a low thermal expansion material is sandwiched by copper that is a high thermal expansion material is 1: 3: 1, the linear expansion coefficient of the entire clad material is approximately 7 ppm / K. The stress buffer plate 7A satisfying 2) can be obtained. Similarly, by adjusting the thickness ratio so as to increase the ratio of the high thermal expansion material, it is possible to obtain the stress buffer plate 7B that satisfies Expression (4). When the stress buffer plates 7A and 7B are manufactured by a combination of copper and invar, the ratio of the thickness of the invar alloy to the total thickness of copper in the stress buffer plate 7A is R A , and the ratio of the invar alloy to the total thickness of copper in the stress buffer plate 7B is Assuming that the thickness ratio is R B , if R B <R A is satisfied, the relationship of α BA <α BB can be adjusted.

なお、図１では応力緩衝板７Ｂの平面サイズを応力緩衝板７Ａより小さくなるように構成している。この構成により、応力緩衝板７Ｂ下の緩衝板用はんだ６ｂがフィレットを形成することが可能となっている。フィレットを形成することによってはんだ接合の信頼性を高め、外観検査による接合確認も容易になるので、緩衝板用はんだ６ｂ、緩衝板用はんだ６ａ、ダイボンド用はんだ５の３段からなる接合層を一括リフローにて接合することが可能になる。   In FIG. 1, the plane size of the stress buffer plate 7B is configured to be smaller than the stress buffer plate 7A. With this configuration, the buffer plate solder 6b under the stress buffer plate 7B can form a fillet. By forming the fillet, the reliability of the solder joint is improved and the joint confirmation by the appearance inspection is also facilitated. Therefore, the joint layer composed of three stages of the buffer plate solder 6b, the buffer plate solder 6a, and the die bond solder 5 is collectively formed. It becomes possible to join by reflow.

つぎに動作について説明する。
電力用半導体装置１０を駆動させると、半導体素子３をはじめとする電力用半導体装置１０内の様々な素子に電流が流れ、その際、電気抵抗分の電力ロスが熱へと変換され、発熱が生ずる。例えば、半導体素子３に、ＳｉＣのような高性能のワイドバンドギャップ半導体素子が用いられているような場合、電流が大きく、動作時の温度は３００℃にまで達する。このとき、半導体素子３とワイヤ４間の線膨張係数に差があるので、半導体素子３と電極部材７とワイヤ４間の接合界面に熱応力が発生する。 Next, the operation will be described.
When the power semiconductor device 10 is driven, a current flows through various elements in the power semiconductor device 10 including the semiconductor element 3. At this time, a power loss corresponding to the electrical resistance is converted into heat, and heat is generated. Arise. For example, when a high-performance wide bandgap semiconductor element such as SiC is used for the semiconductor element 3, the current is large and the operating temperature reaches 300 ° C. At this time, since there is a difference in the coefficient of linear expansion between the semiconductor element 3 and the wire 4, thermal stress is generated at the bonding interface between the semiconductor element 3, the electrode member 7, and the wire 4.

しかし、本実施の形態１にかかる電力用半導体装置１０では、半導体素子３とワイヤ５間に設けた電極部材７を構成する２枚の応力緩衝板７Ａ、７Ｂのうち、半導体素子３側の応力緩衝板７Ａの線膨張係数αＢＡを半導体素子３の線膨張係数αＣとの差が第１の所定値である５ｐｐｍ／Ｋ未満（式（２））になるように設定し、ワイヤ４側の応力緩衝板７Ｂの線膨張係数αＢＢを、半導体素子３の線膨張係数αＣまたは応力緩衝板７Ａの線膨張係数αＢＡと独立して、ワイヤ４の線膨張係数αＷとの差が第２の所定値である１３ｐｐｍ／Ｋ未満（式（５））になるように設定した。そのため、半導体素子３側では、はんだ６ａを用いて接合された応力緩衝板７Ａと半導体素子３間の熱応力をはんだ接合や半導体素子３の電極に対応した許容範囲内に抑えることにより接合信頼性が向上する。また、ワイヤ４側でも、ワイヤボンディングにより直接接合された応力緩衝板７Ｂとワイヤ４間の熱応力をボンディングに対応した許容範囲内に抑えることにより接合信頼性が向上する。 However, in the power semiconductor device 10 according to the first embodiment, the stress on the semiconductor element 3 side of the two stress buffer plates 7A and 7B constituting the electrode member 7 provided between the semiconductor element 3 and the wire 5 is reduced. The linear expansion coefficient α BA of the buffer plate 7A is set so that the difference from the linear expansion coefficient α C of the semiconductor element 3 is less than the first predetermined value of 5 ppm / K (formula (2)), and the wire 4 side The difference between the linear expansion coefficient α BB of the stress buffer plate 7B and the linear expansion coefficient α W of the semiconductor element 3 is independent of the linear expansion coefficient α C of the semiconductor element 3 or the linear expansion coefficient α BA of the stress buffer plate 7A. The second predetermined value was set to be less than 13 ppm / K (formula (5)). Therefore, on the semiconductor element 3 side, the bonding stress is suppressed by suppressing the thermal stress between the stress buffer plate 7A bonded using the solder 6a and the semiconductor element 3 within an allowable range corresponding to the solder bonding or the electrode of the semiconductor element 3. Will improve. Further, also on the wire 4 side, the bonding reliability is improved by suppressing the thermal stress between the stress buffer plate 7B directly bonded by wire bonding and the wire 4 within an allowable range corresponding to bonding.

また、電流は時間的に大きく変化するので、発熱および熱伝導にともなう温度分布は定常的なものではなく過渡的であり、半導体素子３が最高到達温度に達している時間も短時間である。そのため、本実施の形態１にかかる電極部材７のように板材を接合材であるはんだ６ｂを介して層状に重ねた電極部材７がワイヤ４と半導体素子３間に介在することにより、発熱源である半導体素子３の表面から離れたワイヤ４では、熱伝導遅れのために温度上昇が抑制される。このため、半導体素子３の直上にワイヤ４等の配線部材を接合する場合に較べてワイヤ４との接合部の温度変化量および最高到達温度が抑制され、熱応力を低減できる。すなわち、最高到達温度が高く、温度変化量の大きなパワーサイクル負荷にも耐えることが可能になる。   Further, since the current changes greatly with time, the temperature distribution due to heat generation and heat conduction is not steady but transient, and the time during which the semiconductor element 3 reaches the maximum temperature is also short. Therefore, as the electrode member 7 according to the first embodiment, the electrode member 7 in which the plate material is laminated in layers via the solder 6b which is the bonding material is interposed between the wire 4 and the semiconductor element 3, thereby generating a heat source. In the wire 4 away from the surface of a certain semiconductor element 3, the temperature rise is suppressed due to the heat conduction delay. For this reason, compared with the case where wiring members, such as the wire 4, are joined just above the semiconductor element 3, the temperature change amount and the maximum temperature at the joint with the wire 4 are suppressed, and the thermal stress can be reduced. That is, it is possible to withstand a power cycle load having a high maximum temperature and a large amount of temperature change.

以上のように、本発明の実施の形態１にかかる（電力用）半導体装置１０によれば、絶縁基板１の回路面１ｆに一方の面が接合された半導体素子３と、半導体素子３の他方の面に形成された電極に、接合材６ａを介して、一方の面が接合された第１の緩衝板である応力緩衝板７Ａと、第１の緩衝板７Ａの他方の面に、接合材６ｂを介して、一方の面が接合された第２の緩衝板である応力緩衝板７Ｂと、第２の緩衝板７Ｂの他方の面に接合された配線部材であるワイヤ４と、を備え、第１の緩衝板７Ａは、半導体素子の線膨張係数αＣと配線部材４の線膨張係数αＷの間であって、半導体素子３の線膨張係数αＣとの差が第１の所定値より小さい線膨張係数αＢＡを有し（式（２））、第２の緩衝板７Ｂは、第１の緩衝板７Ａの線膨張係数αＢＡと配線部材４の線膨張係数αＷの間であって、配線部材４の線膨張係数αＷとの差が第１の所定値より大きな第２の所定値より小さい線膨張係数αＢＢを有する（式（４））、ように構成したので、半導体素子３と第１の緩衝板７Ａ間の熱応力を適切に抑制するとともに、第２の緩衝板７Ｂと配線部材４間の熱応力も半導体素子３側の状況と独立して適切に抑制することができるので、最高到達温度が高く、温度変化量が大きくなっても、パワーサイクル寿命が飛躍的に伸びる。また、ワイヤボンディング時の超音波振動が半導体素子３に直接伝わることがなく、半導体素子への影響を最小限にして強力なボンディングが可能となる。 As described above, according to the semiconductor device 10 (for power) according to the first embodiment of the present invention, the semiconductor element 3 having one surface bonded to the circuit surface 1f of the insulating substrate 1 and the other of the semiconductor elements 3 A stress buffer plate 7A, which is a first buffer plate, one surface of which is bonded to the electrode formed on the surface of the first buffer plate 7A via a bonding material 6a, and a bonding material on the other surface of the first buffer plate 7A A stress buffer plate 7B, which is a second buffer plate bonded on one surface via 6b, and a wire 4, which is a wiring member bonded to the other surface of the second buffer plate 7B, The first buffer plate 7A is between the linear expansion coefficient α C of the semiconductor element and the linear expansion coefficient α W of the wiring member 4, and the difference between the linear expansion coefficient α C of the semiconductor element 3 is a first predetermined value. have a smaller linear expansion coefficient alpha BA (equation (2)), a second buffer plate 7B is the linear expansion coefficient of the first buffer plate 7A alpha B Having a A between the linear expansion coefficient alpha W of the wiring member 4, the difference between the linear expansion coefficient alpha W of the wiring member 4 is a first larger second predetermined value smaller than the linear expansion coefficient than the predetermined value alpha BB (Equation (4)), the thermal stress between the semiconductor element 3 and the first buffer plate 7A is appropriately suppressed, and the thermal stress between the second buffer plate 7B and the wiring member 4 is also a semiconductor. Since it can be appropriately suppressed independently of the situation on the element 3 side, the power cycle life is dramatically extended even when the maximum temperature reached is high and the temperature change amount is large. Further, ultrasonic vibration during wire bonding is not directly transmitted to the semiconductor element 3, and strong bonding is possible with minimal influence on the semiconductor element.

とくに、配線部材であるワイヤ４と第２の緩衝板７Ｂとの接合が超音波接合によりなされたとき、第１の所定値を式（２）に示すように５ｐｐｍ／Ｋとし、第２の所定値を式（５）に示すように１３ｐｐｍ／Ｋであるようにしたので、最高到達温度が３００℃に達しても、半導体素子３と第１の緩衝板７Ａ間の熱応力を確実に抑制し、さらに超音波接合した第２の緩衝板７Ｂと配線部材４間の熱応力も確実に抑制することができる。   In particular, when the wire 4 as the wiring member and the second buffer plate 7B are joined by ultrasonic joining, the first predetermined value is set to 5 ppm / K as shown in the equation (2), and the second predetermined value is set. Since the value is 13 ppm / K as shown in Equation (5), even if the maximum temperature reaches 300 ° C., the thermal stress between the semiconductor element 3 and the first buffer plate 7A is surely suppressed. Furthermore, the thermal stress between the second buffer plate 7B and the wiring member 4 that are ultrasonically bonded can be reliably suppressed.

さらに、半導体素子３と第１の緩衝板７Ａとを接合する接合材６ａの接合後の降伏応力Ｙａは、第１の緩衝板７Ａと第２の緩衝板７Ｂとを接合する接合材６ｂの接合後の降伏応力Ｙｂよりも小さいように構成したので、接合力を損なうことなく、半導体素子に形成された電極への損傷を抑制することができる。   Further, the yield stress Ya after joining of the joining material 6a for joining the semiconductor element 3 and the first buffer plate 7A is the joining of the joining material 6b for joining the first buffer plate 7A and the second buffer plate 7B. Since it is configured to be smaller than the later yield stress Yb, damage to the electrodes formed in the semiconductor element can be suppressed without impairing the bonding force.

接合材６に焼結性の銀微粒子を含む接合材、またははんだを用いると、半導体素子３、緩衝板７Ａ、７Ｂ、ワイヤ４自体に損傷を与えず、信頼性の高い接合が得られる。   When a bonding material containing sinterable silver fine particles or solder is used as the bonding material 6, the semiconductor element 3, the buffer plates 7A and 7B, and the wires 4 themselves are not damaged, and a highly reliable bonding can be obtained.

実施の形態２．
本実施の形態２にかかる電力用半導体装置においては、電極部材を構成する応力緩衝板の平面サイズを実施の形態１にかかる電極部材と異なり、ワイヤ側のサイズを半導体素子側より大きくするようにしたものである。その他の構成部分については、実施の形態１と同様であるので説明を省略する。 Embodiment 2. FIG.
In the power semiconductor device according to the second embodiment, unlike the electrode member according to the first embodiment, the plane size of the stress buffer plate constituting the electrode member is made larger than the semiconductor element side. It is a thing. Since other components are the same as those in the first embodiment, description thereof is omitted.

図２および図３は本実施の形態２にかかる電力用半導体装置を説明するためのもので、図２は実施の形態１における図１（ｂ）に対応する部分から半導体素子の近傍部分に限定した電力用半導体装置の構成を説明するための部分断面図である。図３は本実施の形態２における電力用半導体装置の製造方法を説明するための工程ごとの断面図である。図２に示すように、電極部材２０７を構成する２枚の応力緩衝板のうち、半導体素子３側の応力緩衝板７Ａは実施の形態１における応力緩衝板７Ａと同じものを用いたが、ワイヤ４側の応力緩衝板２０７Ｂは、実施の形態１における応力緩衝板７Ｂと同じ材質であるが、平面寸法を応力緩衝板７Ａより大きいものを使用した。   2 and 3 are for explaining the power semiconductor device according to the second embodiment, and FIG. 2 is limited to a portion near the semiconductor element from the portion corresponding to FIG. 1B in the first embodiment. It is a fragmentary sectional view for demonstrating the structure of the manufactured semiconductor device for electric power. FIG. 3 is a cross-sectional view for each step for explaining the method for manufacturing the power semiconductor device according to the second embodiment. As shown in FIG. 2, among the two stress buffer plates constituting the electrode member 207, the stress buffer plate 7A on the semiconductor element 3 side is the same as the stress buffer plate 7A in the first embodiment. The stress buffer plate 207B on the 4th side is made of the same material as the stress buffer plate 7B in the first embodiment, but a plane size larger than that of the stress buffer plate 7A is used.

このような構成をとることができるのは、２枚の応力緩衝板のうち、ワイヤ４側の応力緩衝板２０７Ｂが半導体素子３から空間的に離れた位置に配置されることになり、原理的に、半導体素子３の形状（電極サイズ）の制約を受けなくなるので、半導体素子３の電極面積を越えて拡大することが可能となるからである。これにより、半導体素子３のチップ面積と、チップ外周の絶縁部で制約を受けていた接合ワイヤ本数を図２に示すように、ワイヤ４ａ，４ｂのように増やすことが可能になるため、同じ電流に対してワイヤ１本あたりの通電量が低減し、通電によるワイヤの発熱を低減し、ワイヤ発熱に因るチップ温度上昇を抑制することで、パワーサイクル寿命を改善することが可能となる。このことは、ワイヤのループ長に比例するワイヤの電気抵抗の許容値が高くなることを意味しており、長いワイヤループにより、パワーモジュールの設計を容易にすることが出来る。さらに、ワイヤループを長くすることで、パワーサイクル寿命の第２のファクターであるワイヤの通電／非通電サイクルでのループ変形による疲労破壊の寿命を延ばすことにもつながる。   Such a configuration can be adopted because the stress buffer plate 207 </ b> B on the wire 4 side of the two stress buffer plates is disposed at a position spatially separated from the semiconductor element 3. In addition, since the shape (electrode size) of the semiconductor element 3 is not restricted, it is possible to expand beyond the electrode area of the semiconductor element 3. As a result, it is possible to increase the chip area of the semiconductor element 3 and the number of bonding wires restricted by the insulating portion on the outer periphery of the chip as shown in FIG. On the other hand, the amount of energization per wire is reduced, the heat generation of the wire due to the energization is reduced, and the rise in the chip temperature due to the wire heat generation is suppressed, so that the power cycle life can be improved. This means that the allowable value of the electric resistance of the wire proportional to the loop length of the wire is increased, and the design of the power module can be facilitated by the long wire loop. Further, by extending the wire loop, it is possible to extend the life of fatigue failure due to loop deformation in the energization / non-energization cycle of the wire, which is the second factor of the power cycle life.

なお、図２では、実施の形態１との違いとして、ワイヤ本数を増加させることを説明するために、図１で示した本数（一本）より本数の多い２本のワイヤを示しているのであって、実際に用いる本数や配置を限定するものではない。   In FIG. 2, two wires having a larger number than the number (one) shown in FIG. 1 are shown to explain that the number of wires is increased as a difference from the first embodiment. Thus, the number and arrangement actually used are not limited.

つぎに製造方法について説明する。
本実施の形態２にかかる電力用半導体装置のアセンブリ工程においてポイントとなるのは、応力緩衝板７Ａと応力緩衝板２０７Ｂの接合工程である。ワイヤ４側の応力緩衝板２０７Ｂを半導体素子３の電極面積等の制約を越えて拡大すると、半導体素子３の電極面積等に大きさを制約される半導体素子３側の応力緩衝板７Ａは、応力緩衝板２０７Ｂに較べて平面寸法が小さくなることになる。したがって、実施の形態１で説明したように、電力用半導体装置の回路面の上側から外観検査しただけでは、接合確認を容易に行うことができない。そのため、本実施の形態２においては、図３に示すようにして電力用半導体装置２１０を製造した。 Next, the manufacturing method will be described.
The point in the assembly process of the power semiconductor device according to the second embodiment is the joining process of the stress buffer plate 7A and the stress buffer plate 207B. When the stress buffer plate 207B on the wire 4 side is enlarged beyond the constraints such as the electrode area of the semiconductor element 3, the stress buffer plate 7A on the semiconductor element 3 side whose size is limited by the electrode area of the semiconductor element 3 is reduced. The plane dimension is smaller than that of the buffer plate 207B. Therefore, as described in the first embodiment, it is not possible to easily confirm the bonding simply by performing an appearance inspection from the upper side of the circuit surface of the power semiconductor device. Therefore, in the second embodiment, the power semiconductor device 210 is manufactured as shown in FIG.

本実施の形態２においては、図３（ａ）、図３（ｂ）に示すように、はじめに面積の広い応力緩衝板２０７Ｂ上に、応力緩衝板７Ａとの接合材であるはんだ材の膜６ｂＭを形成する。そして、図３（ｃ）に示すように、応力緩衝板２０７Ｂ上に形成したはんだの膜６ｂＭの上に応力緩衝板７Ａを重ね、リフローにより応力緩衝板２０７Ｂと７Ａを接合して電極部材２０７を単独で形成する。そして、図３（ｄ）に示すように、絶縁基板１に実装された半導体素子３上に形成された接合材であるはんだの膜６ａＭ上に、上下を反転させた電極部材２０７を重ね、リフローにより電極部材２０７を接合する。最後に、図３（ｅ）に示すように、ワイヤ４ａ，４ｂを超音波接合によりボンディングして電力用半導体装置２１０が完成する。 In the second embodiment, as shown in FIGS. 3A and 3B, a solder material film 6b which is a bonding material to the stress buffer plate 7A is first formed on the stress buffer plate 207B having a large area. M is formed. Then, as shown in FIG. 3 (c), overlapped stress buffer plate 7A on the solder layer 6b M formed on the stress buffering plate 207B, the electrode member 207 by bonding stress buffer plate 207B and 7A by reflow Is formed alone. Then, as shown in FIG. 3 (d), on the solder film 6a M is a bonding material formed on the semiconductor element 3 mounted on the insulating substrate 1, stacked electrode member 207 turned upside down, The electrode member 207 is joined by reflow. Finally, as shown in FIG. 3E, the wires 4a and 4b are bonded by ultrasonic bonding to complete the power semiconductor device 210.

上記製造方法では、リフロー時に面積の大きな部材が下に位置するようになるので、面積の大きな部材側に広がるフィレットを容易に形成する事ができる。また、応力緩衝板７Ａは３層構造のうち、中間層には、はんだとの濡れ性が銅より低いインバーが配置されているので、応力緩衝板７Ａから半導体素子３側および応力緩衝板２０７Ｂ側に形成したそれぞれのフィレットは、応力緩衝板７Ａの厚さ方向の中間部分で一体化することなく分離することができる。したがって、フィレット形成により接合部の信頼性が向上するとともに、応力緩衝板７Ａの厚み方向のそれぞれ反対側に配置される接合材６ａと６ｂは、それぞれ独立することになるので、それぞれに加わる応力が互いに影響を及ぼしあうことを防止する事ができる。   In the above manufacturing method, a member having a large area is positioned below at the time of reflow, so that a fillet spreading toward the member having a large area can be easily formed. Further, in the stress buffer plate 7A, among the three-layer structure, an invar having lower wettability with the solder than copper is disposed in the intermediate layer, so that the semiconductor element 3 side and the stress buffer plate 207B side from the stress buffer plate 7A. Each fillet formed in (1) can be separated without being integrated at an intermediate portion in the thickness direction of the stress buffer plate 7A. Accordingly, the reliability of the joint is improved by the fillet formation, and the joining materials 6a and 6b disposed on the opposite sides in the thickness direction of the stress buffer plate 7A are independent from each other. It is possible to prevent mutual influences.

なお、先に電極部材として２枚の応力緩衝板７Ａと２０７Ｂの一体化に用いるはんだ材料６ｂの融点を、半導体素子３との接合に用いるはんだ材６ａの融点より高くすることで、さらに製造が容易になる。また、２枚の応力緩衝板の接合材料として、焼結性の銀粒子を用いたり、銅などを拡散させる錫材を用いたりする場合には、上記のように、電極部材２０７部分を単独で接合するようにすれば、応力緩衝板７Ａと２０７Ｂの接合時に最適な圧力を掛けることが可能になるため、緻密な接合構造（銀粒子の場合、緻密な銀焼結体）を得ることができる。その際、圧力を掛けることで応力緩衝板７Ａの端部からはみ出して応力緩衝板２０７Ｂ上に広がる領域が生じても応力緩衝板２０７Ｂ上に広がるだけで問題を生じない。   It should be noted that the manufacturing process can be further increased by making the melting point of the solder material 6b used for the integration of the two stress buffer plates 7A and 207B as electrode members higher than the melting point of the solder material 6a used for joining to the semiconductor element 3. It becomes easy. In addition, when using sinterable silver particles or a tin material for diffusing copper or the like as a bonding material for the two stress buffer plates, as described above, the electrode member 207 portion alone is used. If it joins, since it becomes possible to apply an optimal pressure at the time of joining the stress buffer plates 7A and 207B, a dense joint structure (in the case of silver particles, a dense silver sintered body) can be obtained. . At this time, even if a region that protrudes from the end portion of the stress buffer plate 7A and expands on the stress buffer plate 207B is generated by applying pressure, it does not cause a problem only by spreading on the stress buffer plate 207B.

以上のように、本発明の実施の形態２にかかる（電力用）半導体装置２１０によれば、第２の緩衝板である応力緩衝板２０７Ｂの面積（平面寸法）は、第１の緩衝板である応力緩衝板７Ａの面積よりも大きいように構成したので、半導体素子３の電極面積の制約を超えてワイヤ本数を増加させることができ、抵抗ロスによる発熱を低減し、さらに信頼性の高い半導体装置を得ることができる。   As described above, according to the semiconductor device 210 (for power) according to the second embodiment of the present invention, the area (planar dimension) of the stress buffer plate 207B that is the second buffer plate is the first buffer plate. Since it is configured so as to be larger than the area of a certain stress buffer plate 7A, the number of wires can be increased beyond the limitation of the electrode area of the semiconductor element 3, heat generation due to resistance loss is reduced, and a highly reliable semiconductor A device can be obtained.

以上のように、本発明の実施の形態２にかかる電力用半導体装置２１０の製造方法によれば、第１の緩衝板７Ａの他方の面と第２の緩衝板２０７Ｂの一方の面とを接合材６ｂを介して接合した電極部材７を形成する工程と、電極部材７の第１の緩衝板７Ａ側の面を、絶縁基板１に接合された半導体素子３の電極に接合材６ａを介して接合する工程と、電極部材７の第２の緩衝板２０７Ｂ側の面に、超音波接合により配線部材４を接合する工程と、を備えるように構成したので、フィレットが適切に形成されて接合部の信頼性が向上する。   As described above, according to the method for manufacturing the power semiconductor device 210 according to the second embodiment of the present invention, the other surface of the first buffer plate 7A and the one surface of the second buffer plate 207B are joined. The step of forming the electrode member 7 bonded through the material 6b and the surface of the electrode member 7 on the first buffer plate 7A side are connected to the electrode of the semiconductor element 3 bonded to the insulating substrate 1 through the bonding material 6a. And a step of bonding the wiring member 4 to the surface of the electrode member 7 on the second buffer plate 207B side by ultrasonic bonding, so that the fillet is appropriately formed and the bonded portion Reliability is improved.

実施の形態３．
本実施の形態３にかかる電力用半導体装置においては、実施の形態２と同様にワイヤ側の応力緩衝板が半導体素子側の応力緩衝板より大きくなっており、ワイヤ側の応力緩衝板の端部は半導体素子（チップ）の外周部を乗り越える構成となっている。このような、大面積の応力緩衝板を備えた電極部材を半導体素子上に接合する際に、電極部材（とくに上側に位置する大面積の応力緩衝板）の自重による傾きを抑制するため、本実施の形態３における電力用半導体装置では、少なくとも電極部材を半導体素子に接合するときにスペーサを設置するようにした。その他の構成については、上記実施の形態２と同様であるので説明を省略する。 Embodiment 3 FIG.
In the power semiconductor device according to the third embodiment, the stress buffer plate on the wire side is larger than the stress buffer plate on the semiconductor element side as in the second embodiment, and the end portion of the stress buffer plate on the wire side Is configured to overcome the outer periphery of the semiconductor element (chip). In order to suppress the inclination due to the weight of the electrode member (especially, the large-area stress buffer plate located on the upper side) when joining such an electrode member having a large-area stress buffer plate on the semiconductor element, In the power semiconductor device according to the third embodiment, the spacer is provided at least when the electrode member is bonded to the semiconductor element. Since other configurations are the same as those of the second embodiment, description thereof is omitted.

図４は本実施の形態３にかかる電力用半導体装置の構成を説明するための部分断面図である。また、図５は本実施の形態３にかかる電力用半導体装置において使用する接合材の一例の構成を説明するための半導体素子と応力緩衝板との接合部分の断面図である。図４に示すように、電極部材３０７を構成する２枚の応力緩衝板のうち、半導体素子３側の応力緩衝板７Ａは実施の形態１および２における応力緩衝板７Ａと同じものを用いたが、ワイヤ４側の応力緩衝板３０７Ｂは、実施の形態２における応力緩衝板２０７Ｂよりもさらに大きなものを使用した。さらに、応力緩衝板３０７Ｂの面に平行な方向における応力緩衝板７Ａからのはみ出し長さを、他端Ｅ２側よりも一端Ｅ１側の方が大きくなるように面方向で中心から偏って接合するようにした。そして、応力緩衝板７Ａに対してはみ出し量が大きな一端１Ｅ側の面と絶縁基板１との間には、例えば、実施の形態２のように電極部材３０７自体を予め形成する場合は、少なくとも電極部材３０７を半導体素子３に接合するときに、スペーサ８を設置するようにした。あるいは、応力緩衝板７Ａ、３０７Ｂを順次半導体素子３上に接合していく場合は、少なくとも応力緩衝板３０７Ｂを応力緩衝板７Ａに接合するときに、一端１Ｅ側の面と絶縁基板１との間にスペーサ８を設置するようにした。   FIG. 4 is a partial cross-sectional view for explaining the configuration of the power semiconductor device according to the third embodiment. FIG. 5 is a cross-sectional view of a joining portion between a semiconductor element and a stress buffer plate, for explaining a configuration of an example of a joining material used in the power semiconductor device according to the third embodiment. As shown in FIG. 4, among the two stress buffer plates constituting the electrode member 307, the stress buffer plate 7A on the semiconductor element 3 side is the same as the stress buffer plate 7A in the first and second embodiments. The stress buffer plate 307B on the wire 4 side is larger than the stress buffer plate 207B in the second embodiment. Further, the protrusion length from the stress buffer plate 7A in the direction parallel to the surface of the stress buffer plate 307B is bonded so as to be offset from the center in the surface direction so that the one end E1 side is larger than the other end E2 side. I made it. When the electrode member 307 itself is formed in advance, for example, as in the second embodiment, between the surface on the one end 1E side where the amount of protrusion is large with respect to the stress buffer plate 7A and the insulating substrate 1, at least the electrode The spacer 8 is installed when the member 307 is joined to the semiconductor element 3. Alternatively, when the stress buffer plates 7A and 307B are sequentially bonded onto the semiconductor element 3, at least when the stress buffer plate 307B is bonded to the stress buffer plate 7A, the surface between the one end 1E side and the insulating substrate 1 is used. The spacer 8 was installed on the surface.

なお、スペーサ８は、電極部材３０７あるいは、応力緩衝板３０７Ｂの接合完了後、除去すればよい。また、スペーサ９を絶縁性の部材として絶縁基板１の銅パターン２ａ上に接合してもよい。もちろん、スペーサ８の接合対象は、半導体素子３が接合された配線パターンと同じ配線パターンである必要はない。また絶縁基板１に直接接合し、配線パターンに接触しないのであれば、スペーサ８に導電性の部材を使用してもよい。   The spacer 8 may be removed after the electrode member 307 or the stress buffer plate 307B is completely joined. Further, the spacer 9 may be bonded onto the copper pattern 2a of the insulating substrate 1 as an insulating member. Of course, the bonding target of the spacer 8 need not be the same wiring pattern as the wiring pattern to which the semiconductor element 3 is bonded. Further, a conductive member may be used for the spacer 8 as long as it is directly bonded to the insulating substrate 1 and does not contact the wiring pattern.

この構成によれば、ワイヤの本数をさらに増大させることができ、電流容量を確保するとともに、パワーサイクル寿命の長い半導体装置を得ることが出来る。なお、この構成においては、図に示すように、例えばＭＯＳＦＥＴの場合、制御信号を入力するためのゲートワイヤ３４が必要であり、応力緩衝板３０７Ｂの張り出す（偏る）方向およびスペーサ８の位置をゲートワイヤ３４の無い方向（Ｅ１側）に設定すればよい。   According to this configuration, the number of wires can be further increased, a current capacity can be ensured, and a semiconductor device having a long power cycle life can be obtained. In this configuration, as shown in the figure, for example, in the case of a MOSFET, a gate wire 34 for inputting a control signal is necessary, and the direction in which the stress buffer plate 307B projects (bias) and the position of the spacer 8 are set. What is necessary is just to set to the direction (E1 side) where the gate wire 34 does not exist.

また、上記のように一端Ｅ１側のみにスペーサ８を配置した場合でも、接合材６ａあるいは６ｂにはんだを使用し、はんだの量および加圧力を適切に調整すれば、はんだの表面張力によって、他端Ｅ２側の接合面間の距離（例えば、７Ａ−３間、あるいは７Ａ−３０７Ｂ間）、つまりはんだ厚みはほぼ一定に保つことができる。しかし、確実に接合面間の距離を保つため、図５に示すように、接合材６ａＶとして、基本的には設定したいはんだ厚みと同じ径Ｄｇの厚み保持材として機能するビーズ材料９を含む接合材を用いるようにしてもよい。この場合、はんだリフロー時に接合面間の距離がビーズ径に等しくなるように所定圧をかけるとよい。接合材に焼結性の銀を用いた場合でも、ビーズ９を混入させると同様に厚みを所定厚みに保持することができる。接合材６ａＶのベースがはんだ材料の場合、ビーズ９には、たとえば、はんだ材料でコーティングされた耐熱性樹脂材料からなる粒子や、銅、ニッケルなど、はんだとのなじみのよい金属粒子を用いるとよい。また、ビーズ９に替えて、ワイヤボンダを利用して銅ワイヤ等のワイヤバンプを用いても良い。 Even when the spacer 8 is disposed only on the one end E1 side as described above, if the solder is used for the bonding material 6a or 6b and the amount of solder and the applied pressure are appropriately adjusted, the surface tension of the solder causes other The distance between the joint surfaces on the end E2 side (for example, between 7A-3 or 7A-307B), that is, the solder thickness can be kept substantially constant. However, to keep reliably the distance between the bonding surfaces, as shown in FIG. 5, including a bonding material 6a V, the bead material 9 which functions as a thickness holding material having the same diameter Dg solder thickness to be set basically A bonding material may be used. In this case, it is preferable to apply a predetermined pressure so that the distance between the joining surfaces becomes equal to the bead diameter during solder reflow. Even when sinterable silver is used for the bonding material, the thickness can be maintained at a predetermined thickness in the same manner as the beads 9 are mixed. When the base of the bonding material 6a V is a solder material, for the beads 9, for example, particles made of a heat-resistant resin material coated with a solder material, or metal particles that are compatible with solder, such as copper and nickel, are used. Good. Moreover, it may replace with the bead 9 and may use wire bumps, such as a copper wire, using a wire bonder.

以上のように、本発明の実施の形態３にかかる電力用半導体装置３１０によれば、第２の緩衝板３０７Ｂの面積は、第１の緩衝板７Ａの面積よりも大きく、第１の緩衝板７Ａは、第２の緩衝板３０７Ｂに対して偏った位置（Ｅ２側）に接合され、第２の緩衝板３０７Ｂの第１の緩衝板７Ａからはみ出た部分（Ｅ１側の面）と、絶縁基板１との間にスペーサ８が挿入されているように構成したので、電極部材３０７を形成してから半導体素子３に接合するときは、半導体素子３と第１の緩衝板７Ａ間、半導体素子３に接合された第１の緩衝板７Ａに第２の緩衝板３０７Ｂを接合するときは、第１の緩衝板７Ａと第２の緩衝板３０７Ｂ間の接合面間の距離を所定範囲に制御する事ができる。   As described above, according to the power semiconductor device 310 according to the third embodiment of the present invention, the area of the second buffer plate 307B is larger than the area of the first buffer plate 7A. 7A is joined to a position (E2 side) that is biased with respect to the second buffer plate 307B, and a portion of the second buffer plate 307B that protrudes from the first buffer plate 7A (surface on the E1 side), and an insulating substrate 1, the spacer 8 is inserted between the semiconductor element 3 and the semiconductor element 3 when the electrode member 307 is formed and bonded to the semiconductor element 3. When the second buffer plate 307B is bonded to the first buffer plate 7A bonded to the first buffer plate 7A, the distance between the bonding surfaces between the first buffer plate 7A and the second buffer plate 307B is controlled within a predetermined range. Can do.

とくに、電極部材３０７を形成してから半導体素子３に接合するときは、接合材６ａに、半導体素子３に接合された第１の緩衝板７Ａに第２の緩衝板３０７Ｂを接合するときは、接合材６ｂに、当該接合材の厚みを保持する厚み保持材９が混入されているようにすれば、接合面間の距離をさらに確実に所定範囲に制御する事ができる。   In particular, when joining the semiconductor element 3 after forming the electrode member 307, when joining the second buffer plate 307B to the first buffer plate 7A joined to the semiconductor element 3 to the joining material 6a, If the thickness holding material 9 that holds the thickness of the bonding material is mixed in the bonding material 6b, the distance between the bonding surfaces can be controlled more reliably within a predetermined range.

なお、上記各実施の形態においては、スイッチング素子（トランジスタ）や整流素子（ダイオード）として機能する半導体素子３には、炭化ケイ素によって形成されたものを示したが、これに限られることはなく、一般的に用いられているケイ素（Ｓｉ）で形成されたものであってもよい。しかし、ケイ素よりもバンドギャップが大きい、いわゆるワイドギャップ半導体を形成できる炭化ケイ素や、窒化ガリウム系材料又はダイヤモンドを用いた時の方が、以下に述べるように本発明による効果をより一層発揮することができる。   In each of the above embodiments, the semiconductor element 3 functioning as a switching element (transistor) or a rectifying element (diode) is shown as being formed of silicon carbide, but is not limited thereto. It may be formed of silicon (Si) that is generally used. However, when using silicon carbide, gallium nitride-based material, or diamond that can form a so-called wide gap semiconductor having a larger band gap than silicon, the effects of the present invention can be further exhibited as described below. Can do.

ワイドバンドギャップ半導体によって形成されたスイッチング素子や整流素子（各実施の形態における半導体素子３）は、ケイ素で形成された素子よりも電力損失が低いため、スイッチング素子や整流素子における高効率化が可能であり、ひいては、電力用半導体装置１０、２１０、３１０（以下代表して１０のみ記す）の高効率化が可能となる。さらに、耐電圧性が高く、許容電流密度も高いため、スイッチング素子や整流素子の小型化が可能であり、これら小型化されたスイッチング素子や整流素子を用いることにより、電力用半導体装置１０も小型化が可能となる。また耐熱性が高いので、高温動作が可能であり、ヒートシンクの放熱フィンの小型化や、水冷部の空冷化も可能となるので、電力用半導体装置１０の一層の小型化が可能になる。   Since switching elements and rectifier elements (semiconductor elements 3 in each embodiment) formed of wide band gap semiconductors have lower power loss than elements formed of silicon, higher efficiency can be achieved in switching elements and rectifier elements. As a result, it is possible to increase the efficiency of the power semiconductor devices 10, 210, and 310 (hereinafter, only 10 is representatively described). Furthermore, since the withstand voltage is high and the allowable current density is high, the switching element and the rectifying element can be downsized. By using the downsized switching element and rectifying element, the power semiconductor device 10 is also small. Can be realized. Further, since the heat resistance is high, it is possible to operate at a high temperature, and it is possible to reduce the size of the heat dissipating fins of the heat sink and the air cooling of the water-cooled portion, so that the power semiconductor device 10 can be further reduced in size.

一方、上記のように高温動作する場合は停止・駆動時の温度差が大きくなり、さらに、高効率・小型化によって、単位体積当たりに扱う電流量が大きくなる。そのため経時的な温度変化や空間的な温度勾配が大きくなり、半導体素子と配線部材との熱応力も大きくなる可能性がある。しかし、本発明の各実施の形態に示すように、面どうし接合した２枚の応力緩衝板のうち半導体素子側の応力緩衝板は、半導体素子の線膨張係数に応じて材料を調整し、ワイヤのような配線部材側の応力緩衝板は、配線部材の線膨張係数に応じて材料を調整したので、各接合部での熱応力をそれぞれ適切に緩和されるので、ワイドバンドギャップ半導体の特性を活かして、小型化や高効率化を進めてもパワーサイクル寿命が長く、信頼性の高い電力用半導体装置１０を得ることが容易となる。つまり、本発明による効果を発揮することで、ワイドバンドギャップ半導体の特性を活かすことができるようになる。   On the other hand, when operating at a high temperature as described above, the temperature difference during stop and drive increases, and the amount of current handled per unit volume increases due to high efficiency and downsizing. Therefore, the temperature change with time and the spatial temperature gradient increase, and the thermal stress between the semiconductor element and the wiring member may also increase. However, as shown in each embodiment of the present invention, the stress buffer plate on the semiconductor element side of the two stress buffer plates bonded to each other is adjusted in material according to the linear expansion coefficient of the semiconductor element, and the wire Since the stress buffer plate on the wiring member side as described above is made by adjusting the material according to the coefficient of linear expansion of the wiring member, the thermal stress at each joint can be alleviated appropriately. Taking advantage of this, even if miniaturization and high efficiency are promoted, it is easy to obtain a power semiconductor device 10 having a long power cycle life and high reliability. That is, by exhibiting the effect of the present invention, the characteristics of the wide band gap semiconductor can be utilized.

なお、スイッチング素子及び整流素子の両方がワイドバンドギャップ半導体によって形成されていても、いずれか一方の素子がワイドバンドギャップ半導体によって形成されていてもよい。また、ワイヤやリードといった配線部材も異なる材料を使ってもよい。その場合、素子や配線部材の種類や材料に応じて、つまり、半導体素子と配線部材の線膨張係数に応じて半導体素子側の応力緩衝板と配線部材側の応力緩衝板の線膨張係数を変えるようにすれば、よりパワーサイクル寿命を向上させることができる。   Note that both the switching element and the rectifying element may be formed of a wide band gap semiconductor, or one of the elements may be formed of a wide band gap semiconductor. Different materials may also be used for the wiring members such as wires and leads. In that case, the linear expansion coefficient of the stress buffer plate on the semiconductor element side and the stress buffer plate on the wiring member side is changed according to the type and material of the element and the wiring member, that is, according to the linear expansion coefficient of the semiconductor element and the wiring member. By doing so, the power cycle life can be further improved.

１ 絶縁基板（１ｆ 回路面）、 ２ 回路パターン（２ａ，２ｂ、２ｒ）、 ３ 半導体素子、 ４ ワイヤ（配線部材）、 ６ はんだ（６ａ，６ｂ）、
７ 電極部材（７Ａ 第１の緩衝板、７Ｂ 第２の緩衝板）、 ８ スペーサ、 ９ ビーズ（厚み保持材）、 １０ （電力用）半導体装置 。
百位の数字は実施の形態による構成の相違を示す。 DESCRIPTION OF SYMBOLS 1 Insulation board | substrate (1f circuit surface), 2 Circuit pattern (2a, 2b, 2r), 3 Semiconductor element, 4 Wire (wiring member), 6 Solder (6a, 6b),
7 Electrode member (7A 1st buffer plate, 7B 2nd buffer plate), 8 spacer, 9 beads (thickness holding material), 10 (for power) semiconductor device.
The hundredth digit indicates a difference in configuration according to the embodiment.

Claims (11)

絶縁基板の回路面に一方の面が接合された半導体素子と、
前記半導体素子の他方の面に形成された電極に、接合材を介して、一方の面が接合された第１の緩衝板と、
前記第１の緩衝板の他方の面に、接合材を介して、一方の面が接合された第２の緩衝板と、
前記第２の緩衝板の他方の面に接合された配線部材と、を備え、
前記第１の緩衝板は、前記半導体素子の線膨張係数と前記配線部材の線膨張係数の間であって、前記半導体素子の線膨張係数との差が第１の所定値より小さい線膨張係数を有し、
前記第２の緩衝板は、前記第１の緩衝板の線膨張係数と前記配線部材の線膨張係数の間であって、前記配線部材の線膨張係数との差が、前記第１の所定値より大きな第２の所定値より小さい線膨張係数を有する、
ことを特徴とする半導体装置。 A semiconductor element having one surface bonded to the circuit surface of the insulating substrate;
A first buffer plate having one surface bonded to an electrode formed on the other surface of the semiconductor element via a bonding material;
A second buffer plate having one surface bonded to the other surface of the first buffer plate via a bonding material;
A wiring member joined to the other surface of the second buffer plate,
The first buffer plate is between the linear expansion coefficient of the semiconductor element and the linear expansion coefficient of the wiring member, and the difference between the linear expansion coefficient of the semiconductor element is smaller than a first predetermined value. Have
The second buffer plate is between the linear expansion coefficient of the first buffer plate and the linear expansion coefficient of the wiring member, and a difference between the linear expansion coefficient of the wiring member is the first predetermined value. Having a linear expansion coefficient smaller than the second larger predetermined value,
A semiconductor device. 前記配線部材と前記第２の緩衝板との接合は超音波接合によりなされ、
前記第１の所定値が５ｐｐｍ／Ｋであり、前記第２の所定値が１３ｐｐｍ／Ｋであることを特徴とする請求項１に記載の半導体装置。 The wiring member and the second buffer plate are joined by ultrasonic joining,
The semiconductor device according to claim 1, wherein the first predetermined value is 5 ppm / K, and the second predetermined value is 13 ppm / K. 前記半導体素子と前記第１の緩衝板とを接合する接合材の接合後の降伏応力は、前記第１の緩衝板と前記第２の緩衝板とを接合する接合材の接合後の降伏応力よりも小さいことを特徴とする請求項１または２に記載の半導体装置。   The yield stress after bonding of the bonding material for bonding the semiconductor element and the first buffer plate is based on the yield stress after bonding of the bonding material for bonding the first buffer plate and the second buffer plate. The semiconductor device according to claim 1, wherein the semiconductor device is also small. 前記第２の緩衝板の面積は、前記第１の緩衝板の面積よりも大きいことを特徴とする請求項１ないし３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein an area of the second buffer plate is larger than an area of the first buffer plate. 5. 前記第１の緩衝板は、前記第２の緩衝板に対して偏った位置に接合され、
前記第２の緩衝板の前記第１の緩衝板からはみ出た部分と、前記絶縁基板との間にスペーサが挿入されていることを特徴とする請求項４に記載の半導体装置。 The first buffer plate is bonded to a position biased with respect to the second buffer plate;
5. The semiconductor device according to claim 4, wherein a spacer is inserted between a portion of the second buffer plate that protrudes from the first buffer plate and the insulating substrate. 前記接合材に、当該接合材の厚みを保持する厚み保持材が混入されていることを特徴とする請求項５に記載の半導体装置。   6. The semiconductor device according to claim 5, wherein a thickness maintaining material for maintaining the thickness of the bonding material is mixed in the bonding material. 前記接合材がはんだであることを特徴とする請求項１ないし６のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the bonding material is solder. 前記接合材が焼結性の銀微粒子を含有する材料であることを特徴とする請求項１ないし６のいずれか１項に記載の半導体装置。   7. The semiconductor device according to claim 1, wherein the bonding material is a material containing sinterable silver fine particles. 前記半導体素子がワイドバンドギャップ半導体材料により形成されていることを特徴とする請求項１ないし８のいずれか１項に記載の半導体装置。   9. The semiconductor device according to claim 1, wherein the semiconductor element is made of a wide band gap semiconductor material. 前記ワイドバンドギャップ半導体材料は、炭化ケイ素、窒化ガリウム、またはダイヤモンド、のうちのいずれかであることを特徴とする請求項９に記載の半導体装置。   The semiconductor device according to claim 9, wherein the wide band gap semiconductor material is any one of silicon carbide, gallium nitride, and diamond. 請求項１ないし１０のいずれか１項に記載の半導体装置の製造方法であって、
前記第１の緩衝板の他方の面と前記第２の緩衝板の一方の面とを接合材を介して接合した電極部材を形成する工程と、
前記電極部材の前記第１の緩衝板側の面を、前記絶縁基板に接合された半導体素子の電極に接合材を介して接合する工程と、
前記電極部材の前記第２の緩衝板側の面に前記配線部材を接合する工程と、
を備えたことを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device according to any one of claims 1 to 10,
Forming an electrode member obtained by bonding the other surface of the first buffer plate and one surface of the second buffer plate via a bonding material;
Bonding the surface of the electrode member on the first buffer plate side to the electrode of the semiconductor element bonded to the insulating substrate via a bonding material;
Bonding the wiring member to the surface of the electrode member on the second buffer plate side;
A method for manufacturing a semiconductor device, comprising:
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