JP2017107937A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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JP2017107937A
JP2017107937A JP2015239402A JP2015239402A JP2017107937A JP 2017107937 A JP2017107937 A JP 2017107937A JP 2015239402 A JP2015239402 A JP 2015239402A JP 2015239402 A JP2015239402 A JP 2015239402A JP 2017107937 A JP2017107937 A JP 2017107937A
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wire
semiconductor element
semiconductor device
circuit pattern
power semiconductor
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Inventor
祥久 内田
Yoshihisa Uchida
祥久 内田
裕一郎 鈴木
Yuichiro Suzuki
裕一郎 鈴木
辰則 柳本
Tatsunori Yanagimoto
辰則 柳本
耕一 東久保
Koichi Higashikubo
耕一 東久保
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2015239402A priority Critical patent/JP2017107937A/en
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Abstract

PROBLEM TO BE SOLVED: To provide a small, high-power power semiconductor device capable of facilitating layout change of wiring, and of suppressing damages to a semiconductor element caused by the wiring.SOLUTION: A power semiconductor device includes: a circuit board that comprises a first circuit pattern and a second circuit pattern on an insulation substrate; and a switching semiconductor element and a return current semiconductor element arranged on the first circuit pattern. The return current semiconductor element is arranged at a position opposed to the second circuit pattern while interposing the switching semiconductor element. A surface electrode of the return current semiconductor element, a surface electrode of the switching semiconductor element, and the second circuit pattern are connected with a first wire. The surface electrode of the return current semiconductor element and the second circuit pattern are connected by a second wire having a lower electric resistivity than the first wire.SELECTED DRAWING: Figure 2

Description

本発明は、電力用半導体装置に関し、特に、金属ワイヤを用いて内部配線を形成した電力用半導体装置に関する。   The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device in which an internal wiring is formed using a metal wire.

スイッチング用半導体素子と、スイッチングにより生じた逆起電力を消費する還流用半導体素子を備えた電力用半導体装置では、小型化のために、スイッチング用半導体素子と還流用半導体素子を隣接するように基板上に配置し、スイッチング用半導体素子、還流用半導体素子、および基板のパターンの３点が、アルミニウムを主成分とする連続したワイヤで接続される。また、高出力化のために、アルミニウムを主成分とするワイヤに代えて、板状の銅配線や（特許文献１、２参照）、銅を主成分とするワイヤ（特許文献３参照）を用いて、配線抵抗を低減が図られている。   In a power semiconductor device including a switching semiconductor element and a return semiconductor element that consumes a back electromotive force generated by the switching, the substrate is arranged so that the switching semiconductor element and the return semiconductor element are adjacent to each other for miniaturization. The three points of the switching semiconductor element, the refluxing semiconductor element, and the substrate pattern are connected by a continuous wire mainly composed of aluminum. Further, in order to increase the output, instead of a wire mainly composed of aluminum, a plate-like copper wiring (see Patent Documents 1 and 2) or a wire mainly composed of copper (see Patent Document 3) is used. Thus, the wiring resistance is reduced.

特許第４４９９５７７号公報Japanese Patent No. 4499577 特開２０１４−２２５８０号公報JP 2014-22580 A 特開２０１３−４７７９号公報JP 2013-4779 A

しかしながら、板状の銅配線は、ワイヤ状の配線のように容易に変形しないため、基板パターンの変更や半導体素子の配置の変更に容易に対応できないという問題があった。また、１つの板状の銅配線で、スイッチング用半導体素子、還流用半導体素子、および基板パターンの３点を連続して接続する場合、これら３点の位置関係が重要となり、半導体素子の配置や銅配線の接続に高い精度が要求されるという問題もあった。   However, since the plate-like copper wiring is not easily deformed like the wire-like wiring, there is a problem that it cannot easily cope with the change of the substrate pattern and the change of the arrangement of the semiconductor elements. In addition, when three points of the switching semiconductor element, the refluxing semiconductor element, and the substrate pattern are connected continuously with one plate-like copper wiring, the positional relationship of these three points becomes important, and the arrangement of the semiconductor elements and There was also a problem that high accuracy was required for the connection of the copper wiring.

また、銅を主成分とするワイヤを用いた場合、アルミニウムを主成分とするワイヤに比べて硬くて変形しにくいため、接合に大きな荷重や超音波出力が必要となり、ワイヤボンディング時に半導体素子にダメージが入るという問題があった。   In addition, when using a wire containing copper as its main component, it is harder and more difficult to deform than a wire containing aluminum as its main component. Therefore, a large load and ultrasonic output are required for bonding, which damages the semiconductor elements during wire bonding. There was a problem of entering.

そこで、本発明は、配線のレイアウト変更が容易に行え、かつ配線による半導体素子へのダメージを抑えた、小型で高出力の電力用半導体装置の提供を目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a small-sized and high-output power semiconductor device in which wiring layout can be easily changed and damage to semiconductor elements due to wiring is suppressed.

本発明の一つの形態は、
電力用半導体装置であって、
絶縁基板の上に、第１回路パターンと第２回路パターンとを備えた回路基板と、
第１回路パターン上に配置されたスイッチング用半導体素子および還流用半導体素子と、を含み、
還流用半導体素子は、スイッチング用半導体素子を挟んで、第２回路パターンと対向する位置に配置され、
還流用半導体素子の表面電極とスイッチング用半導体素子の表面電極と第２回路パターンとが、第１ワイヤで接続され、
還流用半導体素子の表面電極と第２回路パターンとが、第１ワイヤより電気抵抗率が低い第２ワイヤで接続された電力用半導体装置である。
One aspect of the present invention is:
A power semiconductor device comprising:
A circuit board having a first circuit pattern and a second circuit pattern on an insulating substrate;
A switching semiconductor element and a refluxing semiconductor element disposed on the first circuit pattern,
The refluxing semiconductor element is disposed at a position facing the second circuit pattern across the switching semiconductor element,
The surface electrode of the semiconductor element for reflux, the surface electrode of the semiconductor element for switching, and the second circuit pattern are connected by the first wire,
In the power semiconductor device, the surface electrode of the semiconductor element for reflux and the second circuit pattern are connected by a second wire having an electrical resistivity lower than that of the first wire.

本発明にかかる電力用半導体装置では、最もループが長くなる還流用半導体素子と第２回路パターンとを直接接続するワイヤを、還流用半導体素子、スイッチング用半導体素子、および第２回路パターンを接続するワイヤより電気伝導率の低いワイヤとすることで、配線のレイアウト変更が容易に行え、かつ配線による半導体素子へのダメージを抑えた、ワイヤの自己発熱が低減された小型で高出力の電力用半導体装置を提供できる。   In the power semiconductor device according to the present invention, the return semiconductor element, the switching semiconductor element, and the second circuit pattern are connected to the wire that directly connects the return semiconductor element having the longest loop and the second circuit pattern. By using a wire with lower electrical conductivity than the wire, the layout of the wiring can be easily changed, and damage to the semiconductor elements due to the wiring is suppressed. A small, high-output power semiconductor with reduced self-heating of the wire Equipment can be provided.

本発明の実施の形態１にかかる電力用半導体装置の主要部の平面図である。It is a top view of the principal part of the semiconductor device for electric power concerning Embodiment 1 of this invention. 図１の電力用半導体装置をＩＩ−ＩＩ方向に見た場合の断面図である。It is sectional drawing at the time of seeing the power semiconductor device of FIG. 1 in the II-II direction. 従来の電力用半導体装置の主要部の平面図である。It is a top view of the principal part of the conventional power semiconductor device. 図３の電力用半導体装置をＩＶ−ＩＶ方向に見た場合の断面図である。FIG. 4 is a cross-sectional view of the power semiconductor device of FIG. 3 when viewed in the IV-IV direction. 他の従来の電力用半導体装置の主要部の平面図である。It is a top view of the principal part of other conventional power semiconductor devices. 本発明の実施の形態２にかかる電力用半導体装置の断面図である。It is sectional drawing of the semiconductor device for electric power concerning Embodiment 2 of this invention. 本発明の実施の形態３にかかる電力用半導体装置の断面図である。It is sectional drawing of the semiconductor device for electric power concerning Embodiment 3 of this invention.

実施の形態１．
図１は、全体が１００で表される、本発明の実施の形態１にかかる電力用半導体装置の主要部の平面図である。また、図２は、図１に示す電力用半導体装置１００の、ＩＩ−ＩＩ方向に見た場合の断面図である。 Embodiment 1 FIG.
FIG. 1 is a plan view of the main part of the power semiconductor device according to the first embodiment of the present invention, the whole being represented by 100. 2 is a cross-sectional view of the power semiconductor device 100 shown in FIG. 1 when viewed in the II-II direction.

電力用半導体装置１００は、回路基板１０を含む。回路基板１０は、表面と裏面を有する絶縁基板１５と、絶縁基板１５の表面上に形成された第１回路パターン１１、第２回路パターン１２、および第３回路パターン１３と、絶縁基板１５の裏面上に形成された裏面回路パターン１４とを含む。   The power semiconductor device 100 includes a circuit board 10. The circuit board 10 includes an insulating substrate 15 having a front surface and a back surface, a first circuit pattern 11, a second circuit pattern 12 and a third circuit pattern 13 formed on the surface of the insulating substrate 15, and a back surface of the insulating substrate 15. And a back surface circuit pattern 14 formed thereon.

絶縁基板１５は、例えばアルミナ等のセラミックからなる。第１回路パターン１１、第２回路パターン１２、第３回路パターン１３、および裏面回路パターン１４は、例えば銅からなる。   The insulating substrate 15 is made of ceramic such as alumina. The first circuit pattern 11, the second circuit pattern 12, the third circuit pattern 13, and the back circuit pattern 14 are made of copper, for example.

第１回路パターン１１の上には、接続材４４を介して還流用半導体素子としてダイオードチップ２０と、スイッチング用半導体素子としてＩＧＢＴチップ３０が固定されている。接続材４４には導電性の材料、例えば焼結性の銀粒子を含む材料が用いられる。   On the first circuit pattern 11, a diode chip 20 as a refluxing semiconductor element and an IGBT chip 30 as a switching semiconductor element are fixed via a connecting member 44. For the connecting material 44, a conductive material, for example, a material containing sinterable silver particles is used.

ダイオードチップ２０には、例えば厚さが１５０μｍのＳｉＣから形成されたダイオードが用いられ、表面（アノード）電極２１と裏面（カソード）電極（図示せず）を有する。裏面電極は、接続材４４を介して第１回路パターンに電気的に接続される。表面電極２１は、例えば厚さが５μｍで、アルミニウムを主成分とする材料からなる。   For example, a diode made of SiC having a thickness of 150 μm is used as the diode chip 20 and has a front surface (anode) electrode 21 and a back surface (cathode) electrode (not shown). The back electrode is electrically connected to the first circuit pattern via the connecting material 44. The surface electrode 21 has a thickness of 5 μm, for example, and is made of a material mainly composed of aluminum.

ＩＧＢＴチップ３０には、例えば厚さが１５０μｍのＳｉＣから形成されたＩＧＢＴが用いられ、裏面にコレクタ電極（図示せず）、表面にエミッタ電極３１と制御電極３２を有する。コレクタ電極は、接続材４４を介して第１回路パターン１１に電気的に接続される。エミッタ電極３１と制御電極３２は、例えば厚さが５μｍで、アルミニウムを主成分とする材料からなる。   For the IGBT chip 30, for example, an IGBT formed of SiC having a thickness of 150 μm is used, and has a collector electrode (not shown) on the back surface and an emitter electrode 31 and a control electrode 32 on the front surface. The collector electrode is electrically connected to the first circuit pattern 11 via the connecting material 44. The emitter electrode 31 and the control electrode 32 have a thickness of 5 μm, for example, and are made of a material mainly composed of aluminum.

図１に示すように、ＩＧＢＴチップ３０は、ダイオードチップ２０より第２回路パターン１２に近い位置に配置され、ダイオードチップ２０は、ＩＧＢＴチップ３０を挟んで、第２回路パターン１２に対向するように設けられる。   As shown in FIG. 1, the IGBT chip 30 is disposed closer to the second circuit pattern 12 than the diode chip 20, and the diode chip 20 faces the second circuit pattern 12 with the IGBT chip 30 interposed therebetween. Provided.

ダイオードチップ２０のアノード電極２１と、ＩＧＢＴチップ３０のエミッタ電極３１および第２回路パターン１２は、連続したアルミニウムワイヤ４１で接続される。アルミニウムワイヤ４１は、並列に複数本設けても良く、図１では２本設けられている。アルミニウムワイヤ４１は、アルミニウムを主成分とするワイヤで、必ずしもアルミニウムのみからなる必要はない。また、アルミニウムワイヤ４１の直径は、例えば約５００μｍである。   The anode electrode 21 of the diode chip 20, the emitter electrode 31 of the IGBT chip 30, and the second circuit pattern 12 are connected by a continuous aluminum wire 41. A plurality of aluminum wires 41 may be provided in parallel, and two aluminum wires 41 are provided in FIG. The aluminum wire 41 is a wire mainly composed of aluminum and does not necessarily need to be made of only aluminum. The diameter of the aluminum wire 41 is about 500 μm, for example.

具体的には、アルミニウムワイヤ４１は、一端がダイオードチップ２０のアノード電極２１にウェッジボンディングされ、中間部（端部と端部の間）でＩＧＢＴチップ３０のエミッタ電極３１にステッチボンディングされ、他端が第２回路パターン１２にウェッジボンディングされている。なお、ワイヤの両端のボンディングはウェッジボンディングで行われ、ワイヤをカットせずに次のボンド点に接続する中間部のステッチボンディングとは区別される。   Specifically, one end of the aluminum wire 41 is wedge-bonded to the anode electrode 21 of the diode chip 20, and stitch bonded to the emitter electrode 31 of the IGBT chip 30 at the intermediate portion (between the end portion). Are wedge-bonded to the second circuit pattern 12. Bonding at both ends of the wire is performed by wedge bonding, and is distinguished from intermediate stitch bonding that connects to the next bond point without cutting the wire.

また、アルミニウムワイヤ４１とは別に、ダイオードチップ２０のアノード電極２１と、第２回路パターン１２は、銅ワイヤ４２で直接接続される。銅ワイヤ４２は、並列に複数本設けても良く、図１では２本設けられている。銅ワイヤ４２は、銅を主成分とするワイヤで、必ずしも銅のみからなる必要はない。銅ワイヤ４２の直径は、例えば約５００μｍである。銅ワイヤ４２は、両端がウェッジボンディングでボンディングされている。   In addition to the aluminum wire 41, the anode electrode 21 of the diode chip 20 and the second circuit pattern 12 are directly connected by a copper wire 42. A plurality of copper wires 42 may be provided in parallel, and two copper wires 42 are provided in FIG. The copper wire 42 is a wire mainly composed of copper and does not necessarily need to be made of only copper. The diameter of the copper wire 42 is, for example, about 500 μm. Both ends of the copper wire 42 are bonded by wedge bonding.

更に、ＩＧＢＴチップ３０の制御電極３２と第３回路パターン１３とは、制御ワイヤ４３で接続されている。制御ワイヤ４３は、例えば直径が約２００μｍであり、アルミニウムを主成分とする材料からなる。   Further, the control electrode 32 of the IGBT chip 30 and the third circuit pattern 13 are connected by a control wire 43. The control wire 43 has a diameter of, for example, about 200 μm and is made of a material mainly composed of aluminum.

なお、電力用半導体装置１００では、回路基板１０の表面上に封止材が設けられ、回路パターンやチップ、ワイヤが封止されるが、図１、２（図３〜７も同様）では、構造を明確にするために、封止材は記載しない。   In the power semiconductor device 100, a sealing material is provided on the surface of the circuit board 10, and a circuit pattern, a chip, and a wire are sealed. In FIGS. In order to clarify the structure, the encapsulant is not described.

回路基板１０の裏面回路パターン１４は、例えばヒートシンク（図示せず）に回路基板１０を接合するために設けられている。   The back circuit pattern 14 of the circuit board 10 is provided, for example, for bonding the circuit board 10 to a heat sink (not shown).

図３、４は、比較例であり、図３は、全体が５００で表される従来の電力用半導体装置の主要部の平面図、図４は図３の電力用半導体装置５００をＩＶ−ＩＶ方向に見た場合の断面図である。図３、４中、図１、２と同一符合は、同一または相当箇所を示す。   FIGS. 3 and 4 are comparative examples. FIG. 3 is a plan view of the main part of a conventional power semiconductor device represented as a whole by 500, and FIG. 4 shows the power semiconductor device 500 of FIG. It is sectional drawing at the time of seeing in a direction. 3 and 4, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding portions.

図３、４に示す比較例では、第１回路パターン１１の上で、ダイオードチップ２０とＩＧＢＴチップ３０の位置が入れ替わり、ダイオードチップ２０がＩＧＢＴチップ３０より第２回路パターン１２に近い位置に配置されている。ＩＧＢＴチップ３０、ダイオードチップ２０、および第２回路パターン１２は、アルミニウムワイヤ４１の一端がＩＧＢＴチップ３０のエミッタ電極３１に、他端が第２回路パターン１２にそれぞれウェッジボンディングされ、中間部でダイオードチップ２０のアノード電極２１にステッチボンディングされている。   In the comparative example shown in FIGS. 3 and 4, the positions of the diode chip 20 and the IGBT chip 30 are switched on the first circuit pattern 11, and the diode chip 20 is disposed closer to the second circuit pattern 12 than the IGBT chip 30. ing. The IGBT chip 30, the diode chip 20, and the second circuit pattern 12 are each formed by wedge bonding one end of the aluminum wire 41 to the emitter electrode 31 of the IGBT chip 30 and the other end to the second circuit pattern 12, and the diode chip in the middle portion. The 20 anode electrodes 21 are stitch-bonded.

また、ＩＧＢＴチップ３０のエミッタ電極３１と、第２回路パターン１２は、他のアルミニウムワイヤ１４２で直接接続されている。さらに、制御電極３２と第３回路パターン１３も、アルミニウムワイヤ１４３で直接接続されている。アルミニウムワイヤ４１、１４２、１４３は、例えば直径が５００μｍで、アルミニウムが主成分のワイヤである。   Further, the emitter electrode 31 of the IGBT chip 30 and the second circuit pattern 12 are directly connected by another aluminum wire 142. Further, the control electrode 32 and the third circuit pattern 13 are also directly connected by the aluminum wire 143. The aluminum wires 41, 142, and 143 are, for example, wires having a diameter of 500 μm and aluminum as a main component.

比較例にかかる従来の電力用半導体装置５００では、ＩＧＢＴチップ３０からの電流がアルミニウムワイヤ４１を流れる場合は、ダイオードチップ２０を経由して第２回路パターン１２に流れ、アルミニウムワイヤ１４２を流れる場合は、ダイオードチップ２０を飛び越えて第２回路パターン１２に流れる。このため、アルミニウムワイヤ１４２が長くなり、ワイヤの自己発熱が大きくなってしまう。   In the conventional power semiconductor device 500 according to the comparative example, when the current from the IGBT chip 30 flows through the aluminum wire 41, the current flows through the diode chip 20 to the second circuit pattern 12 and flows through the aluminum wire 142. Then, it jumps over the diode chip 20 and flows to the second circuit pattern 12. For this reason, the aluminum wire 142 becomes long, and the self-heating of the wire becomes large.

図５は、全体が６００で表される、比較例にかかる他の電力用半導体装置の断面図であり、図３、４と同一符合は、同一または相当箇所を示す。電力用半導体装置６００では、ＩＧＢＴチップ３０のエミッタ電極３１とダイオードチップ２０のアノード電極２１、ダイオードチップ２０のアノード電極２１と第２回路パターン１２の間が、それぞれアルミニウムワイヤ１４２で接続されている。２つのアルミニウムワイヤ１４２の間は、ダイオードチップ２０のアノード電極２１を介して電気的に接続されている。他の構造は、電力用半導体装置５００と同じである。   FIG. 5 is a cross-sectional view of another power semiconductor device according to a comparative example, indicated as a whole by 600, and the same reference numerals as in FIGS. 3 and 4 indicate the same or corresponding portions. In the power semiconductor device 600, the emitter electrode 31 of the IGBT chip 30 and the anode electrode 21 of the diode chip 20, and the anode electrode 21 of the diode chip 20 and the second circuit pattern 12 are connected by aluminum wires 142. The two aluminum wires 142 are electrically connected via the anode electrode 21 of the diode chip 20. Other structures are the same as those of the power semiconductor device 500.

電力用半導体装置６００では、電力用半導体装置５００に比較してアルミニウムワイヤ１４２の長さは短縮できるが、アノード電極２１の厚みが薄いため、アノード電極２１の面方向の配線抵抗が大きく、アノード電極２１が発熱してしまうという問題がある。   In the power semiconductor device 600, the length of the aluminum wire 142 can be shortened as compared with the power semiconductor device 500, but since the anode electrode 21 is thin, the wiring resistance in the surface direction of the anode electrode 21 is large, and the anode electrode There is a problem that 21 will generate heat.

これに対して、本発明の電力用半導体装置１００では、従来の電力用半導体装置５００、６００とは、ダイオードチップ２０とＩＧＢＴチップ３０の位置を逆に配置し、エミッタ電極３１と第２回路パターン１２との距離を短くし、ループ長を縮めることでアルミニウムワイヤ４１の発熱を低減することが可能になる。   On the other hand, in the power semiconductor device 100 of the present invention, the positions of the diode chip 20 and the IGBT chip 30 are reversed from those of the conventional power semiconductor devices 500 and 600, and the emitter electrode 31 and the second circuit pattern are arranged. It is possible to reduce the heat generation of the aluminum wire 41 by shortening the distance to 12 and shortening the loop length.

また、還流電流はアルミニウムワイヤ４１の他にも、アルミニウムワイヤ４１より電機抵抗率の低い銅ワイヤ４２を介してダイオードチップ２０に流れるため、アルミニウムワイヤ１４１を用いた場合よりも、発熱を軽減することができる。   In addition to the aluminum wire 41, the reflux current flows to the diode chip 20 via the copper wire 42 having a lower electrical resistivity than the aluminum wire 41. Therefore, heat generation can be reduced as compared with the case where the aluminum wire 141 is used. Can do.

一般に、ＩＧＢＴチップ３０のエミッタ電極３１の直下には、トランジスタが形成されている。このため、エミッタ電極３１へのワイヤボンディング時に、このトランジスタが破壊されて、チップ特性の劣化や機能不全が発生する場合があった。   In general, a transistor is formed immediately below the emitter electrode 31 of the IGBT chip 30. For this reason, at the time of wire bonding to the emitter electrode 31, this transistor may be destroyed, resulting in deterioration of chip characteristics and malfunction.

これに対して、ダイオードチップ２０のアノード電極２１の直下には、トランジスタが形成されないため、ワイヤボンディング時のダメージ耐量は高くなる。本発明の電力用半導体装置１００では、ダイオードチップ２０にのみ銅ワイヤ４２をワイヤボンディングし、ＩＧＢＴチップ３０には、アルミニウムワイヤ４１をステッチボンディングするため、エミッタ電極３１へのワイヤボンディング工程で、エミッタ電極３１の直下のトランジスタを破壊することによる、チップ特性の劣化を防止できる。   On the other hand, since no transistor is formed immediately below the anode electrode 21 of the diode chip 20, damage resistance during wire bonding is increased. In the power semiconductor device 100 of the present invention, the copper wire 42 is wire-bonded only to the diode chip 20, and the aluminum wire 41 is stitch-bonded to the IGBT chip 30. Therefore, in the wire bonding process to the emitter electrode 31, the emitter electrode It is possible to prevent deterioration of chip characteristics due to destruction of the transistor directly below 31.

また、ボンディングワイヤでの発熱を抑制するために、ボンディングワイヤの本数を増やして１本あたりに流れる電流を小さくし、電流密度を低減する手段がある。しかしながら、ボンディングワイヤの本数を増やすためには、アノード電極２１とエミッタ電極３１の面積を大きくして、複数のボンディングワイヤを接続する領域を確保する必要があり、チップ面積が大きくなるという問題が発生する。   Further, in order to suppress the heat generation in the bonding wires, there is a means for increasing the number of bonding wires to reduce the current flowing per one and reducing the current density. However, in order to increase the number of bonding wires, it is necessary to increase the areas of the anode electrode 21 and the emitter electrode 31 to secure a region for connecting a plurality of bonding wires, resulting in a problem that the chip area increases. To do.

これに対して、本発明の実施の形態１にかかる電力用半導体装置１００では、ボンディングワイヤの材料に、アルミニウムに代えて銅を用いるため、ボンディングワイヤの本数を増やすことなく、ボンディングワイヤでの発熱を抑制できる。   On the other hand, in the power semiconductor device 100 according to the first embodiment of the present invention, since copper is used instead of aluminum as the material of the bonding wire, heat is generated in the bonding wire without increasing the number of bonding wires. Can be suppressed.

また、制御ワイヤ４３を、主配線であるアルミニウムワイヤ４１や銅ワイヤ４２よりも細くすることで、制御用電極のサイズを小さくでき、ＩＧＢＴチップ３０のコストを低減することができる。なお、制御ワイヤ４３には信号電流が流れるだけで、主配線のように大電流が流れないため、ワイヤの直径を小さくしても制御ワイヤ４３の発熱が問題になることはない。   Moreover, by making the control wire 43 thinner than the aluminum wire 41 and the copper wire 42 which are main wirings, the size of the control electrode can be reduced, and the cost of the IGBT chip 30 can be reduced. In addition, since only a signal current flows through the control wire 43 and a large current does not flow unlike the main wiring, heat generation of the control wire 43 does not become a problem even if the wire diameter is reduced.

また、スイッチング用半導体素子よりもワイヤボンディング時のダメージ耐量が高い還流用半導体素子のみに、銅ワイヤを接合するため、ワイヤ接合時のダメージを軽減できる。   In addition, since the copper wire is bonded only to the refluxing semiconductor element having a higher damage tolerance during wire bonding than the switching semiconductor element, damage during wire bonding can be reduced.

さらに、内部配線に銅板を用いる場合は、半導体素子の配置がずれた場合に、銅板の形状を加工しなおす必要がったが、本発明の実施の形態１にかかる電力用半導体装置１００では、内部配線に配線自由度の高いワイヤを用いるため、半導体素子の搭載位置がずれた場合でも、容易に対応が可能となる。   Furthermore, when using a copper plate for the internal wiring, it is necessary to rework the shape of the copper plate when the arrangement of the semiconductor elements is shifted, but in the power semiconductor device 100 according to the first embodiment of the present invention, Since a wire having a high degree of freedom in wiring is used for the internal wiring, it is possible to easily cope with a case where the mounting position of the semiconductor element is shifted.

なお、本発明の実施の形態１にかかる電力用半導体装置１００では、スイッチング用半導体素子としてＩＧＢＴチップ３０を用いる場合について述べたが、スイッチング用半導体素子はこれに限定されるものではなく、例えばＭＯＳＦＥＴやバイポーラトランジスタ等を用いても構わない。ＭＯＳＦＥＴでは、ソース電極、ドレイン電極が、それぞれＩＧＢＴのエミッタ電極、コレクタ電極に対応する。   In the power semiconductor device 100 according to the first embodiment of the present invention, the case where the IGBT chip 30 is used as the switching semiconductor element has been described. However, the switching semiconductor element is not limited to this, for example, a MOSFET Alternatively, a bipolar transistor or the like may be used. In the MOSFET, the source electrode and the drain electrode correspond to the emitter electrode and the collector electrode of the IGBT, respectively.

また、本発明の実施の形態１では、ＩＧＢＴチップ３０のエミッタ電極３１と、ダイオードチップ２０のアノード電極２１が、アルミニウムを主材料とする厚さ５μｍの膜からなる場合について述べたが、これに限定されるものではない。エミッタ電極３１やアノード電極２１の膜厚は、ワイヤボンディングが可能な膜厚であれば、他の膜厚でも良い。   In the first embodiment of the present invention, the case where the emitter electrode 31 of the IGBT chip 30 and the anode electrode 21 of the diode chip 20 are made of a film having a thickness of 5 μm mainly composed of aluminum has been described. It is not limited. The film thicknesses of the emitter electrode 31 and the anode electrode 21 may be other film thicknesses as long as wire bonding is possible.

また、本発明の実施の形態１では、半導体素子がＳｉＣからなる場合について述べたが、これに限定されるものではなく、Ｓｉ、ＧａＮ、ＧａＡｓ、ＩｎＧａＡｓ、ダイヤモンド等の材料を用いても構わない。特に、ＳｉＣ、ＧａＮ、ダイヤモンドなどの、Ｓｉよりもバンドギャップが大きいワイドバンドギャップ半導体を用いる場合、小型化や高温動作化が期待でき、その利点を活かすために電流密度を上げる必要があるため、本発明はより効果的なものとなる。   In the first embodiment of the present invention, the case where the semiconductor element is made of SiC has been described. However, the present invention is not limited to this, and materials such as Si, GaN, GaAs, InGaAs, and diamond may be used. . In particular, when using a wide band gap semiconductor having a larger band gap than Si, such as SiC, GaN, diamond, etc., it can be expected to be downsized and operated at high temperature, and it is necessary to increase the current density in order to take advantage of the advantages, The present invention becomes more effective.

また、本発明の実施の形態１では、セラミックからなる絶縁基板１５に銅の回路パターン１１、１２、１３を形成した回路基板１０について述べたが、これに限定されるものではなく、銅の回路パターンで樹脂絶縁層を挟んだ回路基板や、回路パターンをアルミニウムで形成した回路基板を用いても良い。   In the first embodiment of the present invention, the circuit board 10 in which the copper circuit patterns 11, 12, 13 are formed on the insulating substrate 15 made of ceramic has been described. However, the present invention is not limited to this. A circuit board in which a resin insulating layer is sandwiched between patterns or a circuit board in which a circuit pattern is formed of aluminum may be used.

また、本発明の実施の形態１では、焼結性の銀粒子を含む接続材４４を用いたが、これに限定されるものではなく、はんだ、銀フィラーを混合したエポキシ樹脂、導電性接着剤など、導電性材料からなり、半導体素子と回路パターンが接続できる材料であれば他の材料を用いても構わない。   Further, in Embodiment 1 of the present invention, the connection material 44 containing sinterable silver particles is used, but the present invention is not limited to this, and an epoxy resin mixed with solder and silver filler, a conductive adhesive Other materials may be used as long as they are made of a conductive material and can connect the semiconductor element and the circuit pattern.

また、本発明の実施の形態１では、主配線に、直径５００μｍのアルミニウムワイヤ４１と銅ワイヤ４２を用いたが、これに限定されるものではなく、電極パッドのサイズやワイヤに流れる電流量に応じて、直径が３００〜５００μｍのワイヤを用いても構わない。   In the first embodiment of the present invention, the aluminum wire 41 and the copper wire 42 having a diameter of 500 μm are used for the main wiring. However, the present invention is not limited to this, and the size of the electrode pad and the amount of current flowing through the wire are not limited thereto. Accordingly, a wire having a diameter of 300 to 500 μm may be used.

実施の形態２．
図６は、全体が２００で表される、本発明の実施の形態２にかかる電力用半導体装置の断面図である。図６中、図２と同一符合は、同一または相当箇所を示す。 Embodiment 2. FIG.
FIG. 6 is a cross-sectional view of the power semiconductor device according to the second embodiment of the present invention, indicated as a whole by 200. In FIG. 6, the same reference numerals as those in FIG. 2 denote the same or corresponding parts.

電力用半導体装置２００では、ダイオードチップ１２０がＳｉから形成され、アノード電極１２１には、膜厚が５μｍの、銅を主成分とするめっき層が用いられている。アルミニウムワイヤ４１と銅ワイヤ４２の一端は、この銅めっきからなるアノード電極１２１の上にボンディングされている。他の構成は、実施の形態１にかかる電力用半導体装置１００と同じである。   In the power semiconductor device 200, the diode chip 120 is made of Si, and the anode electrode 121 uses a plating layer having a film thickness of 5 μm as a main component. One end of the aluminum wire 41 and the copper wire 42 is bonded onto the anode electrode 121 made of this copper plating. Other configurations are the same as those of the power semiconductor device 100 according to the first embodiment.

Ｓｉからなるダイオードチップ１２０は、ＳｉＣからなるダイオードチップ２０と比較してヤング率が小さいため素子が破壊されやすく、特に銅ワイヤ４２をワイヤボンディングする際にダメージが生じやすい。本発明の実施の形態２にかかる電力用半導体装置２００では、アノード電極１２１の材料を、アルミニウムを主成分とする材料から、銅を主成分とする材料に変えることにより、アノード電極１２１のヤング率が高くなり、ワイヤボンディング時のダメージを防止できる。   The diode chip 120 made of Si has a Young's modulus smaller than that of the diode chip 20 made of SiC, so that the element is easily destroyed, and damage is particularly likely to occur when the copper wire 42 is wire-bonded. In the power semiconductor device 200 according to the second embodiment of the present invention, the Young's modulus of the anode electrode 121 is changed by changing the material of the anode electrode 121 from a material containing aluminum as a main component to a material containing copper as a main component. Can be prevented and damage during wire bonding can be prevented.

また、ダイオードチップ２０はＩＧＢＴチップ３０に比べてワイヤボンディング時のダメージ耐量が高いため、ＩＧＢＴチップ３０のエミッタ電極３１を銅めっきで形成してダメージを抑制するより、めっき厚を薄くできる。   In addition, since the diode chip 20 has a higher resistance to damage during wire bonding than the IGBT chip 30, the plating thickness can be made thinner than when the emitter electrode 31 of the IGBT chip 30 is formed by copper plating to suppress damage.

なお、本発明の実施の形態２では、ダイオードチップ１２０のアノード電極１２１を、銅めっきで形成する場合について述べたが、アノード電極１２１の材料は、これに限定されるものではない。例えば、銅、ニッケルなど、アルミニウムよりもヤング率の高い他の材料を用いても構わない。また、アノード電極１２１の形成方法も、スパッタ法、蒸着法、ＣＶＤ法、電解めっき法、無電解めっき法など、適宜選択しても良い。   In the second embodiment of the present invention, the anode electrode 121 of the diode chip 120 is formed by copper plating. However, the material of the anode electrode 121 is not limited to this. For example, other materials having a higher Young's modulus than aluminum, such as copper and nickel, may be used. The formation method of the anode electrode 121 may be appropriately selected from a sputtering method, a vapor deposition method, a CVD method, an electrolytic plating method, an electroless plating method, and the like.

また、本発明の実施の形態２では、ダイオードチップ１２０をシリコンから形成する場合について述べたが、これに限定されるものではなく、ＳｉＣなどのシリコンよりもチップダメージが生じにくい材料からダイオードチップ１２０を形成した場合でも、銅を主成分とするアノード電極１２１を用いることにより、銅ワイヤをウェッジボンディングする際のチップダメージをより抑制できる。   In the second embodiment of the present invention, the diode chip 120 is formed from silicon. However, the present invention is not limited to this, and the diode chip 120 is made of a material that is less susceptible to chip damage than silicon such as SiC. Even when formed, the chip damage when the copper wire is wedge-bonded can be further suppressed by using the anode electrode 121 mainly composed of copper.

実施の形態３．
図７は、全体が３００で表される、本発明の実施の形態３にかかる電力用半導体装置の断面図である。図７中、図２と同一符合は、同一または相当箇所を示す。 Embodiment 3 FIG.
FIG. 7 is a cross-sectional view of the power semiconductor device according to the third embodiment of the present invention, indicated as a whole by 300. In FIG. 7, the same reference numerals as those in FIG. 2 denote the same or corresponding parts.

電力用半導体装置３００では、ダイオードチップ２０のアノード電極２１の上に、Ｎｉ／Ａｕめっき膜（図示しない）が形成されている。Ｎｉ／Ａｕめっき膜の上に、はんだからなる緩衝板接合材４５を介して、線膨張係数がダイオードチップ２０に近くなるように膜厚比が調整されたＣＩＣ（Ｃｕ／Ｆｅ−Ｎｉ合金／Ｃｕの積層）の緩衝板２２が設けられている。アルミニウムワイヤ４１および銅ワイヤ４２の一端は、この緩衝板２２の上にワイヤボンディングされる。他の構成は、本発明の実施の形態１にかかる電力用半導体装置１００と同じである。   In the power semiconductor device 300, a Ni / Au plating film (not shown) is formed on the anode electrode 21 of the diode chip 20. A CIC (Cu / Fe—Ni alloy / Cu with a film thickness ratio adjusted so that the linear expansion coefficient is close to that of the diode chip 20 on the Ni / Au plating film via the buffer plate bonding material 45 made of solder. Buffer layer 22 is provided. One end of the aluminum wire 41 and the copper wire 42 is wire-bonded on the buffer plate 22. Other configurations are the same as those of the power semiconductor device 100 according to the first embodiment of the present invention.

本発明の実施の形態３では、アノード電極２１の上に緩衝板２２を搭載することで、銅ワイヤ４２を直接アノード電極２１にウェッジボンディングする場合と比較して、ウェッジボンディング時のチップダメージをより抑制することができる。アノード電極２１上には、はんだ接合が可能となるようにＮｉ／Ａｕめっきが設けられるが、上述のように、ＩＧＢＴチップ３０は下方にトランジスタを有するため、エミッタ電極３１の表面に凹凸ができるのに対して、ダイオードチップ２０では、下方にトランジスタを有さないため、アノード電極２１の表面は平坦になる。表面に凹凸があると、アルミニウムの粒径が不均一になり、前処理のエッチング時に局所的にアルミニウム膜が浸食され、不良が起こりやすい。電力用半導体装置３００では、ダイオードチップ２０のアノード電極２１は平坦であるため、このような浸食による不良は発生せず、ＩＧＢＴチップ３０へのめっき処理に比較して歩留りは高くなる。   In Embodiment 3 of the present invention, by mounting the buffer plate 22 on the anode electrode 21, chip damage during wedge bonding is further reduced as compared with the case where the copper wire 42 is directly wedge bonded to the anode electrode 21. Can be suppressed. Ni / Au plating is provided on the anode electrode 21 so that solder bonding is possible. However, as described above, the IGBT chip 30 has a transistor below, so that the surface of the emitter electrode 31 can be uneven. On the other hand, since the diode chip 20 does not have a transistor below, the surface of the anode electrode 21 becomes flat. If the surface has irregularities, the particle size of the aluminum becomes non-uniform, and the aluminum film is locally eroded during the pretreatment etching, which tends to cause defects. In the power semiconductor device 300, since the anode electrode 21 of the diode chip 20 is flat, such a defect due to erosion does not occur, and the yield is higher than the plating process on the IGBT chip 30.

また、緩衝板２２をＣＩＣ板にすることで、緩衝板２２の線膨張係数をダイオードチップ２０に近づけることができる。これにより、ダイオードチップ２０と緩衝板２２との線膨張係数の違いにより生じる熱応力に起因した緩衝板接合材４５の劣化等を防止できる。   Further, by making the buffer plate 22 a CIC plate, the linear expansion coefficient of the buffer plate 22 can be made closer to the diode chip 20. Thereby, the deterioration of the buffer plate bonding material 45 due to the thermal stress caused by the difference in the linear expansion coefficient between the diode chip 20 and the buffer plate 22 can be prevented.

なお、本発明の実施の形態３では、緩衝板２２が、線膨張係数がダイオードチップ２０に近くなるように板厚比が調整されたＣＩＣである場合について述べたが、Ｆｅ、Ｎｉ、Ｍｏ、Ｃｏ、Ｗなどの線膨張係数がＣｕよりも小さい金属との積層板、あるいは合金により線膨張係数を調整された緩衝板を用いても良い。   In the third embodiment of the present invention, the buffer plate 22 is a CIC whose thickness ratio is adjusted so that the linear expansion coefficient is close to that of the diode chip 20, but Fe, Ni, Mo, A laminated plate with a metal having a linear expansion coefficient such as Co or W smaller than Cu, or a buffer plate whose linear expansion coefficient is adjusted with an alloy may be used.

また、本発明の実施の形態３では、緩衝板接合材４５がはんだである場合について述べたが、これに限定されるものではない。例えば緩衝板接合材４５に焼結性の銀粒子を含む材料を用いた場合、ダイオードチップ２０と緩衝板２２との線膨張係数の違いによって生じる熱応力に対して耐性が上がるため、緩衝板２２に、より線膨張係数の大きいＣｕ板などを用いることも可能となる。   In Embodiment 3 of the present invention, the case where the buffer plate bonding material 45 is solder has been described. However, the present invention is not limited to this. For example, when a material containing sinterable silver particles is used for the buffer plate bonding material 45, resistance to thermal stress caused by a difference in linear expansion coefficient between the diode chip 20 and the buffer plate 22 is increased. In addition, it is possible to use a Cu plate having a larger linear expansion coefficient.

１０ 回路基板、１１ 第１回路パターン、１２ 第２回路パターン、１３ 第３回路パターン、１４ 裏面回路パターン、１５ 絶縁基板、２０ ダイオードチップ、２１ アノード電極、２２ 緩衝板、３０ ＩＧＢＴチップ、３１ エミッタ電極、３２ 制御電極、４１ アルミニウムワイヤ、４２ 銅ワイヤ、４３ 制御ワイヤ、４４ 接続材、４５ 緩衝板接合材、１００ 電力用半導体装置。   DESCRIPTION OF SYMBOLS 10 Circuit board, 11 1st circuit pattern, 12 2nd circuit pattern, 13 3rd circuit pattern, 14 Back surface circuit pattern, 15 Insulation board, 20 Diode chip, 21 Anode electrode, 22 Buffer board, 30 IGBT chip, 31 Emitter electrode , 32 control electrode, 41 aluminum wire, 42 copper wire, 43 control wire, 44 connecting material, 45 buffer plate bonding material, 100 power semiconductor device.

Claims (10)

電力用半導体装置であって、
絶縁基板の上に、第１回路パターンと第２回路パターンとを備えた回路基板と、
該第１回路パターン上に配置されたスイッチング用半導体素子および還流用半導体素子と、を含み、
該還流用半導体素子は、該スイッチング用半導体素子を挟んで、該第２回路パターンと対向する位置に配置され、
該還流用半導体素子の表面電極と該スイッチング用半導体素子の表面電極と該第２回路パターンとが、第１ワイヤで接続され、
該還流用半導体素子の表面電極と該第２回路パターンとが、該第１ワイヤより電気抵抗率が低い第２ワイヤで接続された電力用半導体装置。 A power semiconductor device comprising:
A circuit board having a first circuit pattern and a second circuit pattern on an insulating substrate;
A switching semiconductor element and a refluxing semiconductor element disposed on the first circuit pattern,
The refluxing semiconductor element is disposed at a position facing the second circuit pattern across the switching semiconductor element,
The surface electrode of the semiconductor element for reflux, the surface electrode of the semiconductor element for switching, and the second circuit pattern are connected by a first wire,
A power semiconductor device in which a surface electrode of the refluxing semiconductor element and the second circuit pattern are connected by a second wire having an electrical resistivity lower than that of the first wire. 第１ワイヤは、アルミニウムまたはアルミニウムを主成分とする材料からなることを特徴とする請求項１に記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein the first wire is made of aluminum or a material mainly composed of aluminum. 第２ワイヤは、銅または銅を主成分とする材料からなることを特徴とする請求項１に記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein the second wire is made of copper or a material containing copper as a main component. 上記第１ワイヤは、上記還流用半導体素子の表面電極と上記第２回路パターンに、それぞれの端部がウェッジボンディングされ、上記スイッチング用半導体素子の表面電極に、該それぞれの端部に挟まれた該第１ワイヤの中間部がステッチボンディングされたことを特徴とする請求項１〜３のいずれかに記載の電力用半導体装置。   The first wire is wedge bonded to the surface electrode of the refluxing semiconductor element and the second circuit pattern, and is sandwiched between the surface electrode of the switching semiconductor element. The power semiconductor device according to claim 1, wherein an intermediate portion of the first wire is stitch-bonded. 上記スイッチング用半導体素子は、更に、制御ワイヤが接続された制御用表面電極を含み、該制御ワイヤは、上記第１ワイヤと同じ材料からなり、該第１ワイヤの直径の２分の１以下の直径を有することを特徴とする請求項１〜４のいずれかに記載の電力用半導体装置。   The switching semiconductor element further includes a control surface electrode to which a control wire is connected, and the control wire is made of the same material as the first wire, and is less than or equal to half the diameter of the first wire. The power semiconductor device according to claim 1, wherein the power semiconductor device has a diameter. 上記還流用半導体素子の表面電極は、ニッケルまたは銅を主成分とし、膜厚が５μｍ以上であることを特徴とする請求項１〜５のいずれかに記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein the surface electrode of the semiconductor element for reflux is mainly composed of nickel or copper and has a thickness of 5 μm or more. 上記還流用半導体素子の表面電極の上に、緩衝板接合層を介して緩衝板が接合されており、上記第１ワイヤおよび上記第２ワイヤの一端は、該緩衝板に接続されたことを特徴とする請求項１〜６のいずれかに記載の電力用半導体装置。   A buffer plate is bonded onto the surface electrode of the semiconductor element for reflux via a buffer plate bonding layer, and one end of the first wire and the second wire is connected to the buffer plate. A power semiconductor device according to claim 1. 上記緩衝板は、ＣＩＣ（Ｃｕ／Ｆｅ−Ｎｉ合金／Ｃｕの積層）構造であることを特徴とする請求項７に記載の電力用半導体装置。   8. The power semiconductor device according to claim 7, wherein the buffer plate has a CIC (Cu / Fe—Ni alloy / Cu laminated) structure. 上記還流用半導体素子は、ワイドバンドギャップ半導体であることを特徴とする請求項１〜８のいずれかに記載の電力用半導体装置。   9. The power semiconductor device according to claim 1, wherein the semiconductor element for reflux is a wide band gap semiconductor. 上記ワイドギャップ半導体は、炭化ケイ素、窒化ガリウム系材料、およびダイヤモンドからグループから選択される材料であることを特徴とする請求項９に記載の電力用半導体装置。   10. The power semiconductor device according to claim 9, wherein the wide gap semiconductor is a material selected from the group consisting of silicon carbide, a gallium nitride-based material, and diamond.
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