JP2011146513A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2011146513A JP2011146513A JP2010005912A JP2010005912A JP2011146513A JP 2011146513 A JP2011146513 A JP 2011146513A JP 2010005912 A JP2010005912 A JP 2010005912A JP 2010005912 A JP2010005912 A JP 2010005912A JP 2011146513 A JP2011146513 A JP 2011146513A
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Abstract
【課題】コスト増加を招くことなく、ICチップの作動により発生する熱等を効率的に排除可能にする。
【解決手段】本発明に係る半導体装置1は、基板10と、前記基板10上に固定されるICチップ3と、前記基板10の表面に配される導電体11と、前記基板10の表面及び前記導電体11を被覆すると共に、前記ICチップ3の固定面に対応する部分に前記導電体11を露出させる開口部17が形成されたソルダーレジスト12と、前記固定面と前記開口部17による前記導電体11の露出部18とに接触する接着剤5とを備える。
【選択図】図1
【解決手段】本発明に係る半導体装置1は、基板10と、前記基板10上に固定されるICチップ3と、前記基板10の表面に配される導電体11と、前記基板10の表面及び前記導電体11を被覆すると共に、前記ICチップ3の固定面に対応する部分に前記導電体11を露出させる開口部17が形成されたソルダーレジスト12と、前記固定面と前記開口部17による前記導電体11の露出部18とに接触する接着剤5とを備える。
【選択図】図1
Description
本発明は、プリント基板上にIC(Integrated Circuit)チップが搭載されてなる半導体装置に関し、特に熱等の不要な要素を排除するための技術に関するものである。
現在、各種電気機器において、所望の機能を提供するICチップがプリント基板上に固定された状態で利用されている。前記ICチップは、その作動に伴い、熱、電気的ノイズ等を発生させるため、上記のような構成の半導体装置には、放熱機能、ノイズ抑制機能等を備えることが要求される。
図5は、従来の半導体装置101の構成を例示している。前記半導体装置101は、プリント基板102上にAgペースト等の接着剤105を介してICチップ103が固定されると共に、樹脂等のパッケージング104により全体が被覆されてなるものである。前記プリント基板102は、基板110の表面に、配線としての導電体111が配されると共に、絶縁層としてのソルダーレジスト112が被覆されてなる。前記導電体111は、前記基板110を貫通する複数のビア115を介して、前記ICチップ103が固定された面からその反対側の面まで延設され、外部デバイスとの接続ポイントである半田ボール113と接続している。前記ICチップ103は、半導体等からなるサブストレート120上に、所定の機能を提供する機能素子群121が固定されてなる。前記プリント基板102と前記ICチップ103とは、ボンディングワイヤ106を介して電気信号の送受が可能に接続されている。前記ソルダーレジスト112は、前記ICチップ103が固定された面において、前記ボンディングワイヤ106のボンディングポイント114等の接続ポイントを除く全ての部分で前記導電体110を被覆している。
また、特許文献1において、3層のBGA(Ball Grid Array)パッケージが、上下のトレース間に設けられたVSSプレーンと、外周部分の上下面に設けられたVSSトレースと、前記VSSプレーンと上下面の前記VSSトレースとを電気的及び熱的に接続するビアとを備える構成が開示されている。これにより、内層に配置された前記VSSプレーンが低インピーダンスの電流経路を構成するとされている。
また、特許文献2において、絶縁基材の内部に、放熱用の上部金属層と放熱用の下部金属層との2層を互いに離隔して配置し、前記絶縁基材の裏面側に放熱金属層を配置し、前記上部金属層は、凹所の金属メッキ層に接続され、前記上部金属層と前記下部金属層とが金属メッキ層が施されたインナーバイアホールにより接続された構成が開示されている。これにより、ヒートシンクを用いずに放熱性、耐湿性を向上させることができるとされている。
また、特許文献3において、ICチップをプリント回路基板の第1の導体部及び第2の導体部上に、これらを跨ぐように搭載し、前記両導体部をそれぞれ接地させる構成が開示されている。これにより、アナログ回路からの電流とデジタル回路からの電流とがサブストレートを通じて混在することによる不具合を防止できるとされている。
上記図5に示す従来の半導体装置101においては、前記接着剤105が前記ソルダーレジスト112と前記サブストレート120との間に介在されている。一般的な前記ソルダーレジスト112は、熱伝導性及び電気伝導性が低い性質を有するものである。従って、上記半導体装置101においては、前記機能素子部121の作動により発生する熱、電気的ノイズ等の排除要素130が、前記ソルダーレジスト112に遮断され、前記サブストレート120内に蓄積されることとなる。このように、従来の半導体装置101においては、放熱性能、ノイズ抑制性能等の面で改善の余地がある。
また、上記特許文献1,2に記載の構成は、放熱性等を向上させるために多層構造を採用したものであり、製造工程、部品の増加に伴うコスト増加の問題がある。また、上記特許文献3に記載の構成は、アナログ用及びデジタル用の導体部を個別に用意し、これらの導体部をそれぞれチップエッジよりも外側まで延設するものである。このような構造においては、熱ストレスによりパッケージ内に発生する応力により、配線クラックが生ずる可能性があり、また放熱性の面で改善の余地が大きいものである。
本発明は、上記課題の解決を目的に含むものであり、本発明の一態様は、基板と、前記基板上に固定されるICチップと、前記基板の表面に配される導電体と、前記基板の表面及び前記導電体を被覆すると共に、前記ICチップの固定面に対応する部分に前記導電体を露出させる開口部が形成されたソルダーレジストと、前記固定面と前記開口部による前記導電体の露出部とに接触する接着剤とを備える半導体装置である。
上記態様によれば、前記ソルダーレジストの塗布範囲のうち前記ICチップの固定面に対応する部分が、前記開口部により前記導電体が露出した状態となる。そして、前記接着剤は、前記開口部を介して前記ICチップと前記導電体とに直接接触した状態となる。即ち、前記ICチップから前記導電体までの熱的な伝導性が、前記ソルダーレジストの不介在により、良好となる。これにより、前記ICチップに発生した熱は、前記接着剤及び前記導電体を介して外部に効率的に排除される。また、前記ICチップのサブストレート、前記接着剤等に用いられる材質を選択することにより、前記ICチップから前記導電体までを熱的にだけでなく、電気的にも接続することができ、このような構成によれば、前記ICチップに生じた電気的ノイズ等を排除することも可能となる。
本発明によれば、コスト増加を招くことなく、ICチップの作動により発生する熱等の不要な要素を効率的に排除することが可能となる。
実施の形態1
図1は、本発明の実施の形態1に係る半導体装置1の構成を示している。前記半導体装置1は、プリント基板2上にICチップ3が搭載されると共に、樹脂等のパッケージング4により被覆されてなるものである。本実施の形態においては、基板10の表面に銅箔等の前記導電体11が配されると共に絶縁膜であるソルダーレジスト12が塗布されてなるプリント基板2上に、接着剤としてAgペースト5を用いて前記ICチップ3が固定される。また、前記プリント基板2と前記ICチップ3とは、複数のボンディングワイヤ6により電気信号の送受が可能に接続される。
図1は、本発明の実施の形態1に係る半導体装置1の構成を示している。前記半導体装置1は、プリント基板2上にICチップ3が搭載されると共に、樹脂等のパッケージング4により被覆されてなるものである。本実施の形態においては、基板10の表面に銅箔等の前記導電体11が配されると共に絶縁膜であるソルダーレジスト12が塗布されてなるプリント基板2上に、接着剤としてAgペースト5を用いて前記ICチップ3が固定される。また、前記プリント基板2と前記ICチップ3とは、複数のボンディングワイヤ6により電気信号の送受が可能に接続される。
前記プリント基板2は、前記基板10、前記導電体11、前記ソルダーレジスト12、及び半田ボール13を含んで構成される。
前記基板10は、フェノール係樹脂等から構成される板状の部材である。前記基板10には、その両面を貫通する複数のビア15が形成されている。
前記導電体11は、銅箔等から構成され、主に電気配線として使用される。前記導電体11は、前記ビア11を介して前記ICチップ3が固定された面からその反対側の面まで延設され、前記半田ボール13と接続されている。
前記ソルダーレジスト12は、エポキシ系樹脂等の絶縁性、感光性等を有する合成樹脂膜である。前記ソルダーレジスト12は、前記導電体11と前記ボンディングワイヤ6とのボンディングポイント14等の電気的接続ポイント(パッド、ランド)を除く部分を被覆する。また、本実施の形態に係る前記ソルダーレジスト12は、前記ICチップ3の固定面に対応する部分に開口部17を有している。前記開口部17により、前記導電体11の一部が露出部18となる。
前記半田ボール13は、前記半導体装置1が搭載される外部デバイスとの電気的接続ポイントである。前記半田ボール13は、前記導電体11と接続する。
前記ICチップ3は、サブストレート20、及び機能素子群21を含んで構成される。
本実施の形態に係る前記サブストレート20は、単結晶シリコン等の半導体から構成される板状の部材である。前記サブストレート20上に、所定の機能を提供する前記機能素子群21が固定される。前記機能素子群21は、各種半導体素子の組み合わせ等から構成される。前記サブストレート20の前記機能素子群21が固定された面とは反対側の面(固定面)が、前記Agペースト5により前記プリント基板2に固定される。
また、図1において、前記サブストレート20内に排除要素30が示されている。前記排除要素30は、前記機能素子群21の作動により生ずる熱、電気的ノイズ等の不要な要素をイメージ的に表現したものである。
図2及び図3は、前記プリント基板2の前記ICチップ3を搭載する前の状態、及び前記開口部17の形状を例示している。図2及び図3において、前記ソルダーレジスト12、前記開口部17、前記露出部18(前記導電体11)、前記ボンディングポイント14、前記ビア15、及び前記ICチップ3の固定箇所25が示されている。両図が示すように、前記開口部17の形状としては、四角形状、円形状等の各種形状が許容される。前記開口部17の存在により、前記導電体11の一部が前記露出部18として露出した状態となる。本実施の形態においては、前記露出部18は、前記開口部17の全範囲に渡って前記導電体11が敷き詰められた状態(ベタ状態)となっている。また、前記開口部17(前記露出部18)は、前記固定箇所25の範囲内に収まっている。
図4は、前記固定箇所25に前記ICチップ3を搭載した際の断面構造を模式的に示している。同図が示すように、前記ICチップ3は、前記ソルダーレジスト12上に前記Agペースト5を介して固定される。この時、前記Agペースト5は、前記開口部17に充填されることにより、前記ICチップ3の前記サブストレート20と前記導電体11の前記露出部18とに接触する。また、前記露出部18を含む前記導電体11は、前記基板10に形成された前記ビア15を介して前記半田ボール13(図1参照)に接続されている。更に、前記サブストレート20の固定面(前記Agペースト5と接触する面)には、ショットキーバリアの発生を抑制する表面処理が施されている。前記表面処理としては、粗面加工、又は前記固定面に金を蒸着させ電極を形成する処理が好適である。
上記構成により、図1に示すように、前記機能素子群21の作動により前記サブストレート20内に生じた前記排除要素30は、前記サブストレート20→前記Agペースト5→前記露出部18(前記導電体11)→前記ビア15(前記導電体11)→前記半田ボール13→外部へと伝達し、排除される。
また、本実施の形態においては、前記露出部18が前記ベタ状態となっているため、熱伝導性及び電気伝導性が高く、前記排除要素30を外部へ放出する効果が高い。また、前記開口部17(前記露出部18)は、前記固定箇所25(図2又は図3参照)の範囲内に収まっているため、前記ICチップ3の固定時に前記Agペースト5等にクラックが発生する可能性が低い。更に、本実施の形態においては、前記サブストレート20と前記半田ボール13とが電気的に接続されていると共に、前記サブストレート20の前記固定面に前記ショットキーバリアの発生を抑制する表面処理が施されていることにより、前記排除要素30に熱だけでなく電気的ノイズが含まれている場合であっても、ショットキーバリアによる影響が軽減され、効果的にその排除が行われる。
尚、本発明は、上記実施の形態に限られるものではなく、趣旨を逸脱しない範囲で適宜変更することが可能なものである。例えば、上記実施の形態においては、前記プリント基板2としてBGA型の構成を示したが、本発明はこれに限定するものではない。また、上記実施の形態においては、前記サブストレート20から前記半田ボール13までが熱的にだけでなく電気的にも接続された構成を示したが、熱的にだけ接続する構成であってもよい。
1 半導体装置
2 プリント基板
3 ICチップ
5 Agペースト
6 ボンディングワイヤ
10 基板
11 導電体
12 ソルダーレジスト
13 半田ボール
14 ボンディングポイント
15 ビア
17 開口部
18 露出部
20 サブストレート
21 機能素子群
30 排除要素
2 プリント基板
3 ICチップ
5 Agペースト
6 ボンディングワイヤ
10 基板
11 導電体
12 ソルダーレジスト
13 半田ボール
14 ボンディングポイント
15 ビア
17 開口部
18 露出部
20 サブストレート
21 機能素子群
30 排除要素
Claims (7)
- 基板と、
前記基板上に固定されるICチップと、
前記基板の表面に配される導電体と、
前記基板の表面及び前記導電体を被覆すると共に、前記ICチップの固定面に対応する部分に前記導電体を露出させる開口部が形成されたソルダーレジストと、
前記固定面と前記開口部による前記導電体の露出部とに接触する接着剤と、
を備える半導体装置。 - 前記露出部を含む前記導電体は、前記基板に形成されたビアを介して、前記ICチップが固定された面とは反対側の面に設けられた外部接続用導電体と熱的に接続する、
請求項1に記載の半導体装置。 - 前記露出部は、前記開口部の全範囲に渡って前記導電体が敷き詰められた状態である、
請求項1又は2に記載の半導体装置。 - 前記開口部は、前記固定面の範囲内に収まる、
請求項1〜3のいずれか1つに記載の半導体装置。 - 前記接着剤は、導電性を有し、
前記固定面は、半導体から構成され、ショットキーバリアの発生を抑制する表面処理が施されている、
請求項1〜4のいずれか1つに記載の半導体装置。 - 前記表面処理は、粗面加工である、
請求項5に記載の半導体装置。 - 前記表面処理は、前記固定面に金を蒸着させ電極を形成する処理である、
請求項5に記載の半導体装置。
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US13/004,992 US20110169165A1 (en) | 2010-01-14 | 2011-01-12 | Semiconductor device |
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JP2015156463A (ja) * | 2014-01-14 | 2015-08-27 | 新光電気工業株式会社 | 配線基板及び半導体パッケージ |
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WO2022004178A1 (ja) * | 2020-07-02 | 2022-01-06 | ソニーセミコンダクタソリューションズ株式会社 | インターポーザ、回路装置、インターポーザの製造方法、および回路装置の製造方法 |
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