JP2010516047A - 電気メッキによる垂直素子形成の方法および素子構造 - Google Patents
電気メッキによる垂直素子形成の方法および素子構造 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H51/00—Electromagnetic relays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S205/00—Electrolysis: processes, compositions used therein, and methods of preparing the compositions
- Y10S205/924—Electrolytic coating substrate predominantly comprised of specified synthetic resin
- Y10S205/925—Synthetic resin is electrically conductive
Abstract
【解決手段】具体的には、まずテンプレート構造が形成され、該構造は、基板と、該基板の表面に配置された個別金属導体パッドと、個別金属導体パッドおよび基板を覆うインターレベル誘電体(ILD)層と、ILD層を貫通して個別金属導体パッド上に延びる金属穴構造とを含む。次に、テンプレート構造中に、IDL層を貫通し個別の金属導体パッド上に延びる垂直孔が形成される。しかる後、電気メッキにより垂直孔中に垂直導電構造が形成され、該電気メッキは、電気メッキ電流を金属穴構造を通して個別金属導体パッドに印加することにより実施される。望ましくは、該テンプレート構造は、複数の個別金属導体パッド、複数の金属穴構造、および複数の垂直導電構造を形成するための複数の垂直孔を含む。
【選択図】図3
Description
本出願は、本出願と同日付で出願され本出願と同一の譲受人に譲渡された、同時係属中の米国特許出願、名称「MEMORY STORAGE DEVICES COMPRISING DIFFERENT FERROMAGNETIC MATERIAL LAYERS,AND METHODS OF MAKING AND USING THE SAME(異なる強磁性材料層を含む記憶素子、並びにその作製および使用方法)」(代理人整理番号YOR20060192US1−SSMP19771)および「FORMATION OF NANOSTRUCTURES COMPRISING COMPOSITIONALLY MODULATED FERROMAGNETIC LAYERS BY PULSED ECD(パルス電圧ECDによる、組成変調された強磁性層を含むナノ構造の形成)」(代理人整理番号YOR20060194US1−SSMP19769)に関連する。上記の米国特許出願の全内容は、全ての目的のため参照によって本出願に組み込まれる。
Claims (15)
- 基板、前記基板の上面に配置された個別金属導体パッド、前記基板と前記金属導体パッドとの両方を覆うインターレベル誘電体(ILD)層、および前記ILD層を貫通して前記個別金属導体パッド上に延びる金属穴構造、を含むテンプレート構造を形成するステップと、
前記テンプレート構造に垂直孔を形成するステップと、
電気メッキによって前記垂直孔の中に垂直導電構造を形成するステップと、
を含む方法であって、
前記垂直孔は前記ILD層を貫通して前記個別金属導体パッド上に延びており、
前記電気メッキは、前記金属穴構造を通して前記個別金属導体パッドに電気メッキ電流を印加することにより実施される、
方法。 - 前記垂直導電構造は一つ以上の強磁性金属を含む、請求項1に記載の方法。
- 前記垂直導電構造は、交互する異なった強磁性金属の層を含む、請求項2に記載の方法。
- 前記テンプレート構造は、複数の個別金属導体パッドを含み、その各々は自体に向け延びる金属穴構造を有し、後工程での電気メッキによる複数の垂直導電構造形成のため、複数の垂直孔が前記ILD層中に形成される、請求項1に記載の方法。
- 前記テンプレート構造は、前記IDL層の上面に配置されて前記金属穴構造の全てに電気的に接続された金属層パターンをさらに含み、前記電気メッキの過程において、前記電気メッキ電流が、前記金属層パターンと前記金属穴構造とを介して前記複数の個別金属導体パッドに印加することができるようにされた、請求項4に記載の方法。
- 前記複数の垂直孔の形成の前に、前記金属層パターンが、
前記ILD層の前記上面に、全面的金属層を付着させるステップと、
前記全面金属層をパターニングし、各々の除去部が前記複数の個別金属導体パッドの一つの上に垂直的に位置整列するようにして、前記金属層中に複数の除去部を生成するステップと、
を使って形成される、請求項5に記載の方法。 - 前記複数の垂直孔を形成する前に前記金属層パターンの上に絶縁層を形成し、後工程で形成される前記垂直孔が、前記絶縁層と前記ILD層を貫通して延びるようにするステップをさらに含む、請求項6に記載の方法。
- 前記金属層パターンは、端部域を除き、前記絶縁層によって完全に覆われ、前記電気メッキの過程で、前記電気メッキ電流が前記端部域を介して前記金属層パターンに印加される、請求項7に記載の方法。
- 前記電気メッキ、および過成長メッキ金属除去の後、前記ILD層の前記上面から、前記金属層パターンおよび前記絶縁層の両方を除去するステップをさらに含む、請求項7に記載の方法。
- 前記金属層パターンおよび前記絶縁層の除去の後、前記ILD層の前記上面の上に複数の表面金属コンタクトを形成し、前記複数の垂直導電構造へのアクセスを設けるステップをさらに含む、請求項9に記載の方法。
- 基板と、前記基板の上面に配置された個別金属導体パッドと、前記基板および前記少なくとも一つの金属導体パッドの両方を覆うインターレベル誘電体(ILD)層と、前記ILD層を貫通して前記個別金属導体パッド上に延びる金属穴構造と、前記ILD層を貫通して前記個別金属導体パッド上に延びる垂直導電構造とを含む、素子構造。
- 前記垂直導電構造は一つ以上の強磁性金属を含む、請求項11に記載の素子構造。
- 前記垂直導電構造は、交互する異なった強磁性金属の層を含む、請求項12に記載の素子構造。
- 複数の個別金属導体パッドを含み、その各々が自体に延びる金属穴構造および垂直導電構造を有する、請求項11に記載の素子構造。
- 前記ILD層の上面に配置された複数の表面金属コンタクトをさらに含み、前記複数の表面金属コンタクトの各々は、前記複数の垂直導電構造の一つに電気的に接続されている、請求項14に記載の素子構造。
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US11/620,497 | 2007-01-05 | ||
US11/620,497 US7608538B2 (en) | 2007-01-05 | 2007-01-05 | Formation of vertical devices by electroplating |
PCT/US2008/000003 WO2008085805A1 (en) | 2007-01-05 | 2008-01-02 | Formation of vertical devices by electroplating |
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JP2010516047A true JP2010516047A (ja) | 2010-05-13 |
JP5284981B2 JP5284981B2 (ja) | 2013-09-11 |
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JP2009544909A Expired - Fee Related JP5284981B2 (ja) | 2007-01-05 | 2008-01-02 | 電気メッキによる垂直素子形成の方法 |
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US (2) | US7608538B2 (ja) |
EP (1) | EP2100319B1 (ja) |
JP (1) | JP5284981B2 (ja) |
KR (1) | KR101054841B1 (ja) |
CN (1) | CN101652826B (ja) |
WO (1) | WO2008085805A1 (ja) |
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US20080166874A1 (en) | 2008-07-10 |
US7608538B2 (en) | 2009-10-27 |
EP2100319A4 (en) | 2013-04-03 |
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KR20090096453A (ko) | 2009-09-10 |
US20090294989A1 (en) | 2009-12-03 |
CN101652826B (zh) | 2013-01-02 |
JP5284981B2 (ja) | 2013-09-11 |
US8247905B2 (en) | 2012-08-21 |
EP2100319A1 (en) | 2009-09-16 |
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WO2008085805A1 (en) | 2008-07-17 |
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