JP2010250859A - 同期メモリの読出しデータ収集 - Google Patents
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- JP2010250859A JP2010250859A JP2010168125A JP2010168125A JP2010250859A JP 2010250859 A JP2010250859 A JP 2010250859A JP 2010168125 A JP2010168125 A JP 2010168125A JP 2010168125 A JP2010168125 A JP 2010168125A JP 2010250859 A JP2010250859 A JP 2010250859A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
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- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
【解決手段】先ずグレイコードカウントのシーケンスをメモリに書き込み、次いで単一のバーストでそれを読み出すことで実現する。コントローラは、コマンドが発行された時点から一定間隔で読出しバーストをサンプリングし、周回遅延を決定する。簡単な真理値表の検索により、通常読出しに対する最適のDQSイネーブルのタイミングを決定する。通常の読出し動作中、イネーブルされたDQS信号の第1のポジティブエッジを使用して、コマンドが発行されるたびにイネーブルされたカウンタをサンプリングすることが好ましい。カウンタサンプルが変化した場合、これはタイミングの変動が生じたことを示すが、DQSイネーブル信号を調整して変動を補正し、DQSプリアンブルの中央に合わせた位置に保つことができる。
【選択図】図1
Description
本発明は、一般に、同期メモリおよび関連するメモリコントローラに関するものである。より詳細には、本発明は、双方向データバスおよび双方向データストローブ信号を使用する、メモリコントローラと同期メモリとの間の読出しおよび書込みデータの制御および転送に関するものである。
22 DDR-SDRAM
24 単方向バス
26 双方向バス
28 双方向接続
30 読出し遅延決定回路
32 DQSイネーブル回路
34 DQS信号
40 0度クロック
42、44、46、48、50 グレイコードカウンタ
52 コマンドシーケンス
54 DQS
56 データ信号DQ
58 DQS90
60 DQ0
62 DQ1
64 count_en
66 READコマンド
69 ポストアンブル
70 第1の例
72 第2の例
80 DQSイネーブル
82 反転されたDQS90入力
83 DQS TB1
84、86、92、94、96、104、106、108、110、112、114、116、144、146 フリップフロップ
154 SRフリップフロップ
101 マルチプレクサ選択入力mux_sel
100、102、170、171 マルチプレクサ
120 RTLクロック入力
140 CLK(N)クロック入力
148 dqs_enable_ff出力
150 dqs_disable_ff出力
152 ANDゲート
156 dqs_enable_i
158 DQS入力
172 dqsb_i
173 dqs_i
160 DQS#入力
196 変動出力
198 変動出力
200 コマンドシーケンス
201、203 READコマンド
202 グレイコードカウンタCK
Claims (10)
- 同期メモリコントローラにおいてデータストローブ入力をイネーブルにするための方法であって、
データストローブイネーブル値およびデータストローブエッジ値を決定するステップと、
読出しコマンドの発行があればカウンタを開始するステップと、
前記カウンタの出力が前記データストローブイネーブル値に達したとき、前記データストローブ入力をイネーブルにするステップと、
データストローブエッジサンプルを提供するために、前記データストローブ入力のエッジを使用して前記カウンタの出力をラッチするステップと、
前記データストローブエッジサンプルが前記データストローブエッジ値と異なっている場合、
前記データストローブエッジサンプルと前記データストローブエッジ値との間の差を前記データストローブイネーブル値に加えるステップと、
前記データストローブエッジ値を前記データストローブエッジサンプルに置き換えるステップと
を有する方法。 - 前記カウンタの出力をラッチする前記ステップは、前記データストローブ入力のイネーブルに続いて、前記データストローブ入力の第1エッジで前記カウンタの出力をラッチするステップを有する請求項1に記載の方法。
- 前記カウンタの出力をラッチする前記ステップは、前記データストローブ入力の立ち上がりエッジで前記カウンタの出力をラッチするステップを有する請求項1に記載の方法。
- 前記データストローブ入力の4倍の周波数で前記カウンタをクロックするステップをさらに有する請求項1に記載の方法。
- 同期メモリコントローラにおいてデータストローブ入力をイネーブルにするための方法であって、
データストローブイネーブルチと第1データストローブエッジ値と第2データストローブエッジ値とを決定するステップと、
前記データストローブイネーブル値によって決定された時間での読出しコマンドの発行に続いて前記データストローブ入力をイネーブルにするステップと、
第1データストローブエッジサンプルを提供するために、前記データストローブ入力のエッジを使用してクロックをラッチするステップと、
第2データストローブエッジサンプルを提供するために、前記データストローブ入力のエッジを使用して前記クロックの位相シフトバージョンをラッチするステップと、
前記第1データストローブエッジサンプルが前記第1データストローブエッジ値と異なっている場合、または、前記第2データストローブエッジサンプルが前記第2データストローブエッジ値と異なっている場合、
変動を補正するために前記データストローブイネーブル値を調整するステップと、
前記第1データストローブエッジ値を前記第1データストローブエッジサンプルに置き換えるとともに、前記第2データストローブエッジ値を前記第2データストローブエッジサンプルに置き換えるステップと
を有する方法。 - 前記クロックおよび前記クロックの前記位相シフトバージョンは、前記データストローブ入力のイネーブルに続いて、前記データストローブ入力の第1エッジでラッチされる請求項5に記載の方法。
- 前記クロックおよび前記クロックの前記位相シフトバージョンは、前記データストローブ入力の立ち上がりエッジでラッチされる請求項5に記載の方法。
- 前記クロックの前記位相シフトバージョンの周波数は、前記クロックの周波数と実質的に等しい請求項5に記載の方法。
- 前記クロックの前記位相シフトバージョンは、前記クロックに対して90度位相シフトされている請求項8に記載の方法。
- 前記クロックの前記位相シフトバージョンの周波数と前記クロックの周波数とは、前記データストローブ入力の周波数と実質的に等しい請求項8に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/477,659 US7685393B2 (en) | 2006-06-30 | 2006-06-30 | Synchronous memory read data capture |
US11/477,659 | 2006-06-30 |
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JP2009516832A Division JP5657888B2 (ja) | 2006-06-30 | 2007-05-07 | 同期メモリの読出しデータ収集 |
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JP2010250859A true JP2010250859A (ja) | 2010-11-04 |
JP5241780B2 JP5241780B2 (ja) | 2013-07-17 |
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JP2009516832A Expired - Fee Related JP5657888B2 (ja) | 2006-06-30 | 2007-05-07 | 同期メモリの読出しデータ収集 |
JP2010168125A Expired - Fee Related JP5241780B2 (ja) | 2006-06-30 | 2010-07-27 | 同期メモリの読出しデータ収集 |
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JP2009516832A Expired - Fee Related JP5657888B2 (ja) | 2006-06-30 | 2007-05-07 | 同期メモリの読出しデータ収集 |
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Country | Link |
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US (3) | US7685393B2 (ja) |
EP (1) | EP2036090B1 (ja) |
JP (2) | JP5657888B2 (ja) |
KR (1) | KR101374417B1 (ja) |
CN (1) | CN101479802B (ja) |
AT (1) | ATE532182T1 (ja) |
TW (1) | TWI453754B (ja) |
WO (1) | WO2008000059A1 (ja) |
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JP5657888B2 (ja) | 2015-01-21 |
ATE532182T1 (de) | 2011-11-15 |
US8086813B2 (en) | 2011-12-27 |
US20110016282A1 (en) | 2011-01-20 |
JP2009541868A (ja) | 2009-11-26 |
KR20090035508A (ko) | 2009-04-09 |
JP5241780B2 (ja) | 2013-07-17 |
US20080005518A1 (en) | 2008-01-03 |
EP2036090B1 (en) | 2011-11-02 |
CN101479802A (zh) | 2009-07-08 |
TWI453754B (zh) | 2014-09-21 |
EP2036090A4 (en) | 2009-08-12 |
CN101479802B (zh) | 2011-12-28 |
TW200805392A (en) | 2008-01-16 |
EP2036090A1 (en) | 2009-03-18 |
US7685393B2 (en) | 2010-03-23 |
WO2008000059A1 (en) | 2008-01-03 |
KR101374417B1 (ko) | 2014-03-17 |
USRE46819E1 (en) | 2018-05-01 |
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