JP2010062457A - Diamond field-effect transistor and method of manufacturing the same - Google Patents

Diamond field-effect transistor and method of manufacturing the same Download PDF

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JP2010062457A
JP2010062457A JP2008228654A JP2008228654A JP2010062457A JP 2010062457 A JP2010062457 A JP 2010062457A JP 2008228654 A JP2008228654 A JP 2008228654A JP 2008228654 A JP2008228654 A JP 2008228654A JP 2010062457 A JP2010062457 A JP 2010062457A
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surface layer
diamond
oxygen
effect transistor
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JP5095562B2 (en
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Makoto Kakazu
誠 嘉数
Kenji Ueda
研二 植田
Hiroyuki Kageshima
博之 影島
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Nippon Telegraph and Telephone Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable and practical diamond FET which has a high maximum operating temperature and large drain current density, and can withstand a large-power operation for a long period of time. <P>SOLUTION: A diamond crystal 1 is prepared and irradiated with hydrogen plasma (represented as H) in the reactor of a microwave CVD device to form a surface layer 2 containing hydrogen (Fig.1(a)). In a partial area on the first surface layer 2, metal films 31 and 32 of 600 nm in thickness are vapor-deposited spatially apart from each other. They serve as a source electrode 31 and a drain electrode 32. An Al thin film 4 is vapor-deposited spatially apart from each other between the source electrode 31 and drain electrode 32 (Fig.1(c)). The Al thin film 4 serves as a gate electrode 4. Then NO<SB>2</SB>is supplied to a sample to form a second surface layer 5 on the first surface layer 2 (Fig.1(d)). A protective layer 6 is deposited on the second surface layer 5 so as to cover the entire second surface layer 5 which is exposed (Fig.1(e)). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、ダイヤモンド電界効果トランジスタ及びその作製方法に関し、より詳細には、室温以上でも安定な表面層を有するダイヤモンド電界効果トランジスタ及びその作製方法に関する。   The present invention relates to a diamond field effect transistor and a manufacturing method thereof, and more particularly to a diamond field effect transistor having a surface layer that is stable even at room temperature or higher and a manufacturing method thereof.

ダイヤモンド半導体は、半導体最大の絶縁耐圧、熱伝導性を有するばかりでなく、電子や正孔の移動度やドリフト速度も高く、もしダイヤモンド・トランジスタが実用化できれば、既存の半導体の性能を遥かに超える、最高の性能を持つ高周波電力トランジスタが実用可能になる（非特許文献１参照）。   Diamond semiconductors not only have the highest withstand voltage and thermal conductivity of semiconductors, but also have high electron and hole mobility and drift speed. If diamond transistors can be put to practical use, they will far exceed the performance of existing semiconductors. Thus, a high-frequency power transistor having the best performance can be put into practical use (see Non-Patent Document 1).

図６に、従来の水素終端ダイヤモンド電界効果トランジスタ（ＦＥＴ）の作製工程を示す。ダイヤモンド結晶層１を用意し、そのダイヤモンド結晶層１をＣＶＤリアクター内で水素プラズマに曝し、ダイヤモンド表面を水素ラジカル（Ｈで表す）で終端する（図６（ａ））。そのようにして水素を含む表面層２を形成する。次に、水素を含む表面層２上の一部の領域に、金薄膜３１、３２を空間的に分離して蒸着する（図６（ｂ））。それが各々ソース電極３１、ドレイン電極３２になる。次に、ソース電極３１とドレイン電極３２との間に、空間的に分離して、Ａｌ薄膜４を蒸着する。これがゲート電極４になる（図６（ｃ））。次に、試料に二酸化炭素（ＣＯ２）又は水（Ｈ２Ｏ）を吸着させ、ＣＯ２又はＨ２Ｏを含む表面層５５を形成する。（図６（ｄ））。このデバイスを動作させる場合の配線を図６（ｆ）に示す。 FIG. 6 shows a manufacturing process of a conventional hydrogen-terminated diamond field effect transistor (FET). A diamond crystal layer 1 is prepared, the diamond crystal layer 1 is exposed to hydrogen plasma in a CVD reactor, and the diamond surface is terminated with hydrogen radicals (represented by H) (FIG. 6A). Thus, the surface layer 2 containing hydrogen is formed. Next, the gold thin films 31 and 32 are spatially separated and deposited in a partial region on the surface layer 2 containing hydrogen (FIG. 6B). These become the source electrode 31 and the drain electrode 32, respectively. Next, the Al thin film 4 is deposited in a spatially separated manner between the source electrode 31 and the drain electrode 32. This becomes the gate electrode 4 (FIG. 6C). Next, carbon dioxide (CO 2 ) or water (H 2 O) is adsorbed on the sample to form a surface layer 55 containing CO 2 or H 2 O. (FIG. 6 (d)). The wiring for operating this device is shown in FIG.

このような従来技術に基づき作製したダイヤモンドＦＥＴ（ゲート長１０μｍ）のドレイン電流電圧特性を図７（ａ）に示す。従来技術によるダイヤモンドＦＥＴの特性は、ゲート電圧−３Ｖにおける最大ドレイン電流密度は５ｍＡ／ｍｍであった。   FIG. 7A shows drain current-voltage characteristics of a diamond FET (gate length: 10 μm) manufactured based on such a conventional technique. The characteristic of the diamond FET according to the prior art is that the maximum drain current density at a gate voltage of −3 V is 5 mA / mm.

嘉数 誠 外、「ダイヤモンドＭＥＳＦＥＴの高周波特性」、応用物理、２００４年、第７３巻、第3号、ｐｐ．３６３−３６７Makoto Kaji, “High Frequency Characteristics of Diamond MESFET”, Applied Physics, 2004, Vol. 73, No. 3, pp. 363-367

しかしながら、図８に、従来の水素終端ダイヤモンドＦＥＴのゲート電圧−３Ｖでのドレイン電流密度の試料温度特性を示すように、昇温すると、室温から１４０℃にかけてドレイン電流密度は徐々に減少するという課題があった。これは、表面層２の二酸化炭素（ＣＯ２）又は水（Ｈ２Ｏ）が蒸発してしまうためで、昇温によって一度減少したドレイン電流密度は、再び室温に戻してもドレイン電流密度は元に戻らない。以下の記述では、ドレイン電流密度が急激に減少する試料温度をＴＣと呼ぶことにする。 However, FIG. 8 shows that the drain current density gradually decreases from room temperature to 140 ° C. when the temperature rises, as shown in the sample temperature characteristics of the drain current density at a gate voltage of −3 V of the conventional hydrogen-terminated diamond FET. was there. This is because carbon dioxide (CO 2 ) or water (H 2 O) in the surface layer 2 is evaporated, and the drain current density once reduced by the temperature rise is the original even if the drain current density is returned to room temperature again. Do not return to. In the following description, it will be referred to as sample temperature drain current density decreases rapidly with T C.

従来技術によれば、（１）試料を昇温すると、図６（ｅ）に示すように、水を含む表面層５５は１００℃で消失してしまい、ドレイン電流は劇的に減少するという課題があった。また、（２）試料を真空状態に曝した場合も、図６（ｅ）に示すように、表面層５５は蒸発してしまうため、ドレイン電流が劇的に減少してデバイス動作しなくなるという課題があった。従来のダイヤモンドＦＥＴは、このような根本的課題を抱えていたため、実用化まで至っていなかった。   According to the prior art, (1) when the temperature of the sample is raised, as shown in FIG. 6E, the surface layer 55 containing water disappears at 100 ° C., and the drain current decreases dramatically. was there. Further, (2) even when the sample is exposed to a vacuum state, as shown in FIG. 6E, the surface layer 55 evaporates, so that the drain current is dramatically reduced and the device does not operate. was there. Conventional diamond FETs have had such fundamental problems and have not yet been put into practical use.

本発明は、このような課題に鑑みてなされたもので、その目的とするところは、最高動作温度が高くドレイン電流密度が大きい、かつ、長時間の大電力動作にも耐える信頼性のある、実用的なダイヤモンドＦＥＴを提供することにある。   The present invention has been made in view of such problems, and the object of the present invention is a high maximum operating temperature, a high drain current density, and a reliability that can withstand long-time high-power operation. The object is to provide a practical diamond FET.

このような目的を達成するために、請求項１に記載の発明は、ダイヤモンド電界効果トランジスタであって、ダイヤモンド結晶基板と、前記ダイヤモンド結晶基板上に水素原子で終端された第１の表面層と、前記ダイヤモンド結晶基板の第１の表面層上に形成された、窒素と酸素、硫黄と酸素、及び酸素のみのいずれかから成る第２の表面層と、前記第２の表面層上に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部とを備えたことを特徴とする。   In order to achieve such an object, the invention according to claim 1 is a diamond field effect transistor, comprising: a diamond crystal substrate; and a first surface layer terminated with hydrogen atoms on the diamond crystal substrate. A second surface layer formed of only one of nitrogen and oxygen, sulfur and oxygen, and oxygen formed on the first surface layer of the diamond crystal substrate, and spaced apart from each other on the second surface layer And an electrode portion formed of a source electrode, a gate electrode, and a drain electrode.

請求項２に記載の発明は、ダイヤモンド電界効果トランジスタであって、ダイヤモンド結晶基板と、前記ダイヤモンド結晶基板上に水素原子で終端された第１の表面層と、前記第２の表面層上に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部と、前記ダイヤモンド結晶基板の第１の表面層上に形成された、窒素と酸素、硫黄と酸素、及び酸素のみのいずれかから成る第２の表面層とを備えたことを特徴とする。   The invention according to claim 2 is a diamond field effect transistor, wherein the diamond crystal substrate, the first surface layer terminated with hydrogen atoms on the diamond crystal substrate, and the second surface layer are mutually connected. Any one of nitrogen and oxygen, sulfur and oxygen, and oxygen formed on the first surface layer of the diamond crystal substrate and the electrode portion formed of the source electrode, the gate electrode, and the drain electrode formed separately from each other And a second surface layer.

請求項３に記載の発明は、請求項１又は２に記載のダイヤモンド電界効果トランジスタにおいて、前記第２の表面層上に形成されたフッ素を含む化合物からなる保護層をさらに備えたことを特徴とする。   The invention according to claim 3 is the diamond field effect transistor according to claim 1 or 2, further comprising a protective layer made of a compound containing fluorine formed on the second surface layer. To do.

請求項４に記載の発明は、請求項１乃至３のいずれかに記載のダイヤモンド電界効果トランジスタにおいて、前記第２の表面層が、ＮＯ又はＮＯ２からなることを特徴とする。 According to a fourth aspect of the invention, the diamond field effect transistor according to any one of claims 1 to 3, wherein the second surface layer, characterized in that it consists of NO or NO 2.

請求項５に記載の発明は、ダイヤモンド電界効果トランジスタであって、ダイヤモンド結晶基板と、前記ダイヤモンド結晶基板上に形成された水素原子で終端された第１の表面層と、前記第１の表面層上に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部と、前記第１の表面層上に形成されたフッ素を含む化合物からなる保護層とを備えたことを特徴とする。   The invention according to claim 5 is a diamond field effect transistor comprising a diamond crystal substrate, a first surface layer terminated with hydrogen atoms formed on the diamond crystal substrate, and the first surface layer. And an electrode portion formed of a source electrode, a gate electrode, and a drain electrode formed on the first surface layer, and a protective layer made of a compound containing fluorine formed on the first surface layer. To do.

請求項６に記載の発明は、請求項３乃至５のいずれかに記載のダイヤモンド電界効果トランジスタにおいて、前記保護層が、アモルファスフロロポリマー、ポリテトラフルオロエチレン、テトラフルオロエチレン及びフッ素を含むポリジメチルグルタルイミドのいずれかからなることを特徴とする。   A sixth aspect of the present invention is the diamond field effect transistor according to any one of the third to fifth aspects, wherein the protective layer includes an amorphous fluoropolymer, polytetrafluoroethylene, tetrafluoroethylene and fluorine. It consists of either imide, It is characterized by the above-mentioned.

請求項７に記載の発明は、ダイヤモンド電界効果トランジスタ作製方法であって、ダイヤモンド結晶基板表面に水素ラジカルを吸着させる第１の工程と、前記水素ラジカルが吸着した表面に窒素と酸素、硫黄と酸素、及び酸素のみのいずれかを含む第1の化合物原料を吸着させる第２の工程と、前記水素ラジカルが吸着した表面に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部を形成する第３の工程とを含むことを特徴とする。   The invention according to claim 7 is a method for producing a diamond field effect transistor, wherein the first step of adsorbing hydrogen radicals on the surface of the diamond crystal substrate, and nitrogen and oxygen, sulfur and oxygen on the surface on which the hydrogen radicals are adsorbed. And a second step of adsorbing the first compound raw material containing only one of oxygen and an electrode portion comprising a source electrode, a gate electrode, and a drain electrode formed on the surface on which the hydrogen radicals are adsorbed and spaced apart from each other And a third step of forming.

請求項８に記載の発明は、ダイヤモンド電界効果トランジスタ作製方法であって、ダイヤモンド結晶基板表面に水素ラジカルを吸着させる第１の工程と、前記水素ラジカルが吸着した表面に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部を形成する第２の工程と、前記水素ラジカルが吸着した表面に窒素と酸素、硫黄と酸素、及び酸素のみのいずれかを含む第1の化合物原料を吸着させる第３の工程とを含むことを特徴とする。   The invention according to claim 8 is a method for producing a diamond field effect transistor, wherein the first step of adsorbing hydrogen radicals on the surface of the diamond crystal substrate and the surface on which the hydrogen radicals are adsorbed are formed apart from each other. A second step of forming an electrode portion comprising a source electrode, a gate electrode, and a drain electrode; and a first compound raw material containing only nitrogen and oxygen, sulfur and oxygen, or oxygen on the surface on which the hydrogen radicals are adsorbed And a third step of adsorbing.

請求項９に記載の発明は、請求項７又は８に記載のダイヤモンド電界効果トランジスタ作製方法において、前記第１の化合物原料が吸着した表面にフッ素を含む第２の化合物原料を堆積させる第４の工程をさらに含むことを特徴とする。   According to a ninth aspect of the present invention, in the diamond field effect transistor manufacturing method according to the seventh or eighth aspect, the second compound raw material containing fluorine is deposited on the surface on which the first compound raw material is adsorbed. The method further includes a step.

請求項１０に記載の発明は、請求項７乃至９のいずれかに記載のダイヤモンド電界効果トランジスタ作製方法において、前記第１の化合物原料は、ＮＯ又はＮＯ２であることを特徴とする。 The invention according to claim 10, in the diamond field effect transistor manufacturing method according to any one of claims 7 to 9, wherein said first compound raw material, characterized in that it is a NO or NO 2.

請求項１１に記載の発明は、請求項９又は１０に記載のダイヤモンド電界効果トランジスタ作製方法において、前記第２の化合物原料が、アモルファスフロロポリマー、ポリテトラフルオロエチレン、テトラフルオロエチレン及びフッ素を含むポリジメチルグルタルイミドのいずれかであることを特徴とする。   An eleventh aspect of the present invention is the method for fabricating a diamond field effect transistor according to the ninth or tenth aspect, wherein the second compound raw material is a polycrystal containing amorphous fluoropolymer, polytetrafluoroethylene, tetrafluoroethylene, and fluorine. It is one of dimethylglutarimide.

このようにして、水素終端ダイヤモンド表面をＣＯ２又はＨ２Ｏなる表面層より格段に安定なＮＯ２、ＳＯ２なる表面層を形成することにより、また、表面層をポリテトラフルオロエチレン（ＰＴＦＥ）などの重合化合物からなる保護層で覆うことによって、表面層を更に安定化させ、長時間の大電力動作にも耐える信頼性のある、実用的なダイヤモンドＦＥＴが可能になる。 In this way, a surface layer made of NO 2 and SO 2 that is much more stable than the surface layer made of CO 2 or H 2 O is formed on the surface of the hydrogen-terminated diamond, and the surface layer is made of polytetrafluoroethylene (PTFE). The surface layer is further stabilized by covering with a protective layer made of a polymerized compound such as the above, and a reliable and practical diamond FET capable of withstanding long-time high-power operation becomes possible.

本発明によれば、最高動作温度が高くドレイン電流密度が大きい、かつ、長時間の大電力動作にも耐える信頼性のある、実用的なダイヤモンドＦＥＴが可能になる。   According to the present invention, a practical diamond FET having a high maximum operating temperature, a high drain current density, and a reliability that can withstand long-time high power operation can be realized.

以下、図面を参照しながら本発明の実施形態について詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

（実施形態１）
図１（ａ）〜（ｅ）に、本発明の実施形態１に係るダイヤモンドＦＥＴの作製工程を示す。マイクロ波プラズマＣＶＤ装置などで結晶成長したダイヤモンド結晶１を用意し、マイクロ波ＣＶＤ装置のリアクター内で水素プラズマ（Ｈで表す）を照射し、水素を含む表面層２を形成する（図１（ａ））。マイクロ波プラズマＣＶＤ装置で、水素プラズマ雰囲気内で結晶成長したダイヤモンド結晶１表面は、既に水素を含む第1の表面層２を形成しているので、第1の表面層２が十分形成されている場合、改めて水素プラズマ照射処理をしなくても良い。 (Embodiment 1)
1A to 1E show a process for producing a diamond FET according to Embodiment 1 of the present invention. A diamond crystal 1 crystal-grown by a microwave plasma CVD apparatus or the like is prepared, and hydrogen plasma (represented by H) is irradiated in a reactor of the microwave CVD apparatus to form a surface layer 2 containing hydrogen (FIG. 1A )). Since the surface of diamond crystal 1 which has been crystal-grown in a hydrogen plasma atmosphere with a microwave plasma CVD apparatus has already formed a first surface layer 2 containing hydrogen, the first surface layer 2 is sufficiently formed. In this case, the hydrogen plasma irradiation process may not be performed again.

次に、第1の表面層２上の一部の領域に、空間的に分離して、厚さ６００ｎｍの金薄膜３１、３２を蒸着する。これは、各ソース電極３１、ドレイン電極３２になる。   Next, gold thin films 31 and 32 having a thickness of 600 nm are vapor-deposited in a partial region on the first surface layer 2 in a spatially separated manner. This becomes the source electrode 31 and the drain electrode 32.

次に、ソース電極３１とドレイン電極３２との間に、空間的に分離して、Ａｌ薄膜４を蒸着する（図１（ｃ））。このＡｌ薄膜４はゲート電極４になる。   Next, the Al thin film 4 is vapor-deposited spatially separated between the source electrode 31 and the drain electrode 32 (FIG. 1C). The Al thin film 4 becomes the gate electrode 4.

次に、試料にＮＯ２を供給し、第１の表面層２上に第２の表面層５を形成する（図１（ｄ））。また、第２の表面層５は、ソース電極３１とゲート電極４間、ゲート電極４とドレイン電極３２間を結ぶように形成する。 Next, NO 2 is supplied to the sample, and the second surface layer 5 is formed on the first surface layer 2 (FIG. 1D). The second surface layer 5 is formed so as to connect between the source electrode 31 and the gate electrode 4 and between the gate electrode 4 and the drain electrode 32.

次に、露出した第２の表面層５全体を覆うように、ポリテトラフルオロエチレン（ＰＴＦＥ）、テトラフルオロエチレンからなる保護層６を第２の表面層５上に堆積させる（図１（ｅ））。図９に、本発明の実施形態１に係るダイヤモンドＦＥＴの透過型電子顕微鏡（ＴＥＭ）断面図を示す。   Next, a protective layer 6 made of polytetrafluoroethylene (PTFE) or tetrafluoroethylene is deposited on the second surface layer 5 so as to cover the entire exposed second surface layer 5 (FIG. 1E). ). FIG. 9 shows a transmission electron microscope (TEM) cross-sectional view of the diamond FET according to Embodiment 1 of the present invention.

このようにして作製された本発明のダイヤモンドＦＥＴに対し、図１（ｆ）のように配線してドレイン電流電圧特性を測定し、その結果を図７（ｂ）に示す。本発明のダイヤモンドＦＥＴのゲート電圧−３Ｖにおける最大ドレイン電流密度は１８０ｍＡ／ｍｍと従来の約３０倍になり、トランジスタ特性は大きく向上している。   The diamond FET of the present invention thus manufactured is wired as shown in FIG. 1 (f) and the drain current-voltage characteristics are measured. The result is shown in FIG. 7 (b). The maximum drain current density at a gate voltage of −3 V of the diamond FET of the present invention is 180 mA / mm, which is about 30 times that of the conventional one, and the transistor characteristics are greatly improved.

図８に、本発明のダイヤモンドＦＥＴと従来のダイヤモンドＦＥＴのドレイン電流の試料温度特性を示す。従来のダイヤモンドＦＥＴでは、室温から１４０℃にかけて、第２の表面層５５が蒸発してしまうため、ドレイン電流は急激に減少する。それに対して、本発明のダイヤモンドＦＥＴは、第２の表面層５が安定しているため、３００℃までＦＥＴ動作する。   FIG. 8 shows the sample temperature characteristics of the drain current of the diamond FET of the present invention and the conventional diamond FET. In the conventional diamond FET, since the second surface layer 55 evaporates from room temperature to 140 ° C., the drain current rapidly decreases. In contrast, the diamond FET of the present invention operates up to 300 ° C. because the second surface layer 5 is stable.

表１は、本発明の実施形態１に係るゲート長１０μｍのダイヤモンドＦＥＴにおけるドレイン電流密度（ＩＤＭＡＸ）と最高動作温度（ＴＣ）をまとめたものである。 Table 1 summarizes the drain current density (I DMAX ) and the maximum operating temperature (T C ) in a diamond FET having a gate length of 10 μm according to Embodiment 1 of the present invention.

本発明の実施形態1に係るゲート長１０μダイヤモンドＦＥＴにおいて、保護層６にＰＴＦＥを用い、表面層２を、ＮＯ、ＮＯ２、ＳＯ２、Ｏ３にした場合、（ＩＤＭＡＸ、ＴＣ）は各々、表1のようになり、従来の方法による場合（６ｍＡ／ｍｍ、１００℃）より大幅に上昇する。 In the diamond FET having a gate length of 10 μm according to the first embodiment of the present invention, when PTFE is used for the protective layer 6 and the surface layer 2 is NO, NO 2 , SO 2 , O 3 , (I DMAX , T C ) is Each of them is as shown in Table 1, which is significantly higher than the case of the conventional method (6 mA / mm, 100 ° C.).

また、本発明の実施形態1に係るダイヤモンドＦＥＴにおいて、表面層２に、ＮＯ２にし、保護層をフッソ化ポリミド、ＡＦ１６００（ＴＦＥ（テトラフルオロエチレン）とＰＤＤ（ジオキソール）からなるアモルファスフロロポリマーでガラス転移点が１６０℃のもの）、ＡＦ２４００（ＴＦＥ（テトラフルオロエチレン）とＰＤＤ（ジオキソール）からなるアモルファスフロロポリマーでガラス転移点が２４０℃のもの）、テトラフルオロエチレン、Ｃ２Ｆ４とパーフルオロアルコキシエチレン、Ｆを含むＰＭＭＡ（分子鎖内の水素の一部をフッ素で置換したポリメタクリル酸メチル樹脂）、ＰＭＧＩ（ポリメチルグルタルイミド）、ＡｌＦ３、ＣａＦ２、ＣｅＦ３、ＬｉＦ、ＭｇＦ２、ＮｄＦ３、ＮａＦを用いた場合、（ＩＤＭＡＸ、ＴＣ）は各々、表１のようになり、従来の方法による場合（６ｍＡ／ｍｍ、１００℃）より大幅に上昇する。 Further, in the diamond FET according to the first embodiment of the present invention, the surface layer 2 is made of NO 2 , and the protective layer is made of glass with an amorphous fluoropolymer made of fluorinated polyimide, AF1600 (TFE (tetrafluoroethylene) and PDD (dioxole)). those transition point of 160 ℃), AF2400 (TFE (tetrafluoroethylene) and having a glass transition point of 240 ° C. in an amorphous fluoropolymer consisting PDD (dioxole)), tetrafluoroethylene, C 2 F 4 and perfluoroalkoxy PMMA containing ethylene and F (polymethyl methacrylate resin in which a part of hydrogen in the molecular chain is substituted with fluorine), PMGI (polymethylglutarimide), AlF 3 , CaF 2 , CeF 3 , LiF, MgF 2 , NdF 3. When NaF is used, (I D MAX , T C ) are as shown in Table 1, and are significantly higher than those obtained by the conventional method (6 mA / mm, 100 ° C.).

（実施形態２）
図２に、本発明の実施形態２に係るダイヤモンドＦＥＴの構造を示す。実施形態２では、実施形態１の図１（ａ）〜（ｄ）までの工程を行い、図１（ｅ）の工程を行わない。 (Embodiment 2)
FIG. 2 shows the structure of a diamond FET according to Embodiment 2 of the present invention. In the second embodiment, the steps of FIGS. 1A to 1D of the first embodiment are performed, and the step of FIG. 1E is not performed.

本発明の実施形態2に係るゲート長を１０μｍのダイヤモンドＦＥＴにおいて、表面層２としてＮＯ２を用いた場合、ＦＥＴのドレイン電流密度（ＩＤＭＡＸ）と最高動作温度（ＴＣ）は各々（１８０ｍＡ／ｍｍ、２２０℃）になる。保護層が無い分だけ実施形態１よりもＴＣが低いが、従来のダイヤモンドＦＥＴの場合の（６ｍＡ／ｍｍ、１００℃）より大幅に上昇する。 In a diamond FET having a gate length of 10 μm according to Embodiment 2 of the present invention, when NO 2 is used as the surface layer 2, the drain current density (I DMAX ) and the maximum operating temperature (T C ) of the FET are each 180 mA / mm, 220 ° C.). Although the TC is lower than that of the first embodiment due to the absence of the protective layer, it is significantly higher than that of the conventional diamond FET (6 mA / mm, 100 ° C.).

（実施形態３）
図３に、本発明の実施形態３に係るダイヤモンドＦＥＴの構成を示す。実施形態３では、実施形態１の図１（ａ）〜（ｃ）、（ｅ）の工程を行い、図１（ｄ）の工程を行わない。 (Embodiment 3)
FIG. 3 shows the configuration of a diamond FET according to Embodiment 3 of the present invention. In the third embodiment, the steps of FIGS. 1A to 1C and 1E of the first embodiment are performed, and the step of FIG. 1D is not performed.

本発明の実施形態3に係るゲート長を１０μｍのダイヤモンドＦＥＴにおいて、保護層６としてＰＴＦＥを用いた場合、ＦＥＴのドレイン電流密度（ＩＤＭＡＸ）と最高動作温度（ＴＣ）は（１００ｍＡ／ｍｍ、２６０℃）になる。表面層２が無い分だけ、実施形態１の場合よりもＩＤＭＡＸが低いが、従来のダイヤモンドＦＥＴの場合の（６ｍＡ／ｍｍ、１００℃）より大幅に上昇する。 In a diamond FET having a gate length of 10 μm according to Embodiment 3 of the present invention, when PTFE is used as the protective layer 6, the drain current density (I DMAX ) and the maximum operating temperature (T C ) of the FET are (100 mA / mm, 260 ° C.). Because of the absence of the surface layer 2, IDMAX is lower than that of the first embodiment, but is significantly higher than that of the conventional diamond FET (6 mA / mm, 100 ° C.).

（実施形態４）
図４に、本発明の実施形態４に係るダイヤモンドＦＥＴの作製工程を示す。実施形態４と実施形態１との差異は、電極設置前に第２の表面層５を形成する点にある。 (Embodiment 4)
FIG. 4 shows a manufacturing process of a diamond FET according to Embodiment 4 of the present invention. The difference between the fourth embodiment and the first embodiment is that the second surface layer 5 is formed before the electrodes are installed.

マイクロ波プラズマＣＶＤ装置などで結晶成長したダイヤモンド結晶１を用意し、マイクロ波ＣＶＤ装置のリアクター内で水素プラズマ（Ｈで表す）を照射し、水素を含む表面層２を形成する（図４（ａ））。マイクロ波プラズマＣＶＤ装置で、水素プラズマ雰囲気内で結晶成長したダイヤモンド結晶１表面は、既に水素を含む表面層２を形成しているので、第1の表面層２が十分形成されている場合、改めて水素プラズマ照射処理をしなくても良い。   A diamond crystal 1 crystal-grown by a microwave plasma CVD apparatus or the like is prepared and irradiated with hydrogen plasma (represented by H) in a reactor of the microwave CVD apparatus to form a surface layer 2 containing hydrogen (FIG. 4A )). Since the surface of the diamond crystal 1 which has been grown in a hydrogen plasma atmosphere by a microwave plasma CVD apparatus has already formed a surface layer 2 containing hydrogen, if the first surface layer 2 has been sufficiently formed, it is again necessary. It is not necessary to perform the hydrogen plasma irradiation treatment.

次に、試料にＮＯ２を供給し、第１の表面層２上に第２の表面層５を形成する（図４（ｂ））。 Next, NO 2 is supplied to the sample, and the second surface layer 5 is formed on the first surface layer 2 (FIG. 4B).

次に、第2の表面層５上の一部領域に、空間的に分離して、厚さ６００ｎｍの金薄膜３１、３２を蒸着する。これは、各々ソース電極３１、ドレイン電極３２になる（図４（ｃ））。   Next, gold thin films 31 and 32 having a thickness of 600 nm are deposited in a partial region on the second surface layer 5 in a spatially separated manner. This becomes the source electrode 31 and the drain electrode 32, respectively (FIG. 4C).

次に、ソース電極３１、ドレイン電極３２との間に、空間的に分離して、Ａｌ薄膜４を蒸着する（図４（ｄ））。このＡｌ薄膜４はゲート電極４になる。   Next, the Al thin film 4 is deposited by being spatially separated between the source electrode 31 and the drain electrode 32 (FIG. 4D). The Al thin film 4 becomes the gate electrode 4.

次に、第２の表面層５上全体を覆うように、ポリテトラフルオロエチレン（ＰＴＦＥ）、テトラフルオロエチレンからなる保護層６を堆積させる（図４（ｅ））。   Next, a protective layer 6 made of polytetrafluoroethylene (PTFE) or tetrafluoroethylene is deposited so as to cover the entire surface of the second surface layer 5 (FIG. 4E).

このようにして作製された本発明のダイヤモンドＦＥＴに対し、図４（ｆ）のように配線してドレイン電流電圧特性を測定し、その結果を図７（ｂ）に示す。本発明のダイヤモンドＦＥＴのゲート電圧−３Ｖにおける最大ドレイン電流密度は１８０ｍＡ／ｍｍと従来の約３０倍になり、トランジスタ特性は大きく向上している。   The diamond FET of the present invention thus manufactured is wired as shown in FIG. 4 (f) and the drain current / voltage characteristics are measured. The result is shown in FIG. 7 (b). The maximum drain current density at a gate voltage of −3 V of the diamond FET of the present invention is 180 mA / mm, which is about 30 times that of the conventional one, and the transistor characteristics are greatly improved.

図８に、本発明によって作製したＦＥＴのドレイン電流の試料温度特性を示す。従来の方法では、室温から１４０℃にかけて、第２の表面層５５が蒸発してしまうため、ドレイン電流は急激に減少する。それに対して、本発明によれば、３００℃まで第２の表面層５が安定して、ＦＥＴ動作した。   FIG. 8 shows a sample temperature characteristic of the drain current of the FET manufactured according to the present invention. In the conventional method, since the second surface layer 55 evaporates from room temperature to 140 ° C., the drain current rapidly decreases. On the other hand, according to the present invention, the second surface layer 5 was stably operated up to 300 ° C. and operated as an FET.

表２は、このようにして作製した本発明の実施形態４に係るゲート長を１０μｍのダイヤモンドＦＥＴのドレイン電流密度（ＩＤＭＡＸ）と最高動作温度（ＴＣ）をまとめたものである。 Table 2 summarizes the drain current density (I DMAX ) and the maximum operating temperature (T C ) of the diamond FET having the gate length of 10 μm according to the fourth embodiment of the present invention manufactured as described above.

本発明の実施形態4に係るゲート長１０μｍダイヤモンドＦＥＴにおいて、保護層６をＰＴＦＥを用い、表面層２を、ＮＯ、ＮＯ２、ＳＯ２、Ｏ３にした場合、（ＩＤＭＡＸ、ＴＣ）は各々、表２のようになり、従来の方法による場合（６ｍＡ／ｍｍ、１００℃）より大幅に上昇する。 In the diamond FET having a gate length of 10 μm according to the fourth embodiment of the present invention, when PTFE is used as the protective layer 6 and NO, NO 2 , SO 2 , and O 3 are used as the surface layer 2, (I DMAX , T C ) is Each is as shown in Table 2, which is a significant increase over the conventional method (6 mA / mm, 100 ° C.).

また、本発明の実施形態4に係るダイヤモンドＦＥＴにおいて、表面層２を、ＮＯ２にし、保護層をフッソ化ポリミド、ＡＦ１６００、ＡＦ２４００、テトラフルオロエチレン、Ｃ２Ｆ４とパーフルオロアルコキシエチレン、Ｆを含むＰＭＭＡ、ＰＭＧＩ、ＡｌＦ３、ＣａＦ２、ＣｅＦ３、ＬｉＦ、ＭｇＦ２、ＮｄＦ３、ＮａＦを用いた場合、（ＩＤＭＡＸ、ＴＣ）は各々、表２のようになり、従来の方法による場合（６ｍＡ／ｍｍ、１００℃）より大幅に上昇する。 Further, in the diamond FET according to the fourth embodiment of the present invention, the surface layer 2 is NO 2 , and the protective layer is fluorinated polyimide, AF1600, AF2400, tetrafluoroethylene, C 2 F 4 and perfluoroalkoxyethylene, F. When including PMMA, PMGI, AlF 3 , CaF 2 , CeF 3 , LiF, MgF 2 , NdF 3 , and NaF, (I DMAX , T C ) are as shown in Table 2, respectively, according to the conventional method (6 mA / mm, 100 ° C.).

（実施形態５）
図５に、本発明の実施形態５に係るダイヤモンドＦＥＴの構造を示す。実施形態５では、実施形態４の図４（ａ）〜（ｄ）までの工程を行い、図４（ｅ）の工程を行わない。 (Embodiment 5)
FIG. 5 shows the structure of a diamond FET according to Embodiment 5 of the present invention. In the fifth embodiment, the processes of FIGS. 4A to 4D of the fourth embodiment are performed, and the process of FIG. 4E is not performed.

本発明の実施形態５に係るゲート長１０μｍのダイヤモンドＦＥＴにおいて、表面層２としてＮＯ２を用いた場合、ＦＥＴのドレイン電流密度（ＩＤＭＡＸ）と最高動作温度（ＴＣ）は各々（１８０ｍＡ／ｍｍ、２２０℃）になる。保護層がないだけ、実施形態１よりもＴＣが低いが、従来の方法による場合（６ｍＡ／ｍｍ、１００℃）より大幅に上昇する。 In the diamond FET having a gate length of 10 μm according to the fifth embodiment of the present invention, when NO 2 is used as the surface layer 2, the drain current density (I DMAX ) and the maximum operating temperature (T C ) of the FET are each (180 mA / mm). 220 ° C.). Since there is no protective layer, TC is lower than that of the first embodiment, but it is significantly higher than in the case of the conventional method (6 mA / mm, 100 ° C.).

（ａ）〜（ｅ）は、本発明の実施形態１に係るダイヤモンドＦＥＴの作製工程を示す図であり、（ｆ）は、ドレイン電流電圧特性の測定方法を示す図である。(A)-(e) is a figure which shows the preparation process of the diamond FET which concerns on Embodiment 1 of this invention, (f) is a figure which shows the measuring method of a drain current voltage characteristic. 本発明の実施形態２に係るダイヤモンドＦＥＴの構造を示す図である。It is a figure which shows the structure of the diamond FET which concerns on Embodiment 2 of this invention. 本発明の実施形態３に係るダイヤモンドＦＥＴの構成を示す図である。It is a figure which shows the structure of the diamond FET which concerns on Embodiment 3 of this invention. （ａ）〜（ｅ）は、本発明の実施形態４に係るダイヤモンドＦＥＴの作製工程を示す図であり、（ｆ）は、ドレイン電流電圧特性の測定方法を示す図である。(A)-(e) is a figure which shows the preparation process of the diamond FET which concerns on Embodiment 4 of this invention, (f) is a figure which shows the measuring method of a drain current voltage characteristic. 本発明の実施形態５に係るダイヤモンドＦＥＴの構造を示す図である。It is a figure which shows the structure of the diamond FET which concerns on Embodiment 5 of this invention. （ａ）〜（ｅ）は、従来のダイヤモンドＦＥＴの作製工程を示す図であり、（ｆ）は、ドレイン電流電圧特性の測定方法を示す図である。(A)-(e) is a figure which shows the preparation process of the conventional diamond FET, (f) is a figure which shows the measuring method of a drain current voltage characteristic. （ａ）は、従来のダイヤモンドＦＥＴのドレイン電流電圧特性を示す図であり、（ｂ）は、本発明のダイヤモンドＦＥＴのドレイン電流電圧特性を示す図である。(A) is a figure which shows the drain current voltage characteristic of the conventional diamond FET, (b) is a figure which shows the drain current voltage characteristic of the diamond FET of this invention. 本発明によって作製したダイヤモンドＦＥＴのドレイン電流の試料温度特性を示す図である。It is a figure which shows the sample temperature characteristic of the drain current of the diamond FET produced by this invention. 本発明の実施形態１に係るダイヤモンドＦＥＴの透過型電子顕微鏡（ＴＥＭ）断面図である。It is a transmission electron microscope (TEM) sectional drawing of the diamond FET which concerns on Embodiment 1 of this invention.

符号の説明Explanation of symbols

１ ダイヤモンド結晶膜
２ 水素を含む第１の表面層
３１ ソース電極（Ａｕ）
３２ ドレイン電極（Ａｕ）
４ ゲート電極（Ａｌ）
５ ＮＯ２を含む第２の表面層
５５ ＣＯ２、Ｈ２Ｏを含む第２の表面層
６ ポリテトラフルオロエチレン（ＰＴＦＥ）を含む保護層 DESCRIPTION OF SYMBOLS 1 Diamond crystal film 2 The 1st surface layer 31 containing hydrogen Source electrode (Au)
32 Drain electrode (Au)
4 Gate electrode (Al)
5 Second surface layer containing NO 2 55 Second surface layer containing CO 2 and H 2 O 6 Protective layer containing polytetrafluoroethylene (PTFE)

Claims (11)

ダイヤモンド結晶基板と、
前記ダイヤモンド結晶基板上に水素原子で終端された第１の表面層と、
前記ダイヤモンド結晶基板の第１の表面層上に形成された、窒素と酸素、硫黄と酸素、及び酸素のみのいずれかから成る第２の表面層と、
前記第２の表面層上に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部と、
を備えたことを特徴とするダイヤモンド電界効果トランジスタ。 A diamond crystal substrate;
A first surface layer terminated with hydrogen atoms on the diamond crystal substrate;
A second surface layer made of only nitrogen and oxygen, sulfur and oxygen, and oxygen, formed on the first surface layer of the diamond crystal substrate;
An electrode portion comprising a source electrode, a gate electrode, and a drain electrode formed on the second surface layer so as to be spaced apart from each other;
A diamond field effect transistor comprising: ダイヤモンド結晶基板と、
前記ダイヤモンド結晶基板上に水素原子で終端された第１の表面層と、
前記第２の表面層上に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部と、
前記ダイヤモンド結晶基板の第１の表面層上に形成された、窒素と酸素、硫黄と酸素、及び酸素のみのいずれかから成る第２の表面層と、
を備えたことを特徴とするダイヤモンド電界効果トランジスタ。 A diamond crystal substrate;
A first surface layer terminated with hydrogen atoms on the diamond crystal substrate;
An electrode portion comprising a source electrode, a gate electrode, and a drain electrode formed on the second surface layer so as to be spaced apart from each other;
A second surface layer made of only nitrogen and oxygen, sulfur and oxygen, and oxygen, formed on the first surface layer of the diamond crystal substrate;
A diamond field effect transistor comprising: 前記第２の表面層上に形成されたフッ素を含む化合物からなる保護層をさらに備えたことを特徴とする請求項１又は２に記載のダイヤモンド電界効果トランジスタ。   The diamond field effect transistor according to claim 1 or 2, further comprising a protective layer made of a compound containing fluorine formed on the second surface layer. 前記第２の表面層は、ＮＯ又はＮＯ２からなることを特徴とする請求項１乃至３のいずれかに記載のダイヤモンド電界効果トランジスタ。 The second surface layer is a diamond field effect transistor according to any one of claims 1 to 3, characterized in that it consists of NO or NO 2. ダイヤモンド結晶基板と、
前記ダイヤモンド結晶基板上に形成された水素原子で終端された第１の表面層と、
前記第１の表面層上に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部と、
前記第１の表面層上に形成されたフッ素を含む化合物からなる保護層と
を備えたことを特徴とするダイヤモンド電界効果トランジスタ。 A diamond crystal substrate;
A first surface layer terminated with hydrogen atoms formed on the diamond crystal substrate;
An electrode portion comprising a source electrode, a gate electrode, and a drain electrode formed on the first surface layer so as to be spaced apart from each other;
A diamond field effect transistor comprising: a protective layer made of a compound containing fluorine formed on the first surface layer. 前記保護層は、アモルファスフロロポリマー、ポリテトラフルオロエチレン、テトラフルオロエチレン及びフッ素を含むポリジメチルグルタルイミドのいずれかからなることを特徴とする請求項３乃至５のいずれかに記載のダイヤモンド電界効果トランジスタ。   6. The diamond field effect transistor according to claim 3, wherein the protective layer is made of any one of amorphous fluoropolymer, polytetrafluoroethylene, polydimethylglutarimide containing tetrafluoroethylene and fluorine. . ダイヤモンド結晶基板表面に水素ラジカルを吸着させる第１の工程と、
前記水素ラジカルが吸着した表面に窒素と酸素、硫黄と酸素、及び酸素のみのいずれかを含む第1の化合物原料を吸着させる第２の工程と、
前記水素ラジカルが吸着した表面に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部を形成する第３の工程と
を含むことを特徴とするダイヤモンド電界効果トランジスタ作製方法。 A first step of adsorbing hydrogen radicals on the surface of the diamond crystal substrate;
A second step of adsorbing a first compound material containing only one of nitrogen and oxygen, sulfur and oxygen, and oxygen on the surface on which the hydrogen radicals are adsorbed;
And a third step of forming an electrode portion comprising a source electrode, a gate electrode, and a drain electrode formed on the surface on which the hydrogen radicals are adsorbed to each other, and a third step of producing the diamond field effect transistor. ダイヤモンド結晶基板表面に水素ラジカルを吸着させる第１の工程と、
前記水素ラジカルが吸着した表面に互いに離間して形成されたソース電極、ゲート電極、ドレイン電極からなる電極部を形成する第２の工程と、
前記水素ラジカルが吸着した表面に窒素と酸素、硫黄と酸素、及び酸素のみのいずれかを含む第1の化合物原料を吸着させる第３の工程と
を含むことを特徴とするダイヤモンド電界効果トランジスタ作製方法。 A first step of adsorbing hydrogen radicals on the surface of the diamond crystal substrate;
A second step of forming an electrode portion comprising a source electrode, a gate electrode, and a drain electrode formed on the surface on which the hydrogen radical is adsorbed and spaced apart from each other;
And a third step of adsorbing a first compound material containing only one of nitrogen and oxygen, sulfur and oxygen, and oxygen on the surface on which the hydrogen radicals are adsorbed. . 前記第１の化合物原料が吸着した表面にフッ素を含む第２の化合物原料を堆積させる第４の工程をさらに含むことを特徴とする請求項７又は８に記載のダイヤモンド電界効果トランジスタ作製方法。   The diamond field effect transistor manufacturing method according to claim 7 or 8, further comprising a fourth step of depositing a second compound material containing fluorine on a surface on which the first compound material is adsorbed. 前記第１の化合物原料は、ＮＯ又はＮＯ２であることを特徴とする請求項７乃至９のいずれかに記載のダイヤモンド電界効果トランジスタ作製方法。 The diamond field effect transistor manufacturing method according to claim 7, wherein the first compound material is NO or NO 2 . 前記第２の化合物原料は、アモルファスフロロポリマー、ポリテトラフルオロエチレン、テトラフルオロエチレン及びフッ素を含むポリジメチルグルタルイミドのいずれかであることを特徴とする請求項９又は１０に記載のダイヤモンド電界効果トランジスタ作製方法。   11. The diamond field effect transistor according to claim 9, wherein the second compound raw material is one of amorphous fluoropolymer, polytetrafluoroethylene, tetrafluoroethylene, and polydimethylglutarimide containing fluorine. Manufacturing method.
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