JP2010022190A - Gate driving device of voltage driving type semiconductor device - Google Patents

Gate driving device of voltage driving type semiconductor device Download PDF

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JP2010022190A
JP2010022190A JP2009244730A JP2009244730A JP2010022190A JP 2010022190 A JP2010022190 A JP 2010022190A JP 2009244730 A JP2009244730 A JP 2009244730A JP 2009244730 A JP2009244730 A JP 2009244730A JP 2010022190 A JP2010022190 A JP 2010022190A
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voltage
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driven semiconductor
semiconductor element
resistance
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Hideaki Kakigi
秀昭 柿木
Kunio Matsubara
邦夫 松原
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress the surge voltage of a free-wheeling diode provided to a semiconductor device constituting each arm of a power converting apparatus, and reduce the turn-on loss of the semiconductor device. <P>SOLUTION: In the gate driving device, a delaying circuit comprising a resistance R and a capacitor C, a resistance Rg(on)1, and a transistor TR10 are connected so as to be different from conventional gate driving circuits which have a problem. Thereby, a semiconductor device IGBT is turned on by the resistance Rg(on) in the low-current region of the reverse recovery time of a free-wheeling diode, and is turned on by the parallel resistance comprising a resistance Rg(on) and the Rg(on)1 in the high-current region of the reverse recovery time of the free-wheeling diode respectively so as to solve the problem. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

この発明は、電力変換装置を構成する電圧駆動型半導体素子のゲート駆動装置、特に電力変換装置を高電圧化するために、電圧駆動型半導体素子を直列接続して構成される電力変換装置に用いて好適なゲート駆動装置に関する。   INDUSTRIAL APPLICABILITY The present invention is used in a voltage-driven semiconductor element gate driving device constituting a power conversion device, in particular, a power conversion device configured by connecting voltage-driven semiconductor elements in series in order to increase the voltage of the power conversion device. And a suitable gate driving device.

図３に、電圧駆動型半導体素子としてＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）を用いたチョッパ回路の例を示す。これは、直流電源Ｅｄに対し上アームにはＩＧＢＴ１と、これに逆並列に接続されたフリーホイーリングダイオードＦＷＤ１と、下アームにはＩＧＢＴ２とこれに逆並列に接続されたＦＷＤ２とが設けられ、ＩＧＢＴ１には負荷が接続されている。ＧＤＵ１，ＧＤＵ２はゲート駆動装置で、具体的には例えば図４に示すように、ＩＧＢＴをオン，オフさせるためのトランジスタＴＲ１，ＴＲ２、抵抗Ｒｇ（ｏｎ），Ｒｇ（ｏｆｆ）およびインターフェイス回路ＩＦなどから構成される。   FIG. 3 shows an example of a chopper circuit using an IGBT (insulated gate bipolar transistor) as a voltage-driven semiconductor element. The DC power supply Ed is provided with an IGBT 1 on the upper arm and a freewheeling diode FWD1 connected in antiparallel with the DC power supply Ed, and an IGBT 2 and FWD2 connected in antiparallel with the lower arm on the lower arm. A load is connected to the IGBT 1. GDU1 and GDU2 are gate drive devices. Specifically, for example, as shown in FIG. 4, transistors TR1 and TR2 for turning on and off IGBTs, resistors Rg (on) and Rg (off), an interface circuit IF, and the like. Composed.

いま、図３のＩＧＢＴ２をターンオンすると、負荷を通して電流が流れる。次に、ＩＧＢＴ２をターンオフすると負荷よりＩＧＢＴ２を流れていた電流は、ＦＷＤ１へ転流する（フリーホイーリングモード）。この状態でＩＧＢＴ２がターンオンするとＦＷＤ１は逆回復し、電流は再度負荷からＩＧＢＴ２を通るルートに切り替わる。このとき、ＦＷＤ１へ転流したフリーホイーリング電流が、素子の定格の１／１０以下の低電流時にＦＷＤ１が逆回復すると、大きなサージ電圧が発生することが指摘されている。そのときの様子を示すのが図５，図６で、ＦＷＤ１に定格以上のサージ電圧が印加された例が示されている。なお、図６は図５の部分（要部）拡大図である。   Now, when the IGBT 2 in FIG. 3 is turned on, a current flows through the load. Next, when the IGBT 2 is turned off, the current flowing through the IGBT 2 from the load is commutated to the FWD 1 (free wheeling mode). When the IGBT 2 is turned on in this state, the FWD 1 is reversely recovered, and the current is switched again from the load to the route passing through the IGBT 2. At this time, it is pointed out that a large surge voltage is generated when the FWD1 reversely recovers when the freewheeling current commutated to the FWD1 is a low current of 1/10 or less of the element rating. FIG. 5 and FIG. 6 show the state at that time, and an example in which a surge voltage exceeding the rating is applied to the FWD 1 is shown. FIG. 6 is an enlarged view of the part (main part) of FIG.

図３では１つのアームに１つの電圧駆動型半導体素子を用いる例であるが、上記の問題は図７のように１つのアームに複数（図では２つ）の素子を設けて高電圧化を図る電力変換装置の場合も同様で、そのときの様子を図８に点線で示している。これは、ゲート駆動装置ＧＤＵ３，４により下アーム素子ＩＧＢＴ３，４を動作させるときの上アームのＦＷＤ１，２の逆回復時にＩＧＢＴ１，２に印加される電圧波形を示している。ＩＧＢＴ１，２のいずれにも点線で示すような定格以上のサージ電圧が印加されていることが分かる。   FIG. 3 shows an example in which one voltage-driven semiconductor element is used for one arm. However, the above problem can be solved by providing a plurality of (two in the figure) elements in one arm as shown in FIG. The same applies to the power conversion device to be achieved, and the state at that time is indicated by a dotted line in FIG. This shows a voltage waveform applied to the IGBTs 1 and 2 during reverse recovery of the FWDs 1 and 2 of the upper arms when the lower arm elements IGBTs 3 and 4 are operated by the gate driving devices GDU3 and 4, respectively. It can be seen that a surge voltage exceeding the rating as indicated by the dotted line is applied to both IGBTs 1 and 2.

このようなサージ電圧は時に素子の定格耐圧を大きく超え、最悪の場合は素子破壊に至るおそれがある。このため、従来は例えば図４に示すゲートオン抵抗Ｒｇ（ｏｎ）の値を大きくすることで、ＩＧＢＴ２のターンオン時間を遅くしＩＧＢＴ２側で電圧を保持する時間を長くし、ＦＷＤ１に印加される電圧を低くしてサージ電圧を抑制する方法が用いられている。しかし、ゲート抵抗が大きいと電圧保持時間が増大し、ターンオン損失が増加する。このターンオン損失の増加は、素子全体の総損失を増加させ、動作周波数を低下させたり出力電流を低下させなければならないという問題が生じる。   Such a surge voltage sometimes greatly exceeds the rated breakdown voltage of the element, and in the worst case, the element may be destroyed. Therefore, conventionally, for example, by increasing the value of the gate-on resistance Rg (on) shown in FIG. 4, the turn-on time of the IGBT 2 is delayed, the time for holding the voltage on the IGBT 2 side is lengthened, and the voltage applied to the FWD 1 is increased. A method of suppressing the surge voltage by lowering the voltage is used. However, if the gate resistance is large, the voltage holding time increases and the turn-on loss increases. This increase in turn-on loss increases the total loss of the entire device, causing a problem that the operating frequency must be lowered or the output current must be lowered.

また、１つのアームに複数の素子を設けて高電圧化を図る場合には、上記の問題に加えてさらに、素子特性のばらつき等による問題が発生する。この問題を説明するのが図９で、複数の素子間の素子特性のばらつき等によりＩＧＢＴのターンオンタイミングに違いが生じ、電圧分担にアンバランスが生じた場合を示す。ここでは、例えば図７の上アームのＩＧＢＴ２の方が早くオンし、このときＩＧＢＴ１がオフしているため、ＩＧＢＴ１にだけ電圧が印加されると言うアンバランスが生じている例である。このとき、ＩＧＢＴ１のコレクタ−エミッタ間電圧ＶＣＥ（１）と、ＩＧＢＴ２のコレクタ−エミッタ間電圧ＶＣＥ（２）を加えた電圧が直流電圧Ｅｄに等しくならない期間があるのは、スナバコンデンサＣと主回路浮遊インダクタンスＬｍとの共振動作によるものである。   Further, when a plurality of elements are provided on one arm to increase the voltage, a problem due to variations in element characteristics occurs in addition to the above problems. This problem is illustrated in FIG. 9, which shows a case where there is a difference in IGBT turn-on timing due to variations in element characteristics among a plurality of elements, and an imbalance occurs in voltage sharing. Here, for example, the IGBT 2 of the upper arm in FIG. 7 is turned on earlier, and the IGBT 1 is turned off at this time, so that an imbalance occurs in which a voltage is applied only to the IGBT 1. At this time, there is a period in which the voltage obtained by adding the collector-emitter voltage VCE (1) of the IGBT 1 and the collector-emitter voltage VCE (2) of the IGBT 2 is not equal to the DC voltage Ed. This is due to resonance operation with the floating inductance Lm.

このように電圧アンバランスが発生するが、その対策として、例えば図７にも示すように各ＩＧＢＴにスナバコンデンサＣ，スナバ抵抗Ｒ等からなるＲＣスナバ回路を付加することによって、遅れてオンするＩＧＢＴ１の電圧上昇率（ｄｖ／ｄｔ）を低減させて、ＩＧＢＴ１にオン信号が入るまでの期間（Δｔ）、ＩＧＢＴ１に印加される電圧を抑制するようにしている。   In this way, voltage imbalance is generated. As a countermeasure, for example, as shown in FIG. 7, an IGBT 1 that is turned on late by adding an RC snubber circuit including a snubber capacitor C and a snubber resistor R to each IGBT. The voltage increase rate (dv / dt) is reduced, and the voltage applied to the IGBT 1 is suppressed during the period (Δt) until the ON signal is input to the IGBT 1.

ＩＧＢＴを直列接続して用いる場合、上述のように、各ＩＧＢＴにＲＣスナバ回路を付加することにより、ターンオンタイミングがずれた場合の電圧アンバランスによる過電圧印加およびそれによる素子破壊を防ぐことができるが、許容可能なターンオンタイミングの時間差を大きくしようとすると、付加するスナバのコンデンサ容量を大きくしなければならず、そうすると発生損失が増大するために抵抗Ｒの形状が大きくなり、装置全体も大きくなるなどの問題が生じる。
したがって、この発明の課題は、電力変換装置の各アームを構成する電圧駆動型半導体素子に対し逆並列接続されるフリーホイーリングダイオードのサージ電圧を抑制し、電圧駆動型半導体素子のターンオン損失を低減することにある。 When using IGBTs connected in series, as described above, by adding an RC snubber circuit to each IGBT, it is possible to prevent overvoltage application due to voltage imbalance when the turn-on timing is deviated and element destruction due to this. If an attempt is made to increase the time difference between allowable turn-on timings, the capacitor capacity of the added snubber must be increased, and as a result, the generated loss increases, so that the shape of the resistor R increases and the overall device also increases. Problem arises.
Therefore, an object of the present invention is to suppress the surge voltage of a freewheeling diode connected in reverse parallel to the voltage-driven semiconductor element constituting each arm of the power conversion device, and to reduce the turn-on loss of the voltage-driven semiconductor element. There is to do.

このような課題を解決するため、請求項1の発明では、電力変換装置の各アームに接続される電圧駆動型半導体素子をそれぞれオン，オフ駆動するためのゲート駆動装置であって、
前記電圧駆動型半導体素子を第１の抵抗値で駆動する第１の駆動部と、この第１の駆動部から所定の時間だけ遅延して動作し前記第１の抵抗値よりも低い第２の抵抗値で電圧駆動型半導体素子を駆動する第２の駆動部とを備え、前記電圧駆動型半導体素子と逆並列に接続されるフリーホイーリングダイオード逆回復時の低電流域では前記第１の駆動部により、その高電流域では前記第２の駆動部により電圧駆動型半導体素子をターンオンさせることを特徴とする。
この請求項1の発明においては、前記各アームに接続される電圧駆動型半導体素子を複数個とすることができる（請求項２の発明）。 In order to solve such a problem, the invention of claim 1 is a gate drive device for driving on and off each of the voltage driven semiconductor elements connected to each arm of the power conversion device,
A first driving unit that drives the voltage-driven semiconductor element with a first resistance value, and a second driving unit that operates with a delay of a predetermined time from the first driving unit and is lower than the first resistance value. And a second driving unit that drives the voltage-driven semiconductor element with a resistance value, and the first driving is performed in a low current region during reverse recovery of a freewheeling diode connected in reverse parallel to the voltage-driven semiconductor element. The voltage driving type semiconductor device is turned on by the second driving unit in the high current region.
In the invention of claim 1, a plurality of voltage-driven semiconductor elements connected to each arm can be provided (invention of claim 2).

この発明によれば、電力変換装置の各アームに接続される素子の数に関わらず、ＦＷＤの低電流逆回復時に発生するサージ電圧が抑制されるだけでなく、ターンオン損失を増加させることなく過電圧による素子破壊から、ＩＧＢＴ等の電圧駆動型形素子を保護することが可能となる。   According to the present invention, regardless of the number of elements connected to each arm of the power converter, not only the surge voltage generated at the low current reverse recovery of the FWD is suppressed, but also the overvoltage without increasing the turn-on loss. It is possible to protect a voltage driven type element such as an IGBT from element destruction due to.

この発明の実施の形態を示す構成図である。It is a block diagram which shows embodiment of this invention. 図１の動作を説明するための波形図である。It is a wave form diagram for demonstrating the operation | movement of FIG. チョッパ回路の従来例を示す構成図である。It is a block diagram which shows the prior art example of a chopper circuit. ゲート駆動装置の従来例を示す回路図である。It is a circuit diagram which shows the prior art example of a gate drive device. 図４の動作説明図である。It is operation | movement explanatory drawing of FIG. 図５の要部拡大図である。It is a principal part enlarged view of FIG. 素子直列接続式電力変換装置の１相分を示す回路図である。It is a circuit diagram which shows one phase part of an element serial connection type power converter device. 図７の逆回復時の動作説明図である。It is operation | movement explanatory drawing at the time of reverse recovery of FIG. 図７電圧アンバランス動作説明図である。7 is an explanatory diagram of voltage unbalance operation.

図１はこの発明の実施の形態を示す構成図である。
これは、ＦＷＤ逆回復時のサージ電圧に対処するためのもので、図４に示す従来のゲート駆動装置に対し、抵抗Ｒ，コンデンサＣからなる遅延回路、抵抗Ｒｇ（ｏｎ）１およびトランジスタＴＲ１０を付加して構成される。
したがって、インターフェイス回路ＩＦを介してＴＲ１をオンさせると、まず抵抗Ｒｇ（ｏｎ）を介してＩＧＢＴのゲートが駆動される。その後、遅延回路のＣＲ時定数で決まる一定時間が経過するとＴＲ１０がオンし、これによりＩＧＢＴのゲートは、抵抗Ｒｇ（ｏｎ）と抵抗Ｒｇ（ｏｎ）１の並列抵抗により駆動される。このとき、並列抵抗値は抵抗Ｒｇ（ｏｎ）よりも小さくなるので、このゲート駆動装置を用いれば、ＩＧＢＴのゲートは最初は高抵抗で、一定時間後は低抵抗で駆動されることになる。なお、トランジスタＴＲ２側の遅延回路は、ＴＲ１側で遅延させた分だけターンオフタイミングを調整するためのものである。 FIG. 1 is a block diagram showing an embodiment of the present invention.
This is for coping with a surge voltage at the time of reverse recovery of FWD. Compared to the conventional gate driving device shown in FIG. 4, a delay circuit comprising a resistor R and a capacitor C, a resistor Rg (on) 1 and a transistor TR10 are provided. It is configured by adding.
Therefore, when TR1 is turned on via the interface circuit IF, the gate of the IGBT is first driven via the resistor Rg (on). Thereafter, when a certain time determined by the CR time constant of the delay circuit elapses, TR10 is turned on, whereby the gate of the IGBT is driven by the parallel resistance of the resistor Rg (on) and the resistor Rg (on) 1. At this time, since the parallel resistance value is smaller than the resistance Rg (on), if this gate driving device is used, the gate of the IGBT is driven with a high resistance at the beginning and with a low resistance after a certain time. The delay circuit on the transistor TR2 side is for adjusting the turn-off timing by the amount delayed on the TR1 side.

図２は図１の動作を説明するための波形図である。
図１のゲート駆動装置が先の図３に示すＧＤＵ２に対応するものとし、インターフェイス回路ＩＦを介してＴＲ１をオンとしＩＧＢＴ２を動作させる場合、図２のＧＤＵ２波形に示すように、ＦＷＤ１の低電流逆回復時の期間ｔ１までは高抵抗で駆動し、ＩＧＢＴ２側で電圧を保持することでＦＷＤ１側のサージ電圧を抑制する。また、大電流逆回復時である期間ｔ２では低抵抗で駆動することによりターンオン時間を早め、ターンオン損失を低減するようにしている。その結果、ＩＧＢＴ２のコレクタ−エミッタ間電圧，ＦＷＤ１電圧，電流波形は図示のようになり、図５，６の場合に比べてサージ電圧が抑制されていることが分かる。なお、ＩＧＢＴ２のコレクタ−エミッタ間電圧，ＦＷＤ１電圧，電流波形は実線で大電流時の動作を、また、点線で低電流時の動作を示している。 FIG. 2 is a waveform diagram for explaining the operation of FIG.
When the gate driver of FIG. 1 corresponds to the GDU2 shown in FIG. 3 and when the TR1 is turned on and the IGBT 2 is operated via the interface circuit IF, as shown in the GDU2 waveform of FIG. It drives by high resistance until the period t1 at the time of reverse recovery, and suppresses the surge voltage on the FWD1 side by holding the voltage on the IGBT2 side. In the period t2, which is the time of reverse recovery of a large current, the turn-on time is shortened by driving with a low resistance, and the turn-on loss is reduced. As a result, the collector-emitter voltage, the FWD1 voltage, and the current waveform of the IGBT 2 are as shown in the figure, and it can be seen that the surge voltage is suppressed as compared with the cases of FIGS. Note that the collector-emitter voltage, the FWD1 voltage, and the current waveform of the IGBT 2 indicate the operation at a large current with a solid line and the operation at a low current with a dotted line.

以上は、図３の如きアームの素子が１つの場合であるが、図７のようにアームの素子が複数の場合も上記と同様に、図１に示すゲート駆動装置により最初は高抵抗で駆動し、一定時間後は低抵抗で駆動することにより、サージ電圧を抑制しターンオン損失を低減させることが可能となる。このときの様子を示すのが図８で、ゲート駆動装置ＧＤＵ３，４で下アーム素子ＩＧＢＴ３，４を動作させるときの上アームのＦＷＤの逆回復時にＩＧＢＴ１，２に印加される電圧波形を示している。すなわち、Δｔだけ早く逆回復するＩＧＢＴ２側の電圧は、ＩＧＢＴ１側で分担する電圧が重畳し、点線で示すようにさらにサージ電圧が発生し、素子破壊に至る可能性がある。しかし、図１に示すゲート駆動装置を用いた場合の逆回復動作では、実線で示すようにサージ電圧の発生を抑制し、Δｔだけ早く
逆回復するＩＧＢＴ２側の電圧分担を最小限に抑えることが可能となり、素子破壊を防止できることになる。 The above is the case where there is a single element of the arm as shown in FIG. 3. However, in the case where there are a plurality of elements of the arm as shown in FIG. 7, the gate drive device shown in FIG. In addition, by driving with a low resistance after a certain time, the surge voltage can be suppressed and the turn-on loss can be reduced. FIG. 8 shows the state at this time, and shows voltage waveforms applied to the IGBTs 1 and 2 during reverse recovery of the FWD of the upper arm when the lower arm elements IGBT 3 and 4 are operated by the gate drive units GDU 3 and 4. Yes. That is, the voltage on the IGBT 2 side that reversely recovers as early as Δt overlaps with the voltage shared on the IGBT 1 side, and a surge voltage is generated as indicated by the dotted line, which may lead to element destruction. However, in the reverse recovery operation when the gate drive device shown in FIG. 1 is used, the generation of a surge voltage is suppressed as shown by the solid line, and the voltage sharing on the IGBT 2 side that reversely recovers earlier by Δt can be minimized. This makes it possible to prevent element destruction.

ＩＧＢＴ…絶縁ゲートバイポーラトランジスタスイッチ、ＩＦ…インターフェイス回路、Ｒ，Ｒｇ（ｏｎ），Ｒｇ（ｏｎ）１，Ｒｇ（ｏｆｆ）…抵抗、Ｃ…コンデンサ、ＴＲ１，ＴＲ２，ＴＲ１０…トランジスタ、ＧＤＵ…ゲート駆動装置、Ｅｄ…直流電源、ＦＷＤ…フリーホイーリングダイオード。   IGBT ... insulated gate bipolar transistor switch, IF ... interface circuit, R, Rg (on), Rg (on) 1, Rg (off) ... resistor, C ... capacitor, TR1, TR2, TR10 ... transistor, GDU ... gate drive device , Ed: DC power supply, FWD: Free wheeling diode.

Claims (2)

電力変換装置の各アームに接続される電圧駆動型半導体素子をそれぞれオン，オフ駆動するためのゲート駆動装置であって、
前記電圧駆動型半導体素子を第１の抵抗値で駆動する第１の駆動部と、この第１の駆動部から所定の時間だけ遅延して動作し前記第１の抵抗値よりも低い第２の抵抗値で電圧駆動型半導体素子を駆動する第２の駆動部とを備え、前記電圧駆動型半導体素子と逆並列に接続されるフリーホイーリングダイオード逆回復時の低電流域では前記第１の駆動部により、その高電流域では前記第２の駆動部により電圧駆動型半導体素子をターンオンさせることを特徴とする電圧駆動型半導体素子のゲート駆動装置。 A gate driving device for driving on and off a voltage-driven semiconductor element connected to each arm of a power converter,
A first driving unit that drives the voltage-driven semiconductor element with a first resistance value, and a second driving unit that operates with a delay of a predetermined time from the first driving unit and is lower than the first resistance value. And a second driving unit that drives the voltage-driven semiconductor element with a resistance value, and the first driving is performed in a low current region during reverse recovery of a freewheeling diode connected in reverse parallel to the voltage-driven semiconductor element. The voltage-driven semiconductor element gate drive apparatus is characterized in that the voltage-driven semiconductor element is turned on by the second drive unit in the high current region. 前記各アームに接続される電圧駆動型半導体素子を複数個とすることを特徴とする電圧駆動型半導体素子のゲート駆動装置。 A gate drive device for a voltage-driven semiconductor element, comprising a plurality of voltage-driven semiconductor elements connected to each arm.
JP2009244730A 1999-08-10 2009-10-23 Gate driving device of voltage driving type semiconductor device Pending JP2010022190A (en)

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KR101261944B1 (en) 2010-09-17 2013-05-09 기아자동차주식회사 Inverter control system
KR101907687B1 (en) 2017-07-03 2018-10-12 현대오트론 주식회사 Insulated gate bipolar mode transistor gate driver

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KR101261944B1 (en) 2010-09-17 2013-05-09 기아자동차주식회사 Inverter control system
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US8866515B2 (en) 2011-06-02 2014-10-21 Toyota Jidosha Kabushiki Kaisha Drive unit for driving voltage-driven element
KR101907687B1 (en) 2017-07-03 2018-10-12 현대오트론 주식회사 Insulated gate bipolar mode transistor gate driver

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